JAIDEV EDUCATION SOCIETYS

J D COLLEGE OF ENGINEERING & MANAGEMENT, NAGPUR

Department of Electronics / Electronics Telecommunication Engineering
Expert in Expertise
Session: 2017-18 (ODD)

Date: 13/06/2017
Name of Faculty: Prof. Vaibhav P. Choudhari

Sem/ Branch: 6th Sem. ETC A Subject: Digital Communication

Topic Tentative Actual Lecture Unit Topic to be covered Remark HOD

Code Date Date No. Sign
1. 23.06 I Introduction
2. 24.06 I VLSI circuit concept
3. 27.06 I Approach to integrated system design using
Microprocessors
4. 30.06 I Bus concepts
5. 1.07 I Address, Data and control
6. 3.07 I Organization of computer with MPU
7. 4.07 I Bits/ Byts / Words/ Long wards - their ranges
accuracy and precision.
8. 7.07 I Memory organization
9. 8.07 I Linear / Absolute decoding.
10. 10.07 II Introduction to Intel's 8085A
11. 11.07 II Architecture description
12. 14.07 II Architecture description
13. 15.07 II software instructions
14. 17.07 II software instructions
15. 18.07 II software instructions
16. 21.07 II Address mode- advantages
17. 22.07 II Timing diagrams assess
18. 24.07 II Timing diagrams assess
19. 25.07 II Assemblers and Dissemblers
20. 28.07 III Flag structure
21. 29.07 III concept of PSW
22. 31.07 III stacks and subroutines
23. 04.08 III simple and Nested
24. 05.08 III PUSH, POP instructions
25. 07.08 III CALL/RETURN instruction
26. 08.08 III Stack manipulations
27. 11.08 III simple programs
28. 12.08 III simple programs
29. 14.08 IV Interrupts - Concept
30. 18.08 IV Interrupts structure in 8085
31. 19.08 IV Interrupts structure in 8085
32. 21.08 IV Interrupt services routines
33. 22.08 IV Advanced instructions
34. 26.08 IV Programming of 8085A.
35. 28.08 IV Programming of 8085A.
36. 29.08 V Method of data transfer-serial
37. 01.09 V Method of data transfer- parallel,
38. 04.09 V Method of data transfer -synchronous
39. 05.09 V Method of data transfer -asynchronous,
40. 08.09 V IN/OUT instructions
41. 09.09 V Timing diagrams,
42. 11.09 V simple hardware interface to 8085 of standard
Latches/Buffers
43. 12.09 V simple hardware interface to 8085 of standard
Keys/display devices as I/O ports.
44. 15.09 V Handshaking concept
45. 16.09 V Architecture and interface of 8255 to 8085
46. 18.09 V Architecture and interface of 8253 to 8085
47. 19.09 VI Hardware considerations
48. 22.09 VI bus contention
49. 23.09 VI Slow memory interfacing
50. 25.09 VI complete signal description of 8085
51. 26.09 VI Multiplexed Key board interface
52. 26.09 VI Multiplexed Key Display interface
53. 29.09 VI assembler directives
54. 29.09 VI General awareness about micro computer
system related products.