RDS: Realization of Digital Systems and DSP Winter Term 2016-2017

Seminar 1: Sampling I
1. Sampling Basics
a) Why is a sample and hold circuit necessary?

b) What is the sampling theorem?

c) An analog audio signal is sampled with = 8 by an AD converter. The input signal

consists of four frequencies: 1 = 0.5 ; 2 = 3 ; 3 = 5.5 ; 4 = 7
Behind the DA converter there is a post filter with the half sampling frequency. What
frequencies are there behind the post filter?

8 kHz 8 kHz

ADC DAC Post filter

2. AD Converter
An ideal analog to digital converter (ADC) has a nominal input range of [-10 V ... +10 V]. The
digital value is interpreted as a positive integer value.
a) Which resolution (bit) of the ADC is required to achieve an accuracy (quantization error) of at
least 2.5 mV ?

b) Calculate the actual quantization error for the determined bit resolution.

c) Calculate the integer code for the input voltage of -3V.

d) Calculate the range of input voltage corresponding to the integer code.

e) Calculate the corresponding binary code.

3. Quantization noise
a) How can the quantization noise be calculated? Give a formula and explain using the
definition of SNR. What is the difference between sinusoidal, saw-tooth and (analog) video
signals respectively?

b) Assume a sinusoidal signal is converted with a 12-bit ADC. Calculate the SNR in dB.
 RDS: Realization of Digital Systems and DSP Winter Term 2016/2017

Seminar 2: Sampling II

1. AD Converter
A sinusoidal signal is converted using an ideal ADC. The input signal has an SNR of 60dB
The noise figure (NF), i.e. the degradation of the logarithmic SNR of the input compared to the
output signal, should be less than 3dB.

a) Calculate the noise factor F.

b) Calculate the necessary number of bits to achieve the desired performance.

2. Aliasing
A sinusoidal signal x(t) is given by the following function:
() = 3 (2 300 + / 3) + 8 (2 800 / 5)

The signal is sampled at = 500. Show that aliasing occurs.

3. Sampling of Bandpass Signals

Suppose we have a non-baseband signal with frequencies between = 14 and =
18 . We want to sample the signal using an ADC.

a) Determine the bandwidth and the center frequency of the signal. Draw the spectrum.

b) Which is the minimum sampling frequency required if no replicas between =

14 and + = +14 are allowed?

c) What happens if we allow harmless replicas between = 14 and + =

+14 ? Calculate all possible sampling frequencies.

d) Draw the spectrum for a sampling frequency of = 2 .

 RDS: Realization of Digital Systems and DSP Winter Term 2016/2017

Seminar 3: Dual-Slope ADC

1. Dual-Slope Analog-to-Digital Converter

Consider the dual-slope ADC shown in the figure below. The dual-slope ADC belongs to the group
of integrating AD converters.

a) Explain the working principle of the dual-slope ADC.

b) Calculate the output voltage uo(t) of the (inverting) integrator dependent on the input
voltage ui(t).

c) How can the unknown input voltage Ux be calculated from the reverence voltage Uref and the
counter values N1 and Nx?

d) The resolution of the measured input voltage depends on the number of counter values N1
and Nx. Calculate a counter value N1 to be able to measure an input voltage Ux = -0.2 Uref
with an accuracy of 0.1%.

e) The input signal is superimposed by a sinusoid disturb signal of 50 Hz. How does this affect
the measurement? How can it be eliminated? Calculate the counter frequency fref.

f) How do changes of components R, C and fref affect the accuracy of the dual-slope ADC?
Name advantages and disadvantages of the dual-slope ADC.
 RDS: Realization of Digital Systems and DSP Winter Term 2016/2017

Seminar 4: Sigma-Delta ADC

1. Behavior of an idealized Sigma-Delta ADC

Figure 1 shows an idealized implementation of first-order Sigma-Delta (-) A/D converter.

Figure 1: Implementation of a First-Order Sigma-Delta ADC

Source: http://www.analog.com/media/en/training-seminars/tutorials/MT-023.pdf

a) Explain the principle of operation.

b) Now assume a reference voltage VREF of 5.0 V. Calculate the bit stream at the output of the
comparator (1-bit ADC) (D) for a constant (DC) input voltage of VIN = +3.0 V.

c) How can the measured voltage be calculated from the bit pattern?

d) How does the output bit pattern (D) look like for VIN = - VREF, VIN = 0 and VIN = + VREF
respectively?

e) What happens if VIN > VREF?

 RDS: Realization of Digital Systems and DSP Winter Term 2016/2017

2. Quantization noise of a Sigma-Delta ADC

A Sigma-Delta ADC for an audio application should be developed. The audio signal has a
bandwidth of = 24 . The sampling frequency is = 48 .

a) The Sigma-Delta converter should be a 2nd order converter. Calculate the oversampling
frequency necessary to reach a 16-bit resolution.

b) How does the oversampling frequency change if a 3rd order ADC is used?

c) Now the bandwidth is limited to 16 . How does this affect the quantization noise, if the
same oversampling frequency is used? What is the oversampling frequency necessary to
reach 16-bit resolution?
 RDS: Realization of Digital Systems and DSP Winter Term 2016/2017

Seminar 5: Digital Filters I

1. Digital Filter Basics

The following tasks test your theoretical knowledge gained from the lecture.

a.) Are the given systems linear?

[] = 2 []
[] = 2 []
[] = |[]|

b.) Are the given systems time-invariant?

[] = 2 []
[] = []

c.) Determine the output y[n] of a system with the impulse response function h[n]:

, 0; 0 1
[] = {
0,

and with the input signal:

1, 0
[] = () = {
0,

d.) Characterize the following filter:

[] = 0.5 [] 0.5 [ 2]

e.) Determine the impulse response h[n] for the following filter:

[] = 2 [] + 0.5 [ 2] + 0.5 [ 1]
 RDS: Realization of Digital Systems and DSP Winter Term 2016/2017

2. Representation in the z-domain

a.) Some transfer functions with their poles in the z-domain illustrated below. For each of them,
decide whether it is stable, unstable and/or oscillating.

Im Im Im Im
z
x x

x x
Re Re Re
x x

b.) Illustrate the poles and zeros in z-domain of the below transfer function. Is it stable?

() 2 74 + 38
() = = 2 11
() 6 + 12

3. Block Diagrams

a.) Determine the difference equation and the block diagram of a system with the given transfer
function:
(+ 1 )
() = 1 1 2

b.) Determine the transfer function based on the following block diagram:

x[n] T T

a b c

+ + + y[n]

d
T T
 RDS: Realization of Digital Systems and DSP Winter Term 2016/2017

Seminar 6: Digital Filters II

1. Determination of a system from the system function

Consider a filter with the following system function:

3 + 2 2 + 3 + 4
() =
10 3
a.) What kind of system is this?

b.) Does this filter have a linear phase response?

c.) Determine the difference equation.

2. Determination of a system from the step response

Consider a filter with the following step response:

[] = {1, 3, 4, 8, 9, 13, 14, 16, 17, 17, 17, 17, }

a.) Is this an IIR or FIR filter? Does this system have a linear phase response?

b.) Determine the group delay of this filter.

3. Recursive Filter

Consider a recursive filter with the sampling period and a system function ():

0 + 1 1
() =
1 + 1 1

a.) Determine the transfer function ()

b.) Let 0 = 0.4. Determine the remaining coefficients 1 and 1 , if

1
(0) = 0 ; (2 ) = 40 .

c.) Draw a possible implementation of this filter.

d.) Determine the output sequence [] for the input sequence [] with n = { 0 ... 6 }

[] = { 1, 1, 1, 1, 1, 1, 1, }
 RDS: Realization of Digital Systems and DSP Winter Term 2016/2017

Seminar 7: Digital Filters III

1. Filter types

Consider the following difference equations. Name the filter types and determine the system
functions. Draw the corresponding block diagrams.

a.) [] = [ 2]

b.) [] = [] + 1 [ 1] + 2 [ 2]

c.) [] = [] + 0.5 [ 1]

1 1 1
d.) [] = 4 [] + 2 [ 1] + 4 [ 2]

2. FIR High Pass

Consider the following FIR high pass of 1st order (0 = 0.5; 1 = 0.5):

x[n]

b1 b0

z-1 + y[n]

Determine the frequency response, the cutoff frequency, the phase response and the group delay.