Emulating Large Complex SOC Devices in A Xilinx

Emulating Large
Complex SOC Devices in a

Xilinx
FPGA Environment
Martin Terry
Mike Dunk
22nd February 2012
Development History
Recomp EU funded development program.

Reduced Certification Costs Using Trusted Multi-core Platforms
Provide reference designs and platform architectures
Cost-effective certification and re-certification of mixed-
criticality, component based, multi core systems
10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 2

Board Development Consideration
Cost Vs Performance vs design effort.

Single large FPGA vs several smaller FPGAs with design
partitioning
Design Size vs FPGA logic density
Increase in design size met by increase in FPGA density.
Clocking Consideration
Multiple Clock domains, clock muxing, clock gating.
Logic density vs. Clock routing and skew problems
Internal / External RAM
Xilinx Virtex 6 XC6V760 chosen as Platform FPGA

Single FPGA with overhead for future design expansion

FPGA Design Consideration
Migration from development database

Minimal design modification
Verification and validation in line with SOC development
Reuse of design verification test vectors
Support for cyclical development, update and release of IP

blocks
Alignment of documentation
Support from SOC design teams during development and

debug
Early visibility of end product design

Target Design Structure
Xilinx Target FPGA Hierarchical

Design
Core Core
1 2 Multiple Cores,
peripherals and
buses
Ext Crossbar Interconnect Ethernet
Clock
Memory controller
Generation Multiple Clock
Interface Interface
Bridge Domains
Continual
Peripheral Bus update of
blocks during
Peripheral Peripheral Peripheral Peripheral Peripheral
Development
lifecycle
Synopsis Pad Models

Key Development Stages
Database preparation
RTL modification and Update
RTL simulation
Synthesis
Layout
Gate Level Simulation
PCB and FPGA validation

Database Preparation
Infineon Macroprep consistancy checker

In house tool for IP design release used by all design teams
Generates design database structure
Generates ordered compile list as Infineon standard procedure
Ordered compile list parsing used for FPGA compilation

Perl Scripts used for automatic parsing of release scripts
Listed modifications inserted during parsing
Generating tcl scripts for synthesis and simulation
Tcl scripts can be used in interactive or batch modes during

simulation and synthesis

RTL Modification and Update
Pad Model conversion

Synopsis .lib to verilog model conversion
IP block script generation

File identification from release scripts from SOC design
Tracking and insertion of modifications for FPGA synthesis
Design Top level modification

Single top level RTL compile script.
Clock tree reduction.
Black Box generation for IP removal
System Level test bench Integration

validation of modified RTL using core and system test
regression suite.
Pad Model Conversion
Pad Models Stored in synopsis .Lib format

Synplify lib2syn used to generate verilog equivalent
Verilog Models stored for top level synthesis
Conversion process scripted for batch generation

Black Box Generation
Black Box generation included for

Removal of analogue simulation models
Removal of non distributable Licensed IP blocks
Black box generation integrated into system level simulation

Allows for stepped release of IP blocks
Includes in house macro language to steer blackbox

generation, e.g. Constant declaration, forced output levels,
library inclusion....
For FPGA
Can be reused to generate a database of Black box models

Simulation, Synthesis and Layout
Modifications for FPGA synthesis always checked in simulation

Current Simulator Modelsim
Synthesis generates mapped a verilog model for simulation

Synthesis using Synplify Pro
Gated Clock fixing enabled
Moves clock gating from clock tree to register enable logic
Place and route generates a timing annotated verilog model

Place and Route using Xilinx ISE tools
Generated models used to validate functionality using a test

suite of core and system level test programs.

Gate Level Simulation and Comparison
Synthesis and Layout mangles hierarchy and net names

Un constrained I/O leads to board level timing failures
Novas Verdi tool used for comparison of RTL and gate

simulations
VCD files generated for RTL and Gate Sims using Modelsim
Verdi behavioural Analysis tool identifies mapping between

RTL and gate level netlist
Identifies root cause of X propagation
Comparison of timing paths related to the design RTL
Future flow enhancement

Inclusion of formal equivalence checking between RTL and
gate net lists.

Overall Development Flow
Core Test
Generation
Core Level Tests Core Test Library
RTL Database Modifications Datbase
System
Test
Generation
Compilation System Tests System Test Libraries
Script Simulation
Generation
Synthesis
System Test ELF File Core Test ELF file
Script Synthesis
Generation
Mapped
Verilog Model
Software Debugger
Regression
Test Results
Back Anotated
Place and Route Verilog Model
FPGA
Development Board
FPGA Image File

Infineon FPGA Development Platform
4Mx36 4Mx36
SRAM SRAM FPGA
Ethernet ADC
Virtex XC6VLX760
MAC
External Interfaces
Switches
GPIO Connectors
Flexray
Level Shifters
I/O level shifting and

VIRTEX 6 expansion
TFT
LEDs
FPGA External Analogue

connectivity
USB FTDI
Ethernet, Can bus and
CAN
flexray, TFT
Power Supply Monitoring and control

FPGA Programming
USB FTDI Monitoring
and Control OLED
Brownout detection
Switches (Tricore) lockup detection

(32bit uP) SD Card
System reset

Infineon FPGA Development Platform
Designed in
conjunction with
Hitex UK
Branded as
Meridian FPGA
development
Platform
http://www.recomp
.eu/meridian/

Infineon Debug Access Server (DAS)
Provides common
Host PC 1 Host PC 2 interface for multi core
programming, debug
Tool 1 Tool 1 Tool 1 Tool 1 and calibration
DAS DAS DAS DAS
DLL DLL DLL DLL
Easy connection via USB

UDAS
Server to FPGA board
Network
USB
USB Munich Distributed/remote

debug via network
FPGA
PLATFORM
Bristol
In System Testing
All tests generated used during simulation target FPGA Hardware

Reuse of simulation regression suite for hardware validation
Using ELF files generated during simulation stored for

hardware testing
Core and System tests accelerated as a regression
Debugger scripting used to batch run test
All test store a pass fail indication
Results collated for overall pass rate
9,000 test run in ~20 minutes
System level benchmarking enhances validation

System level OS testing
uCOS, Elinux
Simulation, synthesis and Test Times
Simulation
Single RTL test ~40 seconds
RTL test Regression ~ 4 hours for 9000 test on single compute

node
Gate level single Test ~ 2 hours
Synthesis an Layout
Synplify Pro compilation and map ~4 hours on single compute
node
Xilinx Layout ~ 5 hours
In system regression run ~20 minutes for 9000 tests

Serial Load, run, analyse @ 15Mhz
Possible enhancements for parallel load and run to be

investigated
Benefits of an FPGA development Platform
Tool development
Early visibility of a multi core SOC design
Early delivery of a multi core debugger
Early delivery of example drivers for IP blocks
System level configuration example for software developers
Early understanding of system architecture
Early porting of existing software to a multi core platform

Performance Evaluation
Functional acceleration of pre silicon validation
Prevention of wasted mask sets (multi millions of Euros)

Emulating Large Complex SOC Devices in A Xilinx

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Emulating Large

Complex SOC Devices in a

Recomp EU funded development program.

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 2

Cost Vs Performance vs design effort.

Logic density vs. Clock routing and skew problems

Internal / External RAM

Xilinx Virtex 6 XC6V760 chosen as Platform FPGA

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 3

Migration from development database

Verification and validation in line with SOC development

Reuse of design verification test vectors

Support for cyclical development, update and release of IP

Support from SOC design teams during development and

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 4

Xilinx Target FPGA Hierarchical

Synopsis Pad Models

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 5

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 6

Infineon Macroprep consistancy checker

Generates design database structure

Generates ordered compile list as Infineon standard procedure

Ordered compile list parsing used for FPGA compilation

Generating tcl scripts for synthesis and simulation

Tcl scripts can be used in interactive or batch modes during

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 7

Pad Model conversion

IP block script generation

Tracking and insertion of modifications for FPGA synthesis

Design Top level modification

Black Box generation for IP removal

System Level test bench Integration

Pad Models Stored in synopsis .Lib format

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 9

Black Box generation included for

Removal of non distributable Licensed IP blocks

Black box generation integrated into system level simulation

Includes in house macro language to steer blackbox

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 10

Modifications for FPGA synthesis always checked in simulation

Synthesis generates mapped a verilog model for simulation

Gated Clock fixing enabled

Moves clock gating from clock tree to register enable logic

Place and route generates a timing annotated verilog model

Generated models used to validate functionality using a test

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 11

Synthesis and Layout mangles hierarchy and net names

Novas Verdi tool used for comparison of RTL and gate

Verdi behavioural Analysis tool identifies mapping between

Comparison of timing paths related to the design RTL

Future flow enhancement

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 12

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 13

I/O level shifting and

FPGA External Analogue

Power Supply Monitoring and control

Switches (Tricore) lockup detection

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 14

10.02.2010 Copyright Infineon Technologies 2010. All rights reserved. Page 15

Easy connection via USB

USB Munich Distributed/remote

All tests generated used during simulation target FPGA Hardware

Using ELF files generated during simulation stored for