//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:29:52 06/28/2017
// Design Name:
// Module Name: Traffic_Controller
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Traffic_Controller(
Reset,
Sensor,
Walk_Request,
Reprogram,
System_clk,
Time_Value,
Time_Param_Sel,
LED_out
);
input Reset,Sensor,Walk_Request,Reprogram,System_clk;
input [1:0] Time_Param_Sel;
input [3:0] Time_Value;
output [6:0] LED_out;
//
wire
glbl_rst,sensor_sync,prog_sync,walk_req,w_sync,wreg_rst,start_timer,end_timer,clk_s
;
wire [3:0] tim_out;
wire [1:0] inter_addr;
);
Timer_Parameter Tim_Param (
.Prog_Sync(prog_sync),
.Reset_Sync(glb_rst),
.interval_addr(intr_addr),
.Time_Param_Sel(Time_Param_Sel),
.Time_Value(Time_Value),
.System_clk(System_clk),
.Value(tim_out)
);
Timer timer (
.Value(tim_out),
.start_timer(start_timer),
.clk(clk_s),
.end_timer(end_timer)
);
Divider div (
.System_clk(System_clk),
.enable_signal(clk_s)
);
endmodule
);
input System_clk,Reset,Walk_req,Reprogram,Sensor;
output reg Global_rst,Sensor_Sync,Walk_Sync,Reprog_Sync;
initial begin
Global_rst<=0;
Sensor_Sync <= 0;
Walk_Sync <=0;
Reprog_Sync <=0;
end
always @ (posedge System_clk)begin
Global_rst<=Reset;
Sensor_Sync <= Sensor;
Walk_Sync <=Walk_req;
Reprog_Sync <= Reprogram;
end
endmodule
input Walk_Req,System_clk,end_Reset;
output reg Walk;
always @(posedge System_clk,posedge end_Reset)
begin
if (end_Reset==1)
Walk <= 0;
else if (Walk_Req)
Walk <= Walk_Req;
end
endmodule
);
input Reset_Sync,WR,Prog_Sync,end_timer,System_clk,Sensor;
output reg start_timer,Walk_Reset;
output [6:0] LED;
output reg [1:0] address ;
reg [6:0] LED;
parameter GR1 = 4'd0,
GR2 = 4'd1,
YR1 = 4'd2,
RG1 = 4'd3,
// RG2 = 4'd4,
RY1 = 4'd5,
RRW1 = 4'd6,
RRS1 = 4'd7;
reg [3:0] state,next_state=GR1;
reg flag;
always@(posedge System_clk,posedge Reset_Sync,posedge Prog_Sync)begin
if (Reset_Sync==1 | Prog_Sync==1)
state = GR1;
else
state =next_state;
end
always@(state,WR,end_timer,Sensor)begin
LED <= 7'd0;
Walk_Reset <= 1'b0;
start_timer <= 1'b0;
address <= 1'b0;
next_state <= state;
flag <=0;
case (state)
GR1:begin
start_timer <= 1'd1;
address <= 2'd0;
LED <= 7'b0011000;
if (end_timer)begin
if (Sensor)begin
next_state <= RRS1;
flag <=1;
end else
next_state <= GR2;
end
end
GR2:begin
start_timer <= 1'd1;
address <= 2'd0;
LED <= 7'b0011000;
if (end_timer)
next_state <= YR1;
end
YR1:begin
start_timer <= 1'd1;
address <= 2'd2;
LED <= 7'b0101000;
if(end_timer) begin
if(WR)
next_state <= RRW1;
else
next_state <= RG1;
end
end
RG1:begin
start_timer <= 1'd1;
address <= 2'd0;
LED <= 7'b1000010;
if (end_timer)begin
if(Sensor)
next_state <= RRS1;
else
next_state <= RY1;
end
end
RY1:begin
start_timer <= 1'd1;
address <= 2'd2;
LED <= 7'b1000100;
if (end_timer)
next_state <= GR1;
end
RRS1:begin
start_timer <= 1'd1;
address <= 2'd2;
if (flag)
LED <= 7'b0011000;
else
LED <= 7'b1000010;
if (end_timer)begin
if (flag)
next_state <= YR1;
else
next_state <= RY1;
end
end
RRW1:begin
start_timer <= 1'd1;
address <= 2'd1;
LED <= 7'b0000001;
//WR = 0;
if(end_timer)
next_state <= YR1;
end
default:next_state <= GR1;
endcase
end
endmodule
);
input Prog_Sync,System_clk,Reset_Sync;
input [1:0]interval_addr,Time_Param_Sel;
input [3:0] Time_Value;
output reg [3:0] Value;
end
initial begin
memory[0]=4'b0110;
memory[1] =4'b0011;
memory [2] =4'b0010;
//memory [3] = 4'b0000;
end
endmodule
initial begin
counter <=0;
end_timer <= 0;
end
end
endmodule
);
input System_clk;
output reg enable_signal;
parameter num_clk=(500);//assuming siystem clock is 100MHz
reg [31:0]counter;
initial begin
counter <= 0;
enable_signal <= 0;
end
always @(posedge System_clk) begin
counter <= counter+1;
$display("%d",counter);
if(counter==num_clk)begin
enable_signal = ~enable_signal;
counter <= 0;
end
end
endmodule