K.K.

WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK

Department of Electronics Engineering

Doc. No.: VLSI/VLSI/EW/GB5 (1)

Date:

Subject: Lab Practice -I (404206) VLSI Design

EXPERIMENT NO: GB-1

AIM: To simulate CMOS Inverter

LEARNING OBJECTIVES:
To prepare layout of CMOS Inverter with and without capacitor, simulate and
also observe Voltage Transfer Characteristics.

EQUIPMENTS REQUIRED: PC with Microwin 3.1 installed .

THEORY:

Logic/circuit Diagram

Operation:
When input is logic 1, PMOS in the pull-up is OFF and NMOS in the pull down is ON.
Hence output is Logic0.
When input is logic 0, PMOS in the pull-up is ON and NMOS in the pull down is OFF.
Hence output is Logic1.

Prepared by Approved by
(Prof. K.Nirmalakumari) H. O. D
 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

Truth Table:

Voltage Transfer Characteristics:

Stick Diagram/Layout:
 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

CMOS Inverter with Capacitive Load

CMOS inverter driving a load capacitance. When the input switches from 1 to 0, the
pMOS transistor turns ON and charges the load to VDD. The energy stored in the
capacitor is

The energy delivered from the power supply is

Observe that only half of the energy from the power supply is stored in the
capacitor. The other half is dissipated (converted to heat) in the pMOS transistor because
the transistor has a voltage across it at the same time a current flows through it. The
power dissipated depends only on the load capacitance, not on the size of the transistor
or the speed at which the gate switches.
When the input switches from 0 back to 1, the pMOS transistor turns OFF and
the nMOS transistor turns ON, discharging the capacitor. The energy stored in the
capacitor is dissipated in the nMOS transistor. No energy is drawn from the power
supply during this transition.

Comment on the response of inverter with and without capacitive load

CONCLUSION:
 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

Doc. No.: VLSI/VLSI/EW/GB5 (2)

Date:

Subject: Lab Practice -I (404206) VLSI Design

EXPERIMENT NO: GB-2

AIM: To simulate NAND, NOR

LEARNING OBJECTIVES:
To prepare CMOS layout of 3-input NAND and NOR gates, simulate and Verify
the output.

EQUIPMENTS REQUIRED: PC with Microwin 3.1 installed .

THEORY:

To prepare layout of 3-input NAND/NOR, simulate and Verify.

Logic/circuit Diagram

Prepared by Approved by
(Prof. K.Nirmalakumari) H. O. D
 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

Operation of 3-input NAND:

When any one of the input is logic 0, one of the PMOS in the pull up is ON and output is
Logic 1(VDD)
Only when all the three inputs are logic1 (A=1, B=1, C=1) then all the pull up transistors
are OFF and all the pull down transistors are ON making output as Logic 0.

Operation of 3-input NOR:

When any one of the input is logic 1, one of the PMOS in the pull up is OFF, NMOS in
the pull down is ON making output as Logic 0.
Only when all the three inputs are logic 0 (A=0, B=0, C=0) then all the pull up
transistors are ON and all the pull down transistors are OFF making output as Logic 1.

TRUTH TABLE:

3-input NAND 3-input NOR

Inputs Output Inputs Output
A B C Y A B C Y
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 1 0 1 0 1 0 0
0 1 1 1 0 1 1 0
1 0 0 1 1 0 0 0
1 0 1 1 1 0 1 0
1 1 0 1 1 1 0 0
1 1 1 0 1 1 1 0

STICK DIAGRAM/LAYOUT OF NAND:

 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

STICK DIAGRAM/LAYOUT OF NOR:

CONCLUSION:
 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

Doc. No.: VLSI/VLSI/EW/GB5 (3)

Date:

Subject: Lab Practice -I (404206) VLSI Design

EXPERIMENT NO: GB-3

AIM: To simulate 2:1 Mux Using CMOS And Transmission Gates(TG)

LEARNING OBJECTIVES: To compare 2:1 MUX using Transmission Gates and

Conventional method by preparing layout and simulation the output.

EQUIPMENTS REQUIRED: PC with Microwin 3.1 installed.

THEORY:
.

Logic/circuit Diagram

2:1 Mux using Conventional Method

Prepared by Approved by
(Prof. K.Nirmalakumari) H. O. D
 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

D0
S Y
D1

S
2:1 Mux using Transmission Gates

OPERATION:
Input D0 is selected when the selection input is Logic 0
Input D1 is selected when the selection input is logic 1.

TRUTH TABLE:

Selection Output
Input(S) (Y)
0 D0
1 D1

STICK DIAGRAM/LAYOUT USING TRANSMISSION GATES:

 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

STICK DIAGRAM/LAYOUT USING LOGIC GATES:

CONCLUSION:
 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

Doc. No.: VLSI/VLSI/EW/GB5 (4)

Date:

Subject: Lab Practice -I (404206) VLSI Design

EXPERIMENT NO: GB-4

AIM: To simulate CMOS combinational logic for minimum four variable inputs.

LEARNING OBJECTIVES:

To prepare layout of equation________________________ using CMOS, simulate and

verify the output.

EQUIPMENTS REQUIRED: PC with Microwin 3.1 installed.

THEORY:
.
Logic/circuit Diagram

Prepared by Approved by
(Prof. K.Nirmalakumari) H. O. D
 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

Operation:
Euler paths are defined by a path that traverses each node in the path, such that each
edge is visited only once. The path is defined by the order of each transistor name.
If the path traverses transistor A then B then C. Then the path name is {A, B, C}. The
Euler path of the Pull up network must be the same as the path of the Pull down
network. Euler paths are not necessarily unique. It may be necessary to redefine the
function to find a Euler path

TRUTH TABLE:

Inputs Output
A B C D E Y
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 0 1
0 0 0 1 1 0
0 0 1 0 0 1
0 0 1 0 1 0
0 0 1 1 0 0
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 0 1 1 0
0 1 1 0 0 1
0 1 1 0 1 0
0 1 1 1 0 0
 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

0 1 1 1 1 0
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 1 0 1
1 0 0 1 1 0
1 0 1 0 0 1
1 0 1 0 1 0
1 0 1 1 0 0
1 0 1 1 1 0
1 1 0 0 0 0
1 1 0 0 1 0
1 1 0 1 0 0
1 1 0 1 1 0
1 1 1 0 0 0
1 1 1 0 1 0
1 1 1 1 0 0
1 1 1 1 1 0

STICK DIAGRAM/LAYOUT:

CONCLUSION:
 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

Doc. No.: VLSI/VLSI/EW/GB5 (5)

Date:

Subject: Lab Practice -I (404206) VLSI Design

EXPERIMENT NO: GB-5

AIM: To simulate CMOS SRAM CELL

LEARNING OBJECTIVES: To prepare layout of SRAM CELL using CMOS,

simulate and verify the output.

EQUIPMENTS REQUIRED: PC with Microwin 3.1 installed.

THEORY:

Logic/circuit Diagram

Prepared by Approved by
(Prof. K.Nirmalakumari) H. O. D
 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

OPERATION:
 K.K.WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH NASHIK
Department of Electronics Engineering

STICK DIAGRAM/LAYOUT:

CONCLUSION: