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Table of Figures............................................................................................................................................................................. 2
Introduction ................................................................................................................................................................................... 3
Overview.................................................................................................................................................................................. 3
Rugged MOSFETs................................................................................................................................................................... 5
Repetitive Pulse..................................................................................................................................................................... 10
Buyer Beware.............................................................................................................................................................................. 12
APPLICATION NOTE
Conclusion .................................................................................................................................................................................. 13
The purpose of this note is to better understand and utilize power MOSFETs, it is important to explore the theory behind
avalanche breakdown and to understand the design and rating of rugged MOSFETs. Several different avalanche ratings are
explained and their usefulness and limitations in design is considered.
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TABLE OF FIGURES
Page
Figure 9 Good Source Contact vs. Bad Source Contact Illustration ................................................................................... 6
Figure 12 Single Pulse Unclamped Inductive Switching Test Circuit Output Waveforms ..................................................... 7
Figure 19 Maximum Avalanche Energy vs. Temperature for Various Drain Currents ............................................................ 9
Figure 20 EAR vs. Tstart for Various Duty Cycles, Single ID ................................................................................................... 10
Figure 21 Typical Avalanche Current vs. Pulsewidth for Various Duty Cycles..................................................................... 11
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INTRODUCTION
Overview
To better understand and utilize power MOSFETs, it is VDS
important to explore the theory behind avalanche
breakdown and to understand the design and rating of
rugged MOSFETs. Several different avalanche ratings are
explained and their usefulness and limitations in design is
considered.
Avalanche Mode Defined
All semiconductor devices are rated for a certain max.
reverse voltage (BVDSS for power MOSFETs). Operation
VGS ID
above this threshold will cause high electric fields in
reversed biased p-n junctions. Due to impact ionization, the
high electric fields create electron-hole pairs that undergo a
multiplication effect leading to increased current. The
reverse current flow through the device causes high power
dissipation, associated temperature rise, and potential
device destruction. Fig. 2 - Flyback Converter Switch Under Avalanche Waveform
Avalanche Occurrences In Industry Applications
Flyback Converter Circuit
Some designers do not allow for avalanche operation; Avalanche
Operation
instead, a voltage derating is maintained between rated
BVDSS and VDD (typically 90 % or less). In such instances,
however, it is not uncommon that greater than planned for
voltage spikes can occur, so even the best designs may VDS
encounter an infrequent avalanche event. One such VGS
example, a flyback converter, is shown in figures 1 to 3.
ID
L leakage
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Increasing RB
Parasitic BJT
being F.B.
E Field
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Rugged MOSFETs
First introduced in the middle 1980s, avalanche rugged
MOSFETs are designed to avoid turning on the parasitic BJT
until very high temperature and/or very high avalanche
current occur. This is achieved by:
Reducing the p+ region resistance with higher doping
diffusion
Optimizing cell/line layout to minimize the length of RB
The net effect is a reduction of RB, and thus the voltage drop
necessary to forward bias the parasitic BJT will occur at
higher current and temperature.
Avalanche rugged MOSFETs are designed to contain no
single consistently weak spot, so avalanche occurs Fig. 8 - Power MOSFET Random Device Failure Spots
uniformly across the device surface until failure occurs
randomly in the active area. Utilizing the parallel design of The risk of manufacturing process or fabrication induced
cells, avalanche current is shared among many cells and weak cell parts is always present. The SEM cross-section
failure will occur at higher current than for designs with a micrograph on the top shows one such example. The source
single weak spot. A power MOSFET which is well designed metal contacts the n+ layer at the near surface, but not the
for ruggedness will only fail when the temperature p+ layer. As a result the BJT base is floating and easily
substantially exceeds rated TJ (max.). triggerable. An example of a good contact is shown on the
bottom. The source metal contacts and shorts the n+ layer
An analysis of various MOSFET devices tested to
to the p+ layer thus supressing the parasitic BJT operation.
destruction indicates that failure spots occur randomly in
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1.00
200 20.00
Linear
IAS Fail
Linear
150 Linear
Linear
100
50
0
0 100 200 300 400 500 600
Temperature (C)
Fig. 10 - IAS at Failure vs. Test Temperature
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Rg D.U.T. +
- VDD
A
IAS
20 V
tp 0.01
VDS
tp
IAS
Fig. 11 - Single Pulse Unclamped Inductive Switching Test Circuit
Fig. 14 - Decoupled VDD Voltage Source Test Circuit Waveforms
From the figure 11 schematic we can calculate the single
pulse avalanche energy (EAS) as: Here a driver FET and recirculation diode are added so that
L x IAS
2
V DS the voltage drop across the inductor during avalanche is
E AS = -------------------------- x --------------------------- (1) equal to the avalanche voltage. With this circuit (neglecting
2 V DS - V DD
the angular ESR in the inductor) the energy can be simply
The measured energy values depend on the avalanche calculated as:
breakdown voltage, which tends to vary during the 1 2
discharge period due to the temperature increase. Also note E AS = --- L x I AS (2)
2
that for low voltage devices VDS - VDD may become quite
A better and more accurate reading of the avalanche energy
small, limiting the use of this circuit since it introduces
can be obtained by measuring instantaneous voltage and
high-test error.
current in the device and integrating as described in the
following equation:
t2
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Gate Voltage
IRFP450,
SiHFP450
Inductor
Charging VDD = 50 V
L = 7 mH VAV
IAS = 14 A
Ipk TJ = 25 C
at 50 s/div.
Drain ID
VAV
Avalanche
Phase
Drain Voltage
Fig. 15 - Typical Simulated Avalanche Waveforms Fig. 16 - IRFP450, SiHFP450 (500 V Rated) Device Avalanche
Waveforms
Note that the peak avalanche voltage VAV can be Further note that V(BR)DSS and VAV are used interchangeably
approximated as 1.3 times the device rating, or 650 V. in this text.
AVALANCHE RATING EAS THERMAL LIMIT APPROACH
Generally, there are three approaches to avalanche rating Single Pulse
devices:
The single pulse avalanche rating (EAS) is based on the
1. Thermal Limit Approach: The device is rated to the assumption that the device is rugged enough to sustain
value(s) of energy, EAS, that causes an increase in avalanche operation under a wide set of conditions
junction temperature up to TJ (max.). EAS avalanche rated
subjection only to not exceeding the maximum allowed
MOSFETs are rated in this manner.
junction temperature. Typically, the avalanche rating on the
2. Statistical Approach: Devices are tested up to the failure datasheet is the value of the energy that increases the
point. The rating is given using statistical tools (e.g., junction temperature from 25 C to TJ (max.), assuming a
average (EAS) - 6 ) applied to the failure distribution. constant case temperature of 25 C and assuming a
Some parts are rated this way and indicated as EAS specified value of ID (usually set at 60 % of ID (25 C).
(tested), generally in addition to the thermally limited
rating. However, some MOSFET suppliers provide only For example, consider the 500 V/32 A device as excerpted
this rating on their datasheets. from the datasheet below,
3. No rating at all.
While the first two approaches provide a value for
avalanche energy, the designer must take care to know
the important differences that are outlined below.
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with the following initial conditions: Now from equation 2 we can calculate
Single pulse avalanche current: IAS = ID = 32 A 1 2 2
E AS = --- L x I AS = 0.5 x 0.87 mH x 32 = 445 mJ
Starting temperature: Tstart = 25 C 2
Inductor value: L = 0.87 mH which agrees with the datasheet value within rounding of the
least significant digit.
To calculate the temperature increase due to the avalanche
power dissipation we utilize a thermal model with Ohms The duration of the avalanche power pulse can be
Law equivalence. The resulting equation follows: calculated, assuming the inductor is discharging with a
constant voltage applied to it, as
T = ZTH x P AV (4)
I pk 32 A
The average power dissipated during avalanche can be t AV L x --------- = 0.87 mH x --------------- 43 s (7)
V AV 650 V
calculated as
The thermal impedance (ZTH) for this pulsewidth can be read
1 V AV x I AS x t AV
P AV = --- --------------------------------------- = 0.5 x 650 V x 32 A = 10 kW (5) from the transient thermal impedance plot provided with the
2 t AV
datasheet, as shown in figure 18.
Avalanche voltage can be estimated as
V AV 1.3 x BV DSS = 1.3 x 500 V = 650 V (6)
0.012
43 s
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Fig. 21 - Typical Avalanche Current vs. Pulsewidth For Various Duty Cycles
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V DD 2
14.5 V
I L = I AR = -------------------------------- = --------------------------------------- = 0.966 A (12) P cond. = I L x R DS(on) x D = (16)
R L + R DS(on) 15 + 10 m 2
= 0.966 A x 10 m x 0.013 = 121 W
I AR x V AV x t AV D = t AV x f = 109 s x 125 Hz = 0.013 (17)
E AR = ---------------------------------------- =
2 (13)
T SS = P ave + P cond. x R + T A =
0.966 A x 52 V x 109 s
= ---------------------------------------------------------------- = 2.74 mJ = 343 mW + 121 W x 50 C/W + 120 C = (18)
2
= 137.2 C
Average avalanche, and conduction power values can be The peak rise in junction temperature due to each avalanche
calculated as pulse is given by
E AR 2.74 mJ T = P AV x Z TH = 25.1 W x 0.18 C/W = 4.5 C (19)
P AV = ---------- = --------------------- = 25.1 W, (14)
t AV 109 s
where the thermal impedance (ZTH) is approximated from
P ave = E AR x f = 2.74 mJ x 125 Hz = 343 mW, (15) the transient thermal impedance plot provided with the
datasheet, as shown in figure 23.
since the avalanche duty cycle can be calculated as
Note that TSS + T = 137.2 C + 4.5 C = 141.7 C < TJ (max.)
The average junction temperature can be calculated as
0.18
109 s
Fig. 23 - Typical Effective Transient Thermal Impedance, Junction-to-Ambient
BUYER BEWARE
Many suppliers rate power MOSFET avalanche capability Example 1
with only a single number in the datasheet and without Pulse:
providing full circuit or test condition details. In such cases,
I AS = 32 A
buyer beware! It is not sufficient to merely compare the
APPLICATION NOTE
L = 0.87 mH
numeric values of avalanche energy which appear in
datasheet tables. The following example will help illustrate Result:
one such pitfall. 1 2
E AS = --- x L x I AS = 445 mJ
2
Since avalanche energy depends on the inductor value and
I pk
starting current, it is possible to have two pulses with the t AV = L x --------------------- 43 s
same energy but different shape provide two different V (AV)DSS
junction temperatures. This phenomenon is illustrated in the Z TH = 0.012 C/W
following examples: T = 120 C
T J = 145 C < T J (max.)
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Example 2 CONCLUSION
Pulse: Vishay applies 3 different classes of avalanche rating:
I AS = 16 A The thermal approach allows single pulse and (where
L = 3.48 mH indicated) repetitive pulse avalanche operation as long as
Result: neither ID (max.) nor rated TJ (max.) are exceeded. Energy
1 2
losses due to avalanche operation can be analyzed as any
E AS = --- x L x I AS = 445 mJ other source of power dissipation. Such thermally rated
2
I pk parts are indicated by Vishay with a rating of EAS and,
t AV = L x --------------------- 86 s more recently, with inclusion of repetitive avalanche SOA
V (AV)DSS graph 9 (for example see figures 20 and 21).
Z TH = 0.02 C/W Statistically based avalanche ratings are set based on
T = 200 C sample failure statistics. At this rating is labeled EAS
T J = 225 C > T J (max.) (tested) and corresponds to a production test screening
Examples 1 and 2 both have the same energy, however, limit. While the statistical approach generally gives higher
since the inductor varies, so does the junction temperature. energy value, it does not provide a practical method for
While one junction temperature is within TJ (max.), the second evaluating avalanche capability in conditions that differ
is not. from the datasheet. Since circuit designers conditions
usually differ significantly, the statistical approach does
Note as well that power MOSFETs which are EAS rated not give a clear idea on how to design for occurrence of
include graphs showing constant junction temperature avalanche.
energy values. See for example figure 20, top curve. Which
value of energy should be compared with another suppliers Some legacy products were designed without an
power MOSFET? avalanche rating. Devices without an avalanche rating on
the datasheet should not be used In circuits which will see
Another common industry practice is to rate avalanche avalanche condition during any mode of operation. By
capability based on curves showing allowable time in special arrangement, most such designs can be
avalanche as a trade-off with drain current. At best, such avalanche guaranteed; contact factory representative for
curves are backed up with test to failure data as seen in further information.
figure 10. However, sometimes these curves are based on
statistically determined limits without apparent regard for Power MOSFET users should take care to understand
junction temperature. The result is that a thermal TJ differences in avalanche rating conditions between various
calculation (see examples 1 and 2) for the rated allowed suppliers. Devices that are not avalanche robust can
condition may show that TJ exceeds TJ (max.), without cause unexpected and seemingly unexplained circuit
reliability qualification data at this higher than TJ (max.) failure. Some manufacturers do not rate their MOSFETs for
condition. Again, buyer beware. avalanche at all. Others use a statistical rating alone which
does not offer the same assurance for robust operation
provided by a more complete characterization and rating.
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