ISSCC 2016 / SESSION 15 / OVERSAMPLING DATA CONVERTERS / 15.
15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH
ADC in 28nm CMOS
Yunzhi Dong1, Jialin Zhao1, Wenhua Yang1, Trevor Caldwell2,
Hajime Shibata2, Richard Schreier2, Qingdong Meng3,
Jose Silva1, Donald Paterson1, Jeffrey Gealow1
1
Analog Devices, Wilmington, MA,
2
Analog Devices, Toronto, ON, Canada,
3
Analog Devices, Cambridge, MA
The width of RF bands commonly used for cellular telecommunications has
grown from 35-to-75MHz for 2G/3G/4G platforms to 100-to-200MHz for todays
LTE, and the desire for relaxed image-rejection filtering has pushed the direct IF
sampling frequencies to 300+ MHz. This paper presents a continuous-time (CT)
multi-stage noise-shaping (MASH) ADC IC that achieves 69dB of DR over a
465MHz signal bandwidth with a combined power consumption of 930mW from
1.0V/1.8V supplies. The ADC IC is implemented in 28nm CMOS and achieves a
peak SNDR of 65dB, a small-signal noise-spectral density (NSD) of
156dBFS/Hz, and a figure-of-merit (FOM) of 156dB over a signal bandwidth of
465MHz.
Figure 15.5.1 shows the system-level schematic of the CT 1-2 MASH ADC. With
an 8GHz sample rate and a signal bandwidth of 465MHz, the oversampling ratio
(OSR) is 8.6. A 1-2 MASH architecture is chosen to achieve aggressive
noise-shaping at a low OSR. The use of low-order sub-loops also contributes to
the robustness of the overall ADC. The first stage is a first-order modulator to
minimize the power of amplifiers for a given thermal noise requirement under a
low OSR scenario. The first stage consists of an active-RC integrator, a 17-level
flash ADC (FLASH1), a current-steering DAC (IDAC1), and a capacitive-DAC
(CDAC1). CDAC1 implements a fast direct-feedback (DFB) loop to compensate
for the excess loop delay associated with the chosen FLASH-IDAC timing [1-3].
A differential 200 R1U and a 625uA IDAC1 LSB sets a 2V differential p-p input
full-scale. A dither block adds a 1b 1/2-LSB dither signal to the output of
FLASH1. The quantization residue of the first stage is injected into the second
stage via R21 and current-steering DAC (IDAC2A). R21 is implemented as an
all-pass RC lattice filter to provide both accurate transconductance and a group
delay that approximately matches the delay through the FLASH1-IDAC2A path.
The residue current is then digitized by the second-order second stage. The
second stage consists of an active-RC resonator, a 17-level flash ADC (FLASH2),
current-steering DACs (IDAC2B and IDAC3), and a capacitive-DAC (CDAC2)
used to provide a DFB loop. The second stage uses a feedback topology to
minimize STF peaking and the input full-scale of the second stage is scaled down
to provide an inter-stage gain of six to minimize the overall quantization noise
floor while preventing the residue of the first stage from saturating the second
stage. The digital outputs of both stages, V1 and V2, are fed to the digital
backend for further processing. A 10-tap programmable FIR filter (DNCF) does
noise cancellation after decimation (DEC) by a factor of four. DNCF coefficients
are generated using an off-chip LMS algorithm during an IC start-up calibration
phase.
The amplifiers inside the integrators are multi-path feed-forward amplifiers to
achieve high gain at high frequency at modest power consumption. Figure
15.5.2 shows the implementation of the amplifier inside the first stage. A
fifth-order structure is chosen to provide a high gain over the signal band. The
fifth-order gain path including Gm1a, Gm2a, Gm3a, Gm4a, and Gm5a provides 50+ dB
voltage gain below 500MHz. The fourth-order gain path includes Gm1a, Gm2b,
Gm4a, and Gm5a and the third-order gain path includes Gm1b, Gm4a, and Gm5a,
together they provide the mid-band gain up to 2GHz. The second-order path
including Gm1c and Gm5a dominates gain at 3+GHz while the first-order path via
Gm1d provides a high unity gain frequency of 13GHz. Tunable compensation caps
CC1 to CC3 are added to the outputs of Gm1a, Gm2a and Gm3a. CMFB circuits are not
shown in Fig. 15.5.2. Negative gm compensation circuits (not shown) are applied
to multiple Gm cells to enhance low-to-medium frequency gain. Simple
pseudo-differential inverter-style amplifiers are chosen to implement speed-,
swing- or current-sensitive stages such as Gm1d, Gm1c, Gm4a and Gm5a. The other
Gm stages are implemented using true differential inverter-style amplifiers.
278 2016 IEEE International Solid-State Circuits Conference
The performance of the feedback IDAC1 inside the first stage is critical to the
performance of the entire MASH modulator. In this design, a complementary
current-steering DAC structure is chosen for all regular feedback DACs for its
noise, linearity and speed advantages. Figure 15.5.3 shows the schematic of an
IDAC1 cell. 1.8V and 1V supplies provide sufficient headroom for the top and
bottom current sources to achieve low noise and high output impedance. The
input data from FLASH1, V1, is sampled by a D-Latch before driving the
switching quad consisting of M3 to M6. The switching quad is realized using
ultra-high-Vt devices to provide high output impedance. To minimize dynamic
errors, the capacitance on the sources of cascade transistors M2 and M7 must
be made as small as possible. As a result, the current source devices M1 and M8
are too small to provide adequate matching and the current-source calibration
circuit shown in the bottom left of Fig. 15.5.3 is required. A pair of small
capacitor arrays are also attached to the output of the D-Latch buffer for timing
skew calibration.
Figure 15.5.4 shows the measured in-band spectra of the ADC IC with integrated
digital noise cancellation filtering and decimation filtering. At 8GS/s sampling
rate, the usable signal bandwidth is 465MHz, covering 10 to 475MHz, and the
in-band noise is 69.2dBFS with a 156dBFS/Hz NSD. Peak SNR is 63dB with a
close-to-full-scale signal at 400MHz. A 9dBFS two-tone measurement around
400MHz yields an IMD3 of75dBc. Figure 15.5.5 shows the SNR and SNDR of
the ADC versus the input signal amplitude. With a 400MHz input, an
instantaneous DR of 69dB and a peak SNR of 63dB are achieved. An SNDR
sweep with a 70MHz input signal captures high-order harmonics and the peak
SNDR in this case is about 65dB. The ADC core consumes a total power of
930mW when clocked at 8GHz and achieves an FOM of 156dB over 465MHz
signal bandwidth. When clocked at 6GHz, the ADC consumes a total power of
756mW and achieves a dynamic range of 73dB, a small-signal NSD of
158dBFS/Hz, and an FOM of 160dB over 350MHz signal bandwidth. The digital
decimation filter and noise-cancellation filter (DNCF) consumes a power of
160mW at 8GS/s (not included in FOM). Figure 15.5.7 shows a die photo of the
ADC IC. The ADC analog core is implemented using 1.4mm2 in a 28nm CMOS
process. Figure 15.5.6 compares this work to recent wideband CT ADCs.
This work demonstrates a signal bandwidth that is >3 the state of the art.
Acknowledgements:
The authors would like to thank Bill Harrington, Chris Mello, Adalberto Cantoni,
Jay Bissonnette, Jack Mason, Danial Mohammadi, Zexi Ji, Abrar Ahmed Pathan,
Max Holden, Lin Zhang, Alice Liu, Arshya Feyzi, Grace Jin, Kai Zhang, Huide Li,
Martin Li, John Li, Richard Wang, Leo Wang, Grace Gong, Martin McCormick,
Sudhir Korrapati, Tom Dean, Mike Hathaway, Anthony Del Muro, and Prawal
Shrestha for their hard work and dedication through this project. The authors
also would like to thank Paul Ferguson and Gabriele Manganaro for their
guidance and support.
References:
[1] M. Bolatkale, L. J. Breems, and R. Rutten, A 4GHz CT ADC with 70dB
DR and -74dBFS THD in 125MHz BW,ISSCC Dig. Tech. Papers, pp. 470-471,
Feb. 2011.
[2] H. Shibata, R. Schreier, W. Yang, A. Shaikh, D. Paterson, T. Caldwell, D.
Alldred, P. W. Lai, A DC-to-1GHz Tunable RF ADC Achieving DR = 74dB and
BW = 150MHz at f0 = 450MHz Using 550mW, ISSCC Dig. Tech. Papers, pp.
150-151, Feb. 2012.
[3] Y. Dong, R. Schreier, W. Yang, S. Korrapati, and A. Sheikholeslami, A
235mW CT 0-3 MASH ADC Achieving -167dBFS/Hz NSD with 53MHz BW,
ISSCC Dig. Tech. Papers, pp. 480-481, Feb. 2014.
[4] D. Yoon, S. Ho, and H. Lee, An 85dB-DR 74.6dB-SNDR 50MHz-BW CT
MASH Modulator in 28nm CMOS, ISSCC Dig. Tech. Papers, pp. 272-273,
Feb. 2015.
978-1-4673-9467-3/16/$31.00 2016 IEEE
 ISSCC 2016 / February 2, 2016 / 3:15 PM

Figure 15.5.1: System-level schematic of the 1-2 MASH CT ADC. Figure 15.5.2: Schematic of the feedforward amplifier inside loop filter.

15

Figure 15.5.4: Measured spectra with ADC test IC clocked at 8GHz;

Figure 15.5.3: Schematic of the fully complementary IDAC1 cell with static (top) 70dBFS at 400MHz; (middle) 0.4dBFS at 400 MHz; (bottom) 9dBFS
and timing calibration circuits. two-tone at 390MHz and 400MHz.

Figure 15.5.5: Measured SNR (red) as a function of input signal amplitude at

400MHz; measured SNDR (blue) as a function of input signal amplitude at Figure 15.5.6: Comparison of this work with recent state-of-the-art CT DS and
70MHz. CT MASH ADCs.

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Figure 15.5.7: Microphotograph of the 1-2 MASH ADC chip in 28nm CMOS.

2016 IEEE International Solid-State Circuits Conference 978-1-4673-9467-3/16/$31.00 2016 IEEE