Acer Aspire Timelinex 5820tg Quanta zr7b Rev 1a SCH PDF

5 4 3 2 1
VER : 1A
BOM P/N Description ZR7B SYSTEM BLOCK DIAGRAM
31ZR7MB0000 ZR7B MB(UMA,BT)W/O CPU
31ZR7MB0010 ZR7B MB(SG,MADS,SAM,BT,3G)W/O CPU
D D
Channel A
64MB/128MB x 8
Channel C
P19, 20
Arrandale Madison-Pro
rPGA 989 Park EXT_HDMI
Dual Channel DDR III P4, 5, 6, 7 PCI-E x16
DDRIII-SODIMM1 ATI-GPU
800/1066 MHZ IMC GFX
DDRIII-SODIMM2 EXT_CRT
P14,15
CRT Con.
TS3DV421 P24
P16, 17, 18, 21, 22, 23
EXT_LVDS
FDI DMI
SN74CBT3257 x3
LVDS/CRT
X'TAL SLG8LV595 DMI(x4)
SWITCH
14.318MHz CLOCK USB-8
LVDS/CCD/MIC
INT_CRT
GENERATOR P3 FDI DMI Con.
INT_LVDS P24 Int. MIC P24
CLK
Display
C C
SATA 0
SATA - HDD
P29 INT_HDMI PS8101
SATA
LS P25 HDMI Con.
SATA - ODD SATA 1
P29 EXT_HDMI P25
PCIE-6
PCI-E x1
USB Port USB-1 MINI CARD
USB Ibex Peak-M USB-13
P34 WLAN
P28
USB-3/9/11 PCH
USB/B Con. P34 P8, 9, 10, 11, 12, 13 PCIE-2
(USB Port x3) SIM Card FFC
MINI CARD
USB-10 Conn
3G
USB-4 P28 P28
Bluetooth Con. X'TAL
32.768KHz
P34
B B
PCIE-1 AR8151
Cardreader AU6437-GBL USB-12 X'TAL 25MHz RJ45
GIGA LAN P26
P32
Cardreader control P27
P32
P8 BATTERY RTC X'TAL
25MHz
Azalia SPI SPI ROM

IHDA
P8
LPC
ISL88731A UP6111AQDD ISL62881HRZ-T
LPC Batery Charger P38 +1.05V P42 +VGFX_AXG P46
Int. MIC ALC271X-GRR NPCE781 X'TAL RT8206B RT8207A TPS54418RTE x2

AUDIO CODEC P30 EC P37 32.768KHz 3V/5V P39 +1.5V_SUS P43 +1.8V/+1V P47
ISL62882 MAX8792ETD+T Discharger

CPU core P40 +VGPU_CORE P44 P47
BOM Option Table MIC JACK Speaker Power SW/B Touch Pad
A A
P31 P31 Board Con. Board Con. UP6111AQDD ISL62872 Thermal Protection
Reference Description
P33 P33 P35 +1.1V_VTT P41 +VGPU_IO P45 P48
IV@ for UMA only SKU
SW@ for Switchable Graphic only SKU
MP@ for Madison & Park different parts

for different VRAM parts HP/SPDIF K/B Con. W25X16VSS1G EM-6781-T3 Fan Driver Quanta Computer Inc.
VRAM@
P31 P35 SPI FLASH P37 HALL SENSOR (PWM Type) P35
3G@ for 3G function P24 PROJECT : ZR7B
do not stuff Size Document Number Rev
* 1A
Block Diagram
Date: Friday, March 05, 2010 Sheet 1 of 50
5 4 3 2 1
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A
+3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU A
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
Thermal Follow Chart

Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION SIGNAL ACTIVE IN
B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC

Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V

H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+5V_S5 +5V USB POWER S5_ON S0-S5 H/W Throttling
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0

SML1ALERT#
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
PCH FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0
+VGFX_AXG variation Internal GPU POWER GFX_ON S0

SM-Bus
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
C C
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0

EC
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 CPUFAN#
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0
+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable
+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable
+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable
+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable
+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable
+1V +1V DP/PEG POWER PG_1V_EN Discrete enable
D D
Quanta Computer Inc.

PROJECT : ZR7B
Size Document Number Rev
1A
PWR Status & GPU PWR CRL & THRM
1 2 3 4 5 6 7 8
5 4 3 2 1
D D
150mA(30mil)
+1.5V L53 595@PBY160808T-181Y-N/2A/180ohm_6 +1.5V_CLK 80mA(20mil)
+VDDIO_CLK L49 PBY160808T/2A/180ohm_6+1.05V
C723 C724 C744
C721 C728 C720 C725
.1u/16V_4 .1u/16V_4 .1u/16V_4
R527 .1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
*585@0_6 U35
Place each 0.1uF cap as close as
1 VDD_DOT possible to each VDD IO pin. Place
17 VDD_SRC VDD_SRC_I/O 15 the 10uF caps on the VDD_IO plane.
24 VDD_CPU VDD_CPU_I/O 18
20mil 5 VDD_27
+3V L54 BLM18AG601SN1D/200mA/600ohm_6 +3V_CLK 29 3
VDD_REF DOT_96 CLK_BUF_DREFCLK <10>
DOT_96# 4 CLK_BUF_DREFCLK# <10>
CLK_SDATA 31
C750 C477 C745 CLK_SCLK SDA R609 SW@33_4
32 SCL 27M 6 TP12 27M_CLK <17>
7 CLK_VGA_27M_SS R506 *SW@33_4 CLK_27M_SS <17>
4.7u/10V_8 .1u/16V_4 .1u/16V_4 27M_SS C742 *SW@10p/50V_4
R508 33_4 CPU_SEL 30 10
<10> CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_PCIE_3GPLL <10>
SRC_1#/SATA# 11 CLK_BUF_PCIE_3GPLL# <10>
C734 33p/50V_4 13
SRC_2 CLK_BUF_DREFSSCLK <10>
C SRC_2# 14 CLK_BUF_DREFSSCLK# <10> C
XTAL_IN 28
Y5 XTAL_IN +3V
14.318MHz XTAL_OUT 27 16 R491 10K_4
XTAL_OUT *CPU_STOP#
C727 33p/50V_4 2 20
VSS_DOT CPU_1 TP9
8 VSS_27 CPU_1# 19 TP8
9 VSS_SATA CPU_0 23 CLK_BUF_BCLK <10>
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLK# <10>
21 VSS_CPU
IDT: AL003197001 (ICS9LVS3197AKLFT) 26 25 CK_PWRGD_R
VSS_REF CKPWRGD/PD#
33
Realtek: AL000890000 (RTM890N-632-GRT) GND
Silego: AL000595000 (SLG8LV595VTR)
SLG8LV595V
+3V
CPU_CLK select SMBus
B
+1.05V
CLK Enable +3V B
R325
R489
2
R509 2.2K_4 1K/F_4
*10K_4
3 1 CLK_SDATA CLK_SDATA <14,15,28>
<10> ICH_SMBDATA
CK_PWRGD_R
CPU_SEL Q18
3
2N7002K Q37
2N7002K
R513 C747
+3V <40> VR_PWRGD_CK505# 2 R488
10K_4 *10p/50V/COG_4 100K/F_4
1
R551
2
2.2K_4
0 1
3 1 CLK_SCLK CLK_SCLK <14,15,28>
<10> ICH_SMBCLK
A CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q38 A
2N7002K
(default)

PROJECT : ZR7B
1A
Clock Generator
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
Processor Compensation Signals

U33A U33B
B26 R434 49.9/F_4 R462 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3 T38
A26 A16 CLK_CPU_BCLK <11>
PEG_ICOMPO BCLK
MISC
A24 B27 R461 20/F_4 H_COMP2 AT24 B16 T37 CLK_CPU_BCLK# <11>
<8> DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 R435 750/F_4
<8> DMI_TXN1 DMI_RX#[1] PEG_RBIAS R128 49.9/F_4 H_COMP1 T44
CLOCKS
<8> DMI_TXN2 B22 PEG_RXN[0..15] <16> G16 AR30
DMI_RX#[2] PEG_RXN0 COMP1 BCLK_ITP T48
<8> DMI_TXN3 A21 K35 AT30
D DMI_RX#[3] PEG_RX#[0] PEG_RXN1 R459 49.9/F_4 H_COMP0 BCLK_ITP# D
J34 AT26
PEG_RX#[1] PEG_RXN2 COMP0
<8> DMI_TXP0 B24 J33 E16 CLK_PCIE_3GPLL <10>
DMI_RX[0] PEG_RX#[2] PEG_RXN3 PEG_CLK
<8> DMI_TXP1 D23 G35 D16 CLK_PCIE_3GPLL# <10>
DMI_RX[1] PEG_RX#[3] PEG_CLK#
DMI
B23 G32 PEG_RXN4 T52 AH24
<8> DMI_TXP2 DMI_RX[2] PEG_RX#[4] SKTOCC#
A22 F34 PEG_RXN5 A18 DPLL_REF_SSCLK <10>
<8> DMI_TXP3 DMI_RX[3] PEG_RX#[5] DPLL_REF_SSCLK
F31 PEG_RXN6 A17 DPLL_REF_SSCLK# <10>
PEG_RX#[6] PEG_RXN7 H_CATERR# DPLL_REF_SSCLK#
D24 D35 AK14
<8> DMI_RXN0 DMI_TX#[0] PEG_RX#[7] Use reverse type CATERR#
THERMAL
G24 E33 PEG_RXN8
<8> DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F23 C33 PEG_RXN9 Layout Note: Place
<8>
<8>
DMI_RXN2
DMI_RXN3 H23
DMI_TX#[2]
DMI_TX#[3]
PEG_RX#[9]
PEG_RX#[10]
D32
B32
PEG_RXN10
PEG_RXN11
(at GPU side) AT15
SM_DRAMRST#
F6 CPU_DDR3_DRAMRST# <36> these resistors
PEG_RX#[11] <11> H_PECI PECI
<8> DMI_RXP0 D25
DMI_TX[0] PEG_RX#[12]
C31 PEG_RXN12
SM_RCOMP[0]
AL1 SM_RCOMP_0 R161 100/F_4 near Processor
F24 B28 PEG_RXN13 AM1 SM_RCOMP_1 R163 24.9/F_4
<8> DMI_RXP1 DMI_TX[1] PEG_RX#[13] SM_RCOMP[1]
E23 B30 PEG_RXN14 AN1 SM_RCOMP_2 R170 130/F_4
<8> DMI_RXP2 DMI_TX[2] PEG_RX#[14] SM_RCOMP[2]
G23 A31 PEG_RXN15 <40> H_PROCHOT# H_PROCHOT# AN26
<8> DMI_RXP3 DMI_TX[3] PEG_RX#[15] PROCHOT#
PEG_RXP[0..15] <16> AN15 PM_EXTTS#0 <14>
PM_EXT_TS#[0]
DDR3
MISC
J35 PEG_RXP0 AP15 R188 10K_4
PEG_RX[0] PEG_RXP1 PM_EXT_TS#[1] R179 10K_4
H34 +1.1V_VTT
PEG_RX[1] PEG_RXP2
H33 <11> PM_THRMTRIP# AK15 PM_EXTTS#1 <15>
PEG_RX[2] PEG_RXP3 THERMTRIP#
<8> FDI_TXN0 E22 F35
FDI_TX#[0] PEG_RX[3] PEG_RXP4
<8> FDI_TXN1 D21 G33
FDI_TX#[1] PEG_RX[4] PEG_RXP5 T41
<8> FDI_TXN2 D19 E34 AT28
FDI_TX#[2] PEG_RX[5] PEG_RXP6 PRDY# XDP_PREQ# T67
<8> FDI_TXN3 D18 F32 AP27
FDI_TX#[3] PEG_RX[6] PEG_RXP7 PREQ#
<8> FDI_TXN4 G21 D34
FDI_TX#[4] PEG_RX[7] PEG_RXP8 XDP_TCLK T45
<8> FDI_TXN5 E19 F33 AN28
FDI_TX#[5] PEG_RX[8] TCK
PCI EXPRESS -- GRAPHICS
F21 B33 PEG_RXP9 H_CPURST# AP26 AP28 XDP_TMS T49
<8> FDI_TXN6 FDI_TX#[6] PEG_RX[9] RESET_OBS# TMS
Intel(R) FDI
PWR MANAGEMENT
G18 D31 PEG_RXP10 AT27 XDP_TRST# T68
<8> FDI_TXN7 FDI_TX#[7] PEG_RX[10] TRST#
PEG_RXP11
JTAG & BPM

A32
PEG_RX[11] PEG_RXP12 XDP_TDI_R T73
C30 <8> PM_SYNC AL15 AT29
PEG_RX[12] PEG_RXP13 PM_SYNC TDI XDP_TDO_R T71
<8> FDI_TXP0 D22 A28 AR27
FDI_TX[0] PEG_RX[13] PEG_RXP14 TDO XDP_TDI_M T72
<8> FDI_TXP1 C21 B29 PEG_TXN[0..15] <16> AR29
FDI_TX[1] PEG_RX[14] PEG_RXP15 TDI_M XDP_TDO_M T74
<8> FDI_TXP2 D20 A30 AN14 AP29
FDI_TX[2] PEG_RX[15] VCCPWRGOOD_1 TDO_M
<8> FDI_TXP3 C18
FDI_TX[3] CPEG_TXN0 C300 SW@0.1u/10V_4_X7R PEG_TXN0 H_DBR#_R R190 *Short_4
<8> FDI_TXP4 G22 L33 AN25 XDP_DBRST# <8>
C FDI_TX[4] PEG_TX#[0] CPEG_TXN1 C659 SW@0.1u/10V_4_X7R PEG_TXN1 DBR# C
<8> FDI_TXP5 E20 M35 <11> H_PWRGOOD AN27
FDI_TX[5] PEG_TX#[1] CPEG_TXN2 C304 SW@0.1u/10V_4_X7R PEG_TXN2 VCCPWRGOOD_0
<8> FDI_TXP6 F20 M33
FDI_TX[6] PEG_TX#[2] CPEG_TXN3 C286 SW@0.1u/10V_4_X7R PEG_TXN3 XDP_OBS0 T40
<8> FDI_TXP7 G19 M30 AJ22
FDI_TX[7] PEG_TX#[3] CPEG_TXN4 C288 SW@0.1u/10V_4_X7R PEG_TXN4 BPM#[0] XDP_OBS1 T43
L31 <8,36> PM_DRAM_PWRGD AK13 AK22
PEG_TX#[4] CPEG_TXN5 C285 SW@0.1u/10V_4_X7R PEG_TXN5 SM_DRAMPWROK BPM#[1] XDP_OBS2 T39
<8> FDI_FSYNC0 F17 K32 AK24
FDI_FSYNC[0] PEG_TX#[5] CPEG_TXN6 C289 SW@0.1u/10V_4_X7R PEG_TXN6 BPM#[2] XDP_OBS3 T46
<8> FDI_FSYNC1 E17 M29 AJ24
FDI_FSYNC[1] PEG_TX#[6] CPEG_TXN7 C281 SW@0.1u/10V_4_X7R PEG_TXN7 H_VTTPWRGD BPM#[3] XDP_OBS4 T51
J31 AM15 AJ25
PEG_TX#[7] CPEG_TXN8 C644 SW@0.1u/10V_4_X7R PEG_TXN8 VTTPWRGOOD BPM#[4] XDP_OBS5 T47
<8> FDI_INT C17 K29 AH22
FDI_INT PEG_TX#[8] CPEG_TXN9 C634 SW@0.1u/10V_4_X7R PEG_TXN9 BPM#[5] XDP_OBS6 T50
H30 AK23
PEG_TX#[9] CPEG_TXN10 C636 SW@0.1u/10V_4_X7R PEG_TXN10 T42 BPM#[6] XDP_OBS7 T53
<8> FDI_LSYNC0 F18 H29 AM26 AH23
FDI_LSYNC[0] PEG_TX#[10] CPEG_TXN11 C624 SW@0.1u/10V_4_X7R PEG_TXN11 TAPPWRGOOD BPM#[7]
<8> FDI_LSYNC1 D17 F29
FDI_LSYNC[1] PEG_TX#[11] CPEG_TXN12 C638 SW@0.1u/10V_4_X7R PEG_TXN12
E28
PEG_TX#[12] CPEG_TXN13 C626 SW@0.1u/10V_4_X7R PEG_TXN13 R185 1.5K/F_4 CPU_PLTRST# AL14
D29 <10,11,26,28,32,37> PLTRST#
PEG_TX#[13] CPEG_TXN14 C640 SW@0.1u/10V_4_X7R PEG_TXN14 RSTIN#
D27 PEG_TXP[0..15] <16>
PEG_TX#[14] CPEG_TXN15 C628 SW@0.1u/10V_4_X7R PEG_TXN15 R180
C26
PEG_TX#[15] 750/F_4
L34 CPEG_TXP0 C292 SW@0.1u/10V_4_X7R PEG_TXP0 Clarksfield/Auburndale
PEG_TX[0] CPEG_TXP1 C658 SW@0.1u/10V_4_X7R PEG_TXP1
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
PEG_TX[15]
B B
Clarksfield/Auburndale
Processor pull-up JTAG MAPPING

Thermaltrip protect VTT PWR_Good
XDP_TDI_R XDP_TDI
+1.1V_VTT R476 0_4
XDP_TDO_M XDP_TDO
XDP_TDO R468 51/F_4 R475 *0_4
+1.1V_VTT H_CATERR# R157 49.9/F_4
H_PROCHOT# R460 68_4 R474
H_CPURST# R193 *68_4
3
XDP_TMS R192 *51_4 0_4

+3V XDP_TDI_R R479 *51_4
XDP_PREQ# R466 *51_4 XDP_TDI_M
2 Q15 XDP_TCLK R183 *51_4 R473 *0_4
<8,40> DELAY_VR_PWRGOOD
XDP_TRST# R463 51/F_4 XDP_TDO_R
FDV301N C398 R467 0_4
0.1u/10V_4
1
Scan Chain STUFF -> R469, R491, R507

5
R189 (Default) NO STUFF -> R489, R490

1K_4 <37> MPWROK 2 R187 +1.5V_CPUVDDQ
4 H_VTTPWRGD
1 CPU Only STUFF -> R490, R491
2K/F_4 Use a voltage divider with VDDQ NO STUFF -> R469, R489, R507
U15 R182 (1.5V) rail (ON in S3) and
3
2
A R178 1.1K/F_4 A
resistor combination of 4.75K (to
Q14 TC7SH08FU 1K_4 GMCH Only STUFF -> R489, R507
PM_THRMTRIP# 1 3 MMBT3904 PM_DRAM_PWRGD VDDQ)/12K(to GND) to generate the NO STUFF -> R491, R490, R469
<11> PM_THRMTRIP# SYS_SHDN# <39,48> required voltage.
R181 Note: CRB uses a 3.3V (always ON)
3K/F_4 rail with 2K and 1K combination.

PROJECT : ZR7B
1A
AUBURNDA 1/4
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3) U33D
U33C
<15> M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 <15>

SB_CK#[0] W9 M_B_CLK0# <15>
M_B_DQ0 B5 M3
SB_DQ[0] SB_CKE[0] M_B_CKE0 <15>
M_B_DQ1 A5
M_B_DQ2 SB_DQ[1]
SA_CK[0] AA6 M_A_CLK0 <14> C3 SB_DQ[2]
AA7 M_A_CLK0# <14> M_B_DQ3 B3 V7 M_B_CLK1 <15>
SA_CK#[0] M_B_DQ4 SB_DQ[3] SB_CK[1]
<14> M_A_DQ[63:0] SA_CKE[0] P7 M_A_CKE0 <14> E4 SB_DQ[4] SB_CK#[1] V6 M_B_CLK1# <15>
D M_A_DQ0 M_B_DQ5 D
A10 SA_DQ[0] A6 SB_DQ[5] SB_CKE[1] M2 M_B_CKE1 <15>
M_A_DQ1 C10 M_B_DQ6 A4
M_A_DQ2 SA_DQ[1] M_B_DQ7 SB_DQ[6]
C7 SA_DQ[2] C4 SB_DQ[7]
M_A_DQ3 A7 Y6 M_B_DQ8 D1
SA_DQ[3] SA_CK[1] M_A_CLK1 <14> SB_DQ[8]
M_A_DQ4 B10 Y5 M_B_DQ9 D2
SA_DQ[4] SA_CK#[1] M_A_CLK1# <14> SB_DQ[9]
M_A_DQ5 D10 P6 M_A_CKE1 <14> M_B_DQ10 F2 AB8 M_B_CS#0 <15>
M_A_DQ6 SA_DQ[5] SA_CKE[1] M_B_DQ11 SB_DQ[10] SB_CS#[0]
E10 F1 AD6 M_B_CS#1 <15>
M_A_DQ7 SA_DQ[6] M_B_DQ12 SB_DQ[11] SB_CS#[1]
A8 SA_DQ[7] C2 SB_DQ[12]
M_A_DQ8 D8 M_B_DQ13 F5
F10 AE2 M_A_CS#0 <14> F3
M_A_DQ10 SA_DQ[9] SA_CS#[0] M_B_DQ15 SB_DQ[14]
E6 SA_DQ[10] SA_CS#[1] AE8 M_A_CS#1 <14> G4 SB_DQ[15] SB_ODT[0] AC7 M_B_ODT0 <15>
M_A_DQ11 F7 M_B_DQ16 H6 AD1
SA_DQ[11] SB_DQ[16] SB_ODT[1] M_B_ODT1 <15>
M_A_DQ12 E9 M_B_DQ17 G2
B7 J6
E7 AD8 M_A_ODT0 <14> J3
M_A_DQ15 SA_DQ[14] SA_ODT[0] M_B_DQ20 SB_DQ[19]
C6 AF9 M_A_ODT1 <14> G1 M_B_DM[7:0] <15>
M_A_DQ16 SA_DQ[15] SA_ODT[1] M_B_DQ21 SB_DQ[20] M_B_DM0
H10 SA_DQ[16] G5 SB_DQ[21] SB_DM[0] D4
M_A_DQ17 G8 M_B_DQ22 J2 E1 M_B_DM1
M_A_DQ18 SA_DQ[17] M_B_DQ23 SB_DQ[22] SB_DM[1] M_B_DM2
K7 SA_DQ[18] J1 SB_DQ[23] SB_DM[2] H3
M_A_DQ19 J8 M_B_DQ24 J5 K1 M_B_DM3
G7 K2 AH1
G10 M_A_DM[7:0] <14> L3 AL2
M_A_DQ22 SA_DQ[21] M_A_DM0 M_B_DQ27 SB_DQ[26] SB_DM[5] M_B_DM6
J7 SA_DQ[22] SA_DM[0] B9 M1 SB_DQ[27] SB_DM[6] AR4
M_A_DQ23 J10 D7 M_A_DM1 M_B_DQ28 K5 AT8 M_B_DM7
M_A_DQ24 SA_DQ[23] SA_DM[1] M_A_DM2 M_B_DQ29 SB_DQ[28] SB_DM[7]
L7 H7 K4
M_A_DQ25 SA_DQ[24] SA_DM[2] M_A_DM3 M_B_DQ30 SB_DQ[29]
M6 SA_DQ[25] SA_DM[3] M7 M4 SB_DQ[30]
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ31 N5
L9 AM7 AF3
L6 SA_DQ[28] SA_DM[6] AN10 AG1 SB_DQ[33] M_B_DQS#[7:0] <15>
M_A_DQ29 K8 AN13 M_A_DM7 M_B_DQ34 AJ3 D5 M_B_DQS#0
M_A_DQ30 SA_DQ[29] SA_DM[7] M_B_DQ35 SB_DQ[34] SB_DQS#[0] M_B_DQS#1
N8 AK1 F4
M_A_DQ31 SA_DQ[30] M_B_DQ36 SB_DQ[35] SB_DQS#[1] M_B_DQS#2
P9 AG4 J4
C M_A_DQ32 SA_DQ[31] M_B_DQ37 SB_DQ[36] SB_DQS#[2] M_B_DQS#3 C
AH5 SA_DQ[32] AG3 SB_DQ[37] SB_DQS#[3] L4
M_A_DQ33 AF5 M_B_DQ38 AJ4 AH2 M_B_DQS#4
SA_DQ[33] M_A_DQS#[7:0] <14> SB_DQ[38] SB_DQS#[4]
DDR SYSTEM MEMORY - B

M_A_DQ34 AK6 C9 M_A_DQS#0 M_B_DQ39 AH4 AL4 M_B_DQS#5
SA_DQ[34] SA_DQS#[0] SB_DQ[39] SB_DQS#[5]
DDR SYSTEM MEMORY A
M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ40 AK3 AR5 M_B_DQS#6

M_A_DQ36 SA_DQ[35] SA_DQS#[1] M_A_DQS#2 M_B_DQ41 SB_DQ[40] SB_DQS#[6] M_B_DQS#7
AF6 SA_DQ[36] SA_DQS#[2] J9 AK4 SB_DQ[41] SB_DQS#[7] AR8
M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ42 AM6
M_A_DQ38 SA_DQ[37] SA_DQS#[3] M_A_DQS#4 M_B_DQ43 SB_DQ[42]
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AN2 SB_DQ[43]
M_A_DQ39 AJ6 AK9 M_A_DQS#5 M_B_DQ44 AK5
M_A_DQ40 SA_DQ[39] SA_DQS#[5] M_A_DQS#6 M_B_DQ45 SB_DQ[44]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 AK2 SB_DQ[45]
M_A_DQ41 AJ9 AT13 M_A_DQS#7 M_B_DQ46 AM4
M_A_DQ42 SA_DQ[41] SA_DQS#[7] M_B_DQ47 SB_DQ[46]
AL10 SA_DQ[42] AM3 SB_DQ[47] M_B_DQS[7:0] <15>
M_A_DQ43 AK12 M_B_DQ48 AP3 C5 M_B_DQS0
M_A_DQ44 SA_DQ[43] M_B_DQ49 SB_DQ[48] SB_DQS[0] M_B_DQS1
AK8 SA_DQ[44] AN5 SB_DQ[49] SB_DQS[1] E3
M_A_DQ45 AL7 M_B_DQ50 AT4 H4 M_B_DQS2
M_A_DQ46 SA_DQ[45] M_A_DQS0 M_A_DQS[7:0] <14> M_B_DQ51 SB_DQ[50] SB_DQS[2] M_B_DQS3
AK11 C8 AN6 M5
M_A_DQ47 SA_DQ[46] SA_DQS[0] M_A_DQS1 M_B_DQ52 SB_DQ[51] SB_DQS[3] M_B_DQS4
AL8 F9 AN4 AG2
AN8 H9 AN3 AL5
AM10 M9 AT5 AP5
AR11 AH8 AT6 AR7
M_A_DQ51 SA_DQ[50] SA_DQS[4] M_A_DQS5 M_B_DQ56 SB_DQ[55] SB_DQS[7]
AL11 SA_DQ[51] SA_DQS[5] AK10 AN7 SB_DQ[56]
M_A_DQ52 AM9 AN11 M_A_DQS6 M_B_DQ57 AP6
M_A_DQ53 SA_DQ[52] SA_DQS[6] M_A_DQS7 M_B_DQ58 SB_DQ[57]
AN9 AR13 AP8
M_A_DQ54 SA_DQ[53] SA_DQS[7] M_B_DQ59 SB_DQ[58]
AT11 AT9
AP12 AT7
AM12 AP9
AN12 M_A_A[15:0] <14> AR10 M_B_A[15:0] <15>
M_A_DQ58 SA_DQ[57] M_A_A0 M_B_DQ63 SB_DQ[62] M_B_A0
AM13 SA_DQ[58] SA_MA[0] Y3 AT10 SB_DQ[63] SB_MA[0] U5
M_A_DQ59 AT14 W1 M_A_A1 V2 M_B_A1
M_A_DQ60 SA_DQ[59] SA_MA[1] M_A_A2 SB_MA[1] M_B_A2
AT12 AA8 T5
AL13 AA3 V3
AR14 V1 R1
AP14 AA9 <15> M_B_BS#0 AB1 T8
B SA_DQ[63] SA_MA[5] M_A_A6 SB_BS[0] SB_MA[5] M_B_A6 B
SA_MA[6] V8 <15> M_B_BS#1 W5 SB_BS[1] SB_MA[6] R2
T1 M_A_A7 R7 R6 M_B_A7
SA_MA[7] <15> M_B_BS#2 SB_BS[2] SB_MA[7]
Y9 M_A_A8 R4 M_B_A8
SA_MA[8] M_A_A9 SB_MA[8] M_B_A9
<14> M_A_BS#0 AC3 SA_BS[0] SA_MA[9] U6 SB_MA[9] R5
<14> M_A_BS#1 AB2 AD4 M_A_A10 <15> M_B_CAS# AC5 AB5 M_B_A10
SA_BS[1] SA_MA[10] M_A_A11 SB_CAS# SB_MA[10] M_B_A11
<14> M_A_BS#2 U7 T2 <15> M_B_RAS# Y7 P3
SA_BS[2] SA_MA[11] M_A_A12 SB_RAS# SB_MA[11] M_B_A12
U3 <15> M_B_WE# AC6 R3
SA_MA[12] M_A_A13 SB_WE# SB_MA[12] M_B_A13
AG8 AF7
T3 P5
<14> M_A_CAS# AE1 SA_CAS# SA_MA[15] V9 SB_MA[15] N1
<14> M_A_RAS# AB3 SA_RAS#
<14> M_A_WE# AE9
SA_WE#
Clarksfield/Auburndale Clarksfield/Auburndale
Channel A DQ[15,32,48,54], DM[5] Channel B DQ[16,18,36,42,56,57,60,61,62]

Requires minimum 12mils spacing Requires minimum 12mils spacing
with all other signals, including data signals. with all other signals, including data signals.
A A

PROJECT : ZR7B
1A
AUBURNDA 2/4
5 4 3 2 1
5 4 3 2 1
CPU Core Power U33F
VTT Rail Values are AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

ARD:48A Auburndal VTT=1.05V
+VCC_CORE Clarksfield VTT=1.1V
CFD:52A
18A
C346 22U/6.3V_8 AG35 AH14 +1.1V_VTT U33G
C684 22U/6.3V_8 VCC1 VTT0_1
AG34 AH12
C350 22U/6.3V_8 AG33
VCC2 VTT0_2
AH11 +VGFX_AXG
22A AT21
C303 22U/6.3V_8 VCC3 VTT0_3 C679 10U/6.3V_8 VAXG1 T69
AG32 AH10 AT19 AR22 VCC_AXG_SENSE <46>
D C672 22U/6.3V_8 VCC4 VTT0_4 C676 10U/6.3V_8 VAXG2 VAXG_SENSE T70 D
SENSE
LINES
AG31 J14 AT18 AT22 VSS_AXG_SENSE <46>
C677 22U/6.3V_8 VCC5 VTT0_5 C662 10U/6.3V_8 VAXG3 VSSAXG_SENSE
AG30 J13 AT16
C674 22U/6.3V_8 VCC6 VTT0_6 C362 10U/6.3V_8 VAXG4
AG29 H14 AR21
C384 22U/6.3V_8 VCC7 VTT0_7 C683 10U/6.3V_8 VAXG5
AG28 H12 AR19
C354 22U/6.3V_8 VCC8 VTT0_8 C664 10U/6.3V_8 + VAXG6
AG27 G14 AR18
C668 22U/6.3V_8 VCC9 VTT0_9 C663 10U/6.3V_8 C692 C359 C358 VAXG7
AG26 G13 AR16 AM22 GFX_VID0 <46>
C311 22U/6.3V_8 VCC10 VTT0_10 C685 22U/6.3V_8 330U/2V_7343 22u/6.3V_8 22u/6.3V_8 VAXG8 GFX_VID[0]
AF35 G12 AP21 AP22 GFX_VID1 <46>
VCC11 VTT0_11 VAXG9 GFX_VID[1]
GRAPHICS VIDs
C366 22U/6.3V_8 AF34 G11 C633 22U/6.3V_8 AP19 AN22 GFX_VID2 <46>
C334 10U/6.3V_8 VCC12 VTT0_12 C326 22U/6.3V_8 VAXG10 GFX_VID[2]
AF33 F14 AP18 AP23 GFX_VID3 <46>
C336 10U/6.3V_8 VCC13 VTT0_13 VAXG11 GFX_VID[3]
AF32 F13 AP16 AM23 GFX_VID4 <46>
AF31 F12 C306 AN21 AP24 GFX_VID5 <46>
VCC15 VTT0_15 VAXG13 GFX_VID[5]
GRAPHICS
C675 10U/6.3V_8 AF30 F11 AN19 AN24 GFX_VID6 <46>
+
AF29 E14 AN18
C682 10U/6.3V_8 VCC17 VTT0_17 VAXG15
AF28 E12 AN16
C678 10U/6.3V_8 VCC18 VTT0_18 VAXG16
AF27 D14 AM21 AR25 GFX_ON <46>
C388 10U/6.3V_8 VCC19 VTT0_19 330u/2V_7343 VAXG17 GFX_VR_EN
AF26 D13 AM19 AT25 GFX_DPRSLPVR <46>
C669 10U/6.3V_8 VCC20 VTT0_20 VAXG18 GFX_DPRSLPVR
AD35 D12 AM18 AM24
1.1V RAIL POWER

VCC21 VTT0_21 + VAXG19 GFX_IMON GFX_IMON <46>
C356 10U/6.3V_8 AD34 D11 AM16
C357 10U/6.3V_8 VCC22 VTT0_22 C691 C360 C361 VAXG20
AD33 C14 AL21
C320 10U/6.3V_8 VCC23 VTT0_23 330U/2V_7343 10u/6.3V_8 10u/6.3V_8 VAXG21
C671 10U/6.3V_8
AD32
VCC24 VTT0_24
C13 AL19
VAXG22 ARD:3A
AD31 C12 AL18
C323 10U/6.3V_8 VCC25 VTT0_25 VAXG23 CFD:6A
AD30 C11 AL16
C314 10U/6.3V_8 VCC26 VTT0_26 VAXG24
AD29 B14 AK21 AJ1 +1.5V_CPUVDDQ
C681 10U/6.3V_8 VCC27 VTT0_27 VAXG25 VDDQ1
AD28 B12 AK19 AF1
C344 0.1u/10V_4_X7R VCC28 VTT0_28 VAXG26 VDDQ2
- 1.5V RAILS
AD27 A14 AK18 AE7
C309 0.1u/10V_4_X7R VCC29 VTT0_29 VAXG27 VDDQ3 C368 C301 C307 C373
AD26 A13 AK16 AE4
VCC30 VTT0_30 VAXG28 VDDQ4
AC35 A12 AJ21 AC1
+
C313 330u/2V_7343 AC34 A11 AJ19 AB7 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
AC33 AJ18 AB4
VCC33 VAXG31 VDDQ7
+
C339 330u/2V_7343 AC32 +1.1V_VTT AJ16 Y1

VCC34 VAXG32 VDDQ8
AC31 AH21 W7
VCC35 VAXG33 VDDQ9
POWER
AC30 AF10 AH19 W4
C VCC36 VTT0_33 VAXG34 VDDQ10 C372 C363 C312 + C310 C
AC29 AE10 AH18 U1
AC28 AC10 AH16 T7
CPU CORE SUPPLY

AC27 AB10 C294 22U/6.3V_8 T4 1U/6.3V_4 22U/6.3V_8 22U/6.3V_8 330U/2V_7343
VCC39 VTT0_36 VDDQ13
AC26 Y10 P1
VCC40 VTT0_37 C295 22U/6.3V_8 VDDQ14
AA35 W10 N7
AA34 U10 N4
VCC42 VTT0_39 +1.1V_VTT VDDQ16
DDR3
AA33 T10 L1
AA32 J12 J24 H1
VCC44 VTT0_41 VTT1_45 VDDQ18
FDI
AA31 J11 J23
VCC45 VTT0_42 VTT1_46
AA30 J16 H25
AA29 J15
VCC47 VTT0_44
AA28
VCC48 C297 C670
AA27 P10 +1.1V_VTT
VCC49 22u/6.3V_8 22u/6.3V_8 VTT0_59
AA26 N10
VCC50 VTT0_60 C665 10U/6.3V_8
Y35 L10
VCC51 VTT0_61 C667 10U/6.3V_8
Y34 K10
VCC52 VTT0_62
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
1.1V
Y29 J22
VCC57 VTT1_63 22U/6.3V_8 C660
Y28 K26 J20
VCC58 VTT1_48 VTT1_64 22U/6.3V_8 C661
Y27 J27 J18
PEG & DMI

Y26 J26 H21
VCC60 H_PSI# C345 C673 C296 C335 VTT1_50 VTT1_66
V35 AN33 H_PSI# <40> J25 H20
VCC61 PSI# 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 VTT1_51 VTT1_67
V34 H27 H19
POWER

V33 G28
VCC63 H_VID0 VTT1_53
V32 AK35 H_VID0 <40> G27
VCC64 VID[0] H_VID1 VTT1_54
V31
VCC65 VID[1]
AK33
H_VID2
H_VID1 <40> G26
VTT1_55 0.6A
V30 AK34 H_VID2 <40> F26
VCC66 VID[2] H_VID3 VTT1_56
V29 AL35 H_VID3 <40> E26 L26 +1.8V
VCC67 VID[3] VTT1_57 VCCPLL1
CPU VIDS
1.8V
V28 AL33 H_VID4 H_VID4 <40> E25 L27
B VCC68 VID[4] H_VID5 VTT1_58 VCCPLL2 22U/6.3V_8 C298 B
V27 AM33 H_VID5 <40> M26
VCC69 VID[5] H_VID6 VCCPLL3 4.7U/6.3V_6 C299
V26 AM35 H_VID6 <40>
VCC70 VID[6] H_DPRSLPVR 2.2U/6.3V_6 C272
U35 AM34 H_DPRSLPVR <40>
VCC71 PROC_DPRSLPVR 1U/6.3V_4 C274
U34
VCC72 1U/6.3V_4 C273
U33
VCC73
U32
VCC74 H_VTTVID1
U31 G15 T36
VCC75 VTT_SELECT
U30
VCC76 Clarksfield/Auburndale
U29
VCC77 H_VTTVID1=Low, 1.1V
U28
VCC78 H_VTTVID1=High, 1.05V
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32 AN35 I_MON <40>
VCC84 ISENSE
R31
VCC85
R30
VCC86 R159 100/F_4
R29 +VCC_CORE
VCC87
R28 AJ34
SENSE LINES
VCC88 VCC_SENSE VCCSENSE <40>

R27 AJ35 VSSSENSE <40>
1 H_VID0 R478 1K_4 +1.1V_VTT
VCC89 VSS_SENSE R477 *1K/F_4
R26
VCC90 R160 100/F_4 1 H_VID1 R481 1K_4
P35
VCC91 VTT_SENSE R480 *1K/F_4
P34 B15 T65
VCC92 VTT_SENSE VSS_SENSE_VTT 1 H_VID2 R197 1K_4
P33 A15 T64
VCC93 VSS_SENSE_VTT R196 *1K/F_4
P32
VCC94 0 H_VID3 R472 *1K/F_4
P31
VCC95 R471 1K_4
P30
VCC96 0 H_VID4 R195 *1K/F_4
P29
VCC97 R194 1K_4
P28
VCC98 1 H_VID5 R465 1K_4
P27
VCC99 R458 *1K/F_4
P26
A VCC100 0 H_VID6 R470 *1K/F_4 A
R469 1K_4
1 H_DPRSLPVR R202 1K_4
R201 *1K/F_4
0 H_PSI# R464 *1K/F_4
R457 1K_4
Note:
For Validating IMVP VR R6451 should be STUFF
HFM_VID : Max 1.4V
and R2N1 NO_STUFF LFM_VID : Min 0.65V PROJECT : ZR7B
AUBURNDALE/CLARKSFIELD PROCESSOR (POWER) Size Document Number Rev
1A
AUBURNDA 3/4 (PWR)
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

U33H U33I U33E
AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AT17 VSS2 VSS82 AE33 RSVD33 AJ12
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162 AP25 RSVD1
AR26 VSS5 VSS85 AE30 K6 VSS163 AL25 RSVD2 RSVD34 AH25
AR24 VSS6 VSS86 AE29 K3 VSS164 AL24 RSVD3 RSVD35 AK26
AR23 VSS7 VSS87 AE28 J32 VSS165 AL22 RSVD4
AR20 VSS8 VSS88 AE27 J30 VSS166 AJ33 RSVD5 RSVD36 AL26
AR17 VSS9 VSS89 AE26 J21 VSS167 AG9 RSVD6 RSVD_NCTF_37 AR2
AR15 VSS10 VSS90 AE6 J19 VSS168 M27 RSVD7
D AR12 VSS11 VSS91 AD10 H35 VSS169 L28 RSVD8 RSVD38 AJ26 D
AR9 VSS12 VSS92 AC8 H32 VSS170 <14,36> VREF_DQ_DIMM0 J17 SA_DIMM_VREF RSVD39 AJ27
AR6 VSS13 VSS93 AC4 H28 VSS171 <15,36> VREF_DQ_DIMM1 H17 SB_DIMM_VREF
AR3 VSS14 VSS94 AC2 H26 VSS172 G25 RSVD11
AP20 VSS15 VSS95 AB35 H24 VSS173 G17 RSVD12
AP17 VSS16 VSS96 AB34 H22 VSS174 E31 RSVD13 RSVD_NCTF_40 AP1
AP13 VSS17 VSS97 AB33 H18 VSS175 E30 RSVD14 RSVD_NCTF_41 AT2
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177 RSVD_NCTF_42 AT3
AP4 VSS20 VSS100 AB30 H11 VSS178 RSVD_NCTF_43 AR1
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182 RSVD45 AL28
AN20 AB6 G31 CFG0 AM30 AL29
VSS25 VSS105 VSS183 CFG[0] RSVD46
AN17 VSS26 VSS106 AA10 G20 VSS184 AM28 CFG[1] RSVD47 AP30
AM29 VSS27 VSS107 Y8 G9 VSS185 AP31 CFG[2] RSVD48 AP32
AM27 Y4 G6 CFG3 AL32 AL27
VSS28 VSS108 VSS186 CFG4 CFG[3] RSVD49
AM25 VSS29 VSS109 Y2 G3 VSS187 AL30 CFG[4] RSVD50 AT31
AM20 VSS30 VSS110 W 35 F30 VSS188 AM31 CFG[5] RSVD51 AT32
AM17 VSS31 VSS111 W 34 F27 VSS189 AN29 CFG[6] RSVD52 AP33
AM14 W 33 F25 CFG7 AM32 AR33
VSS32 VSS112 VSS190 CFG[7] RSVD53
AM11 VSS33 VSS113 W 32 F22 VSS191 AK32 CFG[8] RSVD_NCTF_54 AT33
AM8 W 31 F19 AK31 AT34
RESERVED
VSS34 VSS114 VSS192 CFG[9] RSVD_NCTF_55
AM5 VSS35 VSS115 W 30 F16 VSS193 AK28 CFG[10] RSVD_NCTF_56 AP35
AM2 VSS36 VSS116 W 29 E35 VSS194 AJ28 CFG[11] RSVD_NCTF_57 AR35
AL34 W 28 E32 AN30 AR32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W 27
W 26
E29
E24
VSS195
VSS196
VSS197
VSS AN32
AJ32
CFG[12]
CFG[13]
CFG[14]
RSVD58
AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

AL17 VSS41 VSS121 V10 E18 VSS199 AJ30 CFG[16] RSVD_TP_60 F15
C AL12 U8 E13 AK30 A2 C
VSS42 VSS122 VSS200 CFG[17] KEY
AL9 VSS43 VSS123 U4 E11 VSS201 H16 RSVD_TP_86 RSVD62 D15
AL6 VSS44 VSS124 U2 E8 VSS202 RSVD63 C15
AL3 VSS45 VSS125 T35 E5 VSS203 RSVD64 AJ15 TP6
AK29 VSS46 VSS126 T34 E2 VSS204 VSS_NCTF1 AT35 RSVD65 AH15 TP7
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34 TP5 B19 RSVD15
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34 TP2 A19 RSVD16
AK17 T30 D9 B2 TP3
NCTF
VSS50 VSS130 VSS208 VSS_NCTF5
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1 TP33 A20 RSVD17
AJ23 VSS52 VSS132 T28 D3 VSS210 VSS_NCTF7 A35 TP34 B20 RSVD18
AJ20 VSS53 VSS133 T27 C34 VSS211 RSVD_TP_66 AA5
AJ17 VSS54 VSS134 T26 C32 VSS212 U9 RSVD19 RSVD_TP_67 AA4
AJ14 VSS55 VSS135 T6 C29 VSS213 T9 RSVD20 RSVD_TP_68 R8
AJ11 VSS56 VSS136 R10 C28 VSS214 RSVD_TP_69 AD3
AJ8 VSS57 VSS137 P8 C24 VSS215 AC9 RSVD21 RSVD_TP_70 AD2
AJ5 VSS58 VSS138 P4 C22 VSS216 AB9 RSVD22 RSVD_TP_71 AA2
AJ2 VSS59 VSS139 P2 C20 VSS217 RSVD_TP_72 AA1
AH35 VSS60 VSS140 N35 C19 VSS218 RSVD_TP_73 R9
AH34 VSS61 VSS141 N34 C16 VSS219 RSVD_TP_74 AG7
AH33 VSS62 VSS142 N33 B31 VSS220 C1 RSVD_NCTF_23 RSVD_TP_75 AE3
AH32 VSS63 VSS143 N32 B25 VSS221 A3 RSVD_NCTF_24
AH31 VSS64 VSS144 N31 B21 VSS222
AH30 VSS65 VSS145 N30 B18 VSS223 RSVD_TP_76 V4
AH29 VSS66 VSS146 N29 B17 VSS224 RSVD_TP_77 V5
AH28 VSS67 VSS147 N28 B13 VSS225 RSVD_TP_78 N2
AH27 VSS68 VSS148 N27 B11 VSS226 J29 RSVD26 RSVD_TP_79 AD5
AH26 VSS69 VSS149 N26 B8 VSS227 J28 RSVD27 RSVD_TP_80 AD7
AH20 VSS70 VSS150 N6 B6 VSS228 RSVD_TP_81 W3
AH17 VSS71 VSS151 M10 B4 VSS229 A34 RSVD_NCTF_28 RSVD_TP_82 W2
AH13 VSS72 VSS152 L35 A29 VSS230 A33 RSVD_NCTF_29 RSVD_TP_83 N3
B B
AH9 VSS73 VSS153 L32 A27 VSS231 RSVD_TP_84 AE5
AH6 VSS74 VSS154 L29 A23 VSS232 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
AH3 VSS75 VSS155 L8 A9 VSS233 B35 RSVD_NCTF_31
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2 VSS AP34 TP4
AF4 VSS78 VSS158 K34
AF2 K33 AP34 can be NC on CRB; EDS/DG suggestion to GND
VSS79 VSS159
AE35 VSS80 VSS160 K30
Clarksfield/Auburndale Clarksfield/Auburndale
Processor Strapping
1 0 DEFAULT
CFG0 CFG0 R186 *3.01K_NC
(PCI-Epress Single PEG Bifurcation enabled 1
Configuration Select)
CFG3
(PCI-Epress Static Normal Operation Lane Numbers Reversed CFG3 R169
1 3.01K/F_4
Lane Reversal)
A CFG4 Enabled; An external Display port A
(Embended Disabled; No Physical Display Port device is connected to the Embedded CFG4 R162
1 *3.01K
Display Port Presence) attached to Embedded Diplay Port Display port
Ts
hI
CFG7 R172 *3.01K/F_4

p
ea

n
ec
PROJECT : ZR7B
n
t
c
Co

d
e
i
lm
1A
AUBURNDA 4/4
l
f
ap

B
5 4 3 2 1
i
roG
r
c
knA
e
5 4 3 2 1
IBEX PEAK-M (DMI,FDI,GPIO)

IBEX PEAK-M (LVDS,DDI)
U36C
BA18 FDI_TXN0 <4>
FDI_RXN0 U36D
<4> DMI_RXN0 BC24 BH17 FDI_TXN1 <4>
DMI0RXN FDI_RXN1
<4> DMI_RXN1 BJ22 BD16 FDI_TXN2 <4> <24> INT_LVDS_BLON T48 BJ46
DMI1RXN FDI_RXN2 L_BKLTEN SDVO_TVCLKINN
D <4> DMI_RXN2 AW20 BJ16 FDI_TXN3 <4> <24> INT_LVDS_DIGON T47 BG46 D
DMI2RXN FDI_RXN3 L_VDD_EN SDVO_TVCLKINP
<4> DMI_RXN3 BJ20 BA16 FDI_TXN4 <4>
DMI3RXN FDI_RXN4
BE14 FDI_TXN5 <4> <24> INT_LVDS_BRIGHT Y48 BJ48
FDI_RXN5 L_BKLTCTL SDVO_STALLN
<4> DMI_RXP0 BD24 BA14 FDI_TXN6 <4> BG48
DMI0RXP FDI_RXN6 SDVO_STALLP
<4> DMI_RXP1 BG22 BC12 FDI_TXN7 <4> <24> INT_LVDS_EDIDCLK AB48
DMI1RXP FDI_RXN7 L_DDC_CLK
<4> DMI_RXP2 BA20 <24> INT_LVDS_EDIDDATA Y45 BF45
DMI2RXP L_DDC_DATA SDVO_INTN
<4> DMI_RXP3 BG20 BB18 FDI_TXP0 <4> BH45
DMI3RXP FDI_RXP0 R254 10K_4 SDVO_INTP
BF17 FDI_TXP1 <4> +3V AB46
FDI_RXP1 R258 10K_4 L_CTRL_CLK
<4> DMI_TXN0 BE22 BC16 FDI_TXP2 <4> V48
DMI0TXN FDI_RXP2 L_CTRL_DATA
<4> DMI_TXN1 BF21 BG16 FDI_TXP3 <4>
DMI1TXN FDI_RXP3 R233 2.37K/F_4
<4> DMI_TXN2 BD20 AW16 FDI_TXP4 <4> AP39 T51 SDVO_CTRLCLK <25>
DMI2TXN FDI_RXP4 LVD_IBG SDVO_CTRLCLK
<4> DMI_TXN3 BE18 BD14 FDI_TXP5 <4> AP41 T53 SDVO_CTRLDAT <25>
DMI3TXN FDI_RXP5 LVD_VBG SDVO_CTRLDATA
BB14 FDI_TXP6 <4>
FDI_RXP6
<4> DMI_TXP0 BD22 BD12 FDI_TXP7 <4> AT43
DMI0TXP FDI_RXP7 LVD_VREFH
<4> DMI_TXP1 BH21 AT42 BG44 TP36
DMI1TXP LVD_VREFL DDPB_AUXN
<4> DMI_TXP2 BC20 BJ44 TP35
DMI2TXP DDPB_AUXP
<4> DMI_TXP3 BD18 BJ14 FDI_INT <4> AU38 INT_HDMI_HPD <25>
DMI3TXP FDI_INT DDPB_HPD
LVDS
<24> INT_TXLCLKOUT- INT_TXLCLKOUT- AV53
DMI
FDI
INT_TXLCLKOUT+ AV51 LVDSA_CLK# INT_HDMITX2N_R C411 0.1u/10V_4_X7R
BF13 FDI_FSYNC0 <4> <24> INT_TXLCLKOUT+ BD42 INT_HDMITX2N <25>
FDI_FSYNC0 LVDSA_CLK DDPB_0N INT_HDMITX2P_R C412 0.1u/10V_4_X7R
BH25 BC42 INT_HDMITX2P <25>
DMI_ZCOMP INT_TXLOUT0- DDPB_0P INT_HDMITX1N_R C414 0.1u/10V_4_X7R
BH13 FDI_FSYNC1 <4> <24> INT_TXLOUT0- BB47 BJ42 INT_HDMITX1N <25>
R483 49.9/F_4 FDI_FSYNC1 INT_TXLOUT1- LVDSA_DATA#0 DDPB_1N INT_HDMITX1P_R C413 0.1u/10V_4_X7R
BF25 BA52 BG42
Digital Display Interface

+1.05V DMI_IRCOMP <24> INT_TXLOUT1- LVDSA_DATA#1 DDPB_1P INT_HDMITX1P <25>
BJ12 INT_TXLOUT2- AY48 BB40 INT_HDMITX0N_R C442 0.1u/10V_4_X7R
FDI_LSYNC0 FDI_LSYNC0 <4> <24> INT_TXLOUT2- LVDSA_DATA#2 DDPB_2N INT_HDMITX0N <25>
AV47 BA40 INT_HDMITX0P_R C443 0.1u/10V_4_X7R
LVDSA_DATA#3 DDPB_2P INT_HDMITX0P <25>
BG14 AW38 INT_HDMICLK-_R C432 0.1u/10V_4_X7R
FDI_LSYNC1 FDI_LSYNC1 <4> DDPB_3N INT_HDMICLK- <25>
<24> INT_TXLOUT0+ INT_TXLOUT0+ BB48 BA38 INT_HDMICLK+_R C431 0.1u/10V_4_X7R
LVDSA_DATA0 DDPB_3P INT_HDMICLK+ <25>
<24> INT_TXLOUT1+ INT_TXLOUT1+ BA50
INT_TXLOUT2+ LVDSA_DATA1
C <24> INT_TXLOUT2+ AY49 C
LVDSA_DATA2
AV48 Y49
LVDSA_DATA3 DDPC_CTRLCLK
AB49
DDPC_CTRLDATA
AP48
XDP_DBRST# LVDSB_CLK#
<4> XDP_DBRST# T6 J12 PCIE_WAKE# <26,28> AP47 BE44
SYS_RESET# WAKE# LVDSB_CLK DDPC_AUXN
BD44
DDPC_AUXP
AY53 AV40
SYS_PWROK LVDSB_DATA#0 DDPC_HPD
M6 Y1 CLKRUN# <37> AT49
SYS_PWROK CLKRUN# / GPIO32 LVDSB_DATA#1
AU52 BE40
LVDSB_DATA#2 DDPC_0N
AT53 BD40
LVDSB_DATA#3 DDPC_0P
System Power Management
B17 BF41
PWROK DDPC_1N
AY51 BH41
LVDSB_DATA0 DDPC_1P
AT48 BD38
SUS_STAT# LVDSB_DATA1 DDPC_2N
K5 P8 TP14 AU50 BC38
MEPWROK SUS_STAT# / GPIO61 LVDSB_DATA2 DDPC_2P
AT51 BB36
LVDSB_DATA3 DDPC_3N
BA36
RSV_ICH_LAN_RST# A10 R401 *Short_4 DDPC_3P
F3 ICH_SUSCLK <37>
LAN_RST# SUSCLK / GPIO62
INT_CRT_BLU AA52 U50
<24> INT_CRT_BLU CRT_BLUE DDPD_CTRLCLK
D9 E4 SLP_S5#_R TP27 INT_CRT_GRN AB53 U52
<4,36> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 <24> INT_CRT_GRN CRT_GREEN DDPD_CTRLDATA
INT_CRT_RED AD53
<24> INT_CRT_RED CRT_RED
<37> ICH_RSMRST# C16 H7 SUSC# <37> BC46

RSMRST# SLP_S4# DDPD_AUXN
<24> INT_CRT_DDCCLK V51
CRT_DDC_CLK DDPD_AUXP
BD46 R place close to PCH
<24> INT_CRT_DDCDAT V53 AT38
SUS_PWR_ACK_R CRT_DDC_DATA DDPD_HPD R507 150_4 INT_CRT_BLU
M1 P12 SUSB# <37>
SUS_PWR_DN_ACK / GPIO30 SLP_S3#
B BJ40 B
DDPD_0N R499 150_4 INT_CRT_GRN
<24> INT_HSYNC Y53 BG40
SLP_M# R278 *0_4 CRT_HSYNC DDPD_0P
<37> DNBSWON# P5 K8 <24> INT_VSYNC Y51 BJ38
PWRBTN# SLP_M# CRT_VSYNC DDPD_1N R495 150_4 INT_CRT_RED
BG38
DDPD_1P
CRT
BF37
R269 *0_4 ACIN_R DAC_IREF DDPD_2N
<37> PCH_ACIN P7 N2 TP23 AD48 BH37
ACPRESENT / GPIO31 TP23 DAC_IREF DDPD_2P
AB51 BE36
CRT_IRTN DDPD_3N
BD36
PM_BATLOW# R243 DDPD_3P
A6 BJ10 PM_SYNC <4>
BATLOW# / GPIO72 PMSYNCH 1K/F_4 IbexPeak-M_R1P0
PM_RI# F14 F6 PM_SLP_LAN# TP29

RI# SLP_LAN# / GPIO29
IbexPeak-M_R1P0
PCH Pull-high/low +3V_S5

System PWR_OK
+3V
PM_RI# R296 10K_4

CLKRUN# R498 8.2K_4 +3V_S5
PM_BATLOW# R541 10K_4 DELAY_VR_PWRGOOD need PU 2K to +3V.
XDP_DBRST# R275 1K_4 C805 *.1u_4
A
PCIE_WAKE# R287 1K_4
PU at power side A
5
ICH_RSMRST# R560 10K_4 PM_SLP_LAN# R292 *10K_4 1 DELAY_VR_PWRGOOD <4,40>
SYS_PWROK 4
RSV_ICH_LAN_RST# R572 10K_4 SUS_PWR_ACK_R R530 10K_4 2
U41
PWROK_EC <37>
3
SYS_PWROK R582 10K_4 ACIN_R R270 10K_4 R605 100K_4
TC7SH08FU
PROJECT : ZR7B
1A
IBEX PEAK-M 1/6
5 4 3 2 1
5 4 3 2 1
RTC Circuitry C786

15p/50V_4
2
1
+VCCRTC
CR1 Y6
R557
+3VPCU U36A
R586 20K/F_4 RTC_RST# 32.768KHZ 10M_4
VCCRTC_1
3
4
C785
1
RTC_X1 B13 D33
RTCX1 FWH0 / LAD0 LPC_LAD0 <28,37>
BAT54C C796 J1 15p/50V_4 RTC_X2 D13 B33
RTCX2 FWH1 / LAD1 LPC_LAD1 <28,37>
1u/10V_4 *SHORT_ PAD1 C32
FWH2 / LAD2 LPC_LAD2 <28,37>
A32 LPC_LAD3 <28,37>
2
RTC_RST# FWH3 / LAD3
C14
RTCRST#
C34 LPC_LFRAME# <28,37>
SRTC_RST# FWH4 / LFRAME#
D17
D
R326 20K/F_4 SRTC_RST# SRTCRST# D
A34
RTC
LPC
R573 1M_4 SM_INTRUDER# LDRQ0#
+VCCRTC A16 F34
INTRUDER# LDRQ1# / GPIO23
1
R592 R253 10K_4 +3V
1K_4 C798 C781 J2 PCH_INVRMEN A14 AB9
INTVRMEN SERIRQ IRQ_SERIRQ <37>
1u/10V_4 1u/10V_4 *SHORT_ PAD1
2
HDA_SYNC (PCH strap pin) ACZ_BIT_CLK A30
HDA_BCLK SATA_RXN0_C
AK7 SATA_RXN0_C <29>
ACZ_SYNC SATA0RXN SATA_RXP0_C
Internal weak pull-down D29 AK6 SATA_RXP0_C <29>
HDA_SYNC SATA0RXP
VCCVRM=>+1.8V (default) AK11 SATA_TXN0 <29>
VCCRTC_2 SATA0TXN
1 3 RTC_N01 R601 *22K_6
+5V_S5 external pull-up <30> SPKR
SPKR P1 AK9 SATA_TXP0 <29>
SPKR SATA0TXP
Q44 R600 VCCVRM=>+1.5V ACZ_RST# C30
HDA_RST# SATA_RXN1_C
AH6 SATA_RXN1_C <29>
*MMBT3904 *68.1K/F_4 SATA1RXN SATA_RXP1_C
AH5 SATA_RXP1_C <29>
SATA1RXP
<30> PCH_AZ_CODEC_SDIN0 G30 AH9 SATA_TXN1 <29>
2
RTC_N03 HDA_SDIN0 SATA1TXN

BT1 AH8 SATA_TXP1 <29>
SATA1TXP
1 F30
1 HDA_SDIN1
2 AF11
2 R591 SATA2RXN
E32 AF9
IHDA
HDA_SDIN2 SATA2RXP
RTC_CONN AF7
*150K/F_6 SATA2TXN
F32
HDA_SDIN3 SATA2TXP
AF6 Note:
SATA port2/3 may not be available on all PCH sku
AH3
ACZ_SDOUT B29
SATA3RXN
AH1
(HM55 support 3 port only)
HDA_SDO SATA3RXP
AF3
SATA3TXN
AF1
PCH_GPIO33 SATA3TXP
H32
SATA
HDA_DOCK_EN# / GPIO33
AD9
R562 *10K_4 TP20 PCH_GPIO13 SATA4RXN
+3V_S5 J30 AD8
HDA_DOCK_RST# / GPIO13 SATA4RXP
AD6
SATA4TXN
AD5
HDA Bus <25> HDMI_HPD_PCH#
SATA4TXP
M3 AD3
JTAG_TCK SATA5RXN
AD1
SATA5RXP
K3 AB3
R563 33_4 ACZ_SYNC JTAG_TMS SATA5TXN
C
<30> PCH_AZ_CODEC_SYNC AB1 C
SATA5TXP
K1
JTAG_TDI
JTAG
R569 33_4 ACZ_RST# J2 AF16
<30> PCH_AZ_CODEC_RST# JTAG_TDO SATAICOMPO
J4 AF15 R245 37.4/F_4 +1.05V
R568 33_4 ACZ_SDOUT TRST# SATAICOMPI
<30> PCH_AZ_CODEC_SDOUT
SPI_CLK_R BA2
SPI_CLK
R564 33_4 ACZ_BIT_CLK SPI_CS0#_R AV3
<30> PCH_AZ_CODEC_BITCLK SPI_CS0# SATA_ACT# <33>
+3VPCU R485 *10K_4 SPI_CS1# AY3 T3

SPI_CS1# SATALED# PCH_ODD_EN <29>
C787
*27p_4
SPI_SI_R AY1 Y9 R263 43K/F_4 +3V
SPI_MOSI SATA0GP / GPIO21
SPI
SPI_SO_R AV1 V1 R505 43K/F_4 +3V
SPI_MISO SATA1GP / GPIO19
IbexPeak-M_R1P0
PCH Strap Pin Configuration Table-1

INTVRMEN Integrated 1.05V VRM Enable / 1 = Integrated VRM is enabled
R593 330K_6 PCH_INVRMEN
Disable 0 = Integrated VRM is disabled +VCCRTC
SPI_MOSI TPM Functionality 1 = Enabled

Disable R529 *1K_4 SPI_SI_R
0 = Disable +3V
PCH SPI
SPKR Reboot option at power-up 0 = Default Mode (Internal weak Pull-down)
R522 *1K/F_4 SPKR
1 = No Reboot Mode with TCO Disabled +3V
B 0 = Flash Descriptor Security will be overridden B

HDA_DOCK_EN Flash Descriptor 1 = Security measure defined in the Flash
PCH_GPIO33 R286 *1K/F_4
#/GPIO33 Security Override Descriptor will be enabled.
R293 *10K_4 +3V
+3V
U37
SPI_CS0#_R 1 8 R455 1K_4 +3V
SPI_CLK_R CE# VDD R612 1K_4
6
SCK GNT0#, (0,0) = LPC (0,1) = Reserved NAND
SPI_SI_R 5 Boot BIOS Strap R282 *1K_4
SPI_SO_R 2
SI
7 R523 3.3K/F_4 GNT1# (1,0) = PCI (1,1) = SPI <10> PCI_GNT0#
R285 *1K_4
SO HOLD# <10> PCI_GNT1#
3
WP# VSS
4 GNT2#/ ESI compatible mode is for server
C741 ESI Strap
W25Q32BVSSIG .1u/10V_4 GPIO53 platforms only R289 *1K/F_4
(Server Only) <10,24> PWM_SELECT#
GNT3#/ Top-Block 0 = Top Block Swap Mode

R518 3.3K/F_4 R528 *10K/F_4
+3V
GPIO55 Swap Override 1 = Default Mode (Internal pull-up) <10> PCI_GNT3#
IntelR Anti-Theft Technology

HDD Data Protection 1 = Enabled
NV_ALE R225 *1K/F_4
(Intel AT-d) Enable 0 = Disabled (Default) <10> NV_ALE +1.8V
NV_CLE DMI Termination DMI termination voltage. Weak

R224 *1K/F_4
Voltage internal pull-up. Do not pull low. <10> NV_CLE +1.8V
GPIO8 Reserved This signal has a weak internal pull up.

R302 10K_4
NOTE: This signal should not be pulled low<11> RSV_GPIO8 +3V_S5
R295 *1K_4
0 = Intel ME Crypto Transport Layer Security

(TLS) cipher suite with no confidentiality
GPIO15 Reserved
A 1 = Intel ME Crypto Transport Layer Security<11> CR_WAKE# R266 1K_4 +3V_S5 A
(TLS) cipher suite with confidentiality
GPIO27 On-Die PLL Voltage 0 = Disables the VccVRM.

Regulator 1 = Enables the internal VccVRM to have
<internal weak pull-up> a clean supply for analog rails. <11> PCH_GPIO27 R247 *10K_4

PROJECT : ZR7B
1A
IBEX PEAK-M 2/6
5 4 3 2 1
5 4 3 2 1
U36B
U36E
H40 AY9 BG30 B9 RSV_SMBALERT#
AD0 NV_CE#0 <26> PCIE_RX1- PERN1 SMBALERT# / GPIO11
N34 BD1 <26> PCIE_RX1+ BJ30
AD1 NV_CE#1 C704 0.1u/10V_4_X7R PCIE_TXN1_C PERP1 ICH_SMBCLK
C44 AP15 <26> PCIE_TX1- BF29 H14 ICH_SMBCLK <3>
AD2 NV_CE#2 C705 0.1u/10V_4_X7R PCIE_TXP1_C PETN1 SMBCLK
A38 BD8 <26> PCIE_TX1+ BH29
AD3 NV_CE#3 PETP1 ICH_SMBDATA
C36 C8 ICH_SMBDATA <3>
AD4 SMBDATA
J34 AV9 <28> PCIE_RX2- AW30
AD5 NV_DQS0 PERN2
A40 BG8 <28> PCIE_RX2+ BA30
AD6 NV_DQS1 C439 0.1u/10V_4_X7R PCIE_TXN2_C PERP2 RSV_SML0ALERT#
D45 <28> PCIE_TX2- BC30 J14
D AD7 C438 0.1u/10V_4_X7R PCIE_TXP2_C PETN2 SML0ALERT# / GPIO60 D
E36 AP7 <28> PCIE_TX2+ BD30
AD8 NV_DQ0 / NV_IO0 PETP2 SMB_CLK_ME0
H48 AP6 C6 SMB_CLK_ME0 <26>
AD9 NV_DQ1 / NV_IO1 SML0CLK
E40 AT6 AU30
SMBus
AD10 NV_DQ2 / NV_IO2 PERN3 SMB_DATA_ME0
C40 AT9 AT30 G8 SMB_DATA_ME0 <26>
AD11 NV_DQ3 / NV_IO3 PERP3 SML0DATA
M48 BB1 AU32
AD12 NV_DQ4 / NV_IO4 PETN3
M45 AV6 AV32
AD13 NV_DQ5 / NV_IO5 PETP3 RSV_SML1ALERT# R261 *0_4
F53 BB3 M14 SML1ALERT# <11,35,37>
AD14 NV_DQ6 / NV_IO6 SML1ALERT# / GPIO74
M40 BA4 BA32
AD15 NV_DQ7 / NV_IO7 PERN4 SMB_CLK_ME1
NVRAM
M43 BE4 BB32 E10
AD16 NV_DQ8 / NV_IO8 PERP4 SML1CLK / GPIO58
J36 BB6 BD32
AD17 NV_DQ9 / NV_IO9 PETN4 SMB_DATA_ME1
K48 BD6 BE32 G12
AD18 NV_DQ10 / NV_IO10 PETP4 SML1DATA / GPIO75
F40 BB7
PCI-E*
AD19 NV_DQ11 / NV_IO11
C42 BC8 BF33
AD20 NV_DQ12 / NV_IO12 PERN5 CL_CLK1
K46 BJ8 BH33 T13 CL_CLK1 <28>
AD21 NV_DQ13 / NV_IO13 PERP5 CL_CLK1
Controller
M51 BJ6 BG32
AD22 NV_DQ14 / NV_IO14 PETN5 CL_DATA1
J52 BG6 BJ32 T11 CL_DATA1 <28>
AD23 NV_DQ15 / NV_IO15 PETP5 CL_DATA1
K51
Link
AD24 NV_ALE CL_RST1#
L34 BD3 NV_ALE <9> <28> PCIE_RX6- BA34 T9 CL_RST1# <28>
AD25 NV_ALE NV_CLE PERN6 CL_RST1#
F42 AY6 NV_CLE <9> <28> PCIE_RX6+ AW34
AD26 NV_CLE C441 0.1u/10V_4_X7R PCIE_TXN6_C PERP6
J40 <28> PCIE_TX6- BC34
AD27 C440 0.1u/10V_4_X7R PCIE_TXP6_C PETN6
G46 <28> PCIE_TX6+ BD34
AD28 PETP6
F44 AU2 NV_RCOMP R486 *32.4/F_4 H1 PEG_CLKREQ#_R R531 *0_4
PEG_CLKREQ# <17>
AD29 NV_RCOMP PEG_A_CLKRQ# / GPIO47
M47 AT34
AD30 PERN7
PCI
H36 AV7 AU34
AD31 NV_RB# PERP7
AU36 AD43 CLK_PCIE_VGA# <16>
PETN7 CLKOUT_PEG_A_N
J50 AY8 AV36 AD45 CLK_PCIE_VGA <16>
C/BE0# NV_WR#0_RE# PETP7 CLKOUT_PEG_A_P
G42 AY5
C/BE1# NV_WR#1_RE#
H47 BG34 AN4 CLK_PCIE_3GPLL# <4>
C/BE2# PERN8 CLKOUT_DMI_N
PEG
G34 AV11 BJ34 AN2 CLK_PCIE_3GPLL <4>
C/BE3# NV_WE#_CK0 PERP8 CLKOUT_DMI_P
BF5 BG36
PCI_PIRQA# NV_WE#_CK1 PETN8
G38 BJ36
PCI_PIRQB# PIRQA# PETP8
H51 AT1 DPLL_REF_SSCLK# <4>
PCI_PIRQC# PIRQB# CLKOUT_DP_N / CLKOUT_BCLK1_N
B37
PIRQC# USBP0N
H18 TP31 Port1 and port9 can be used on debug mode CLKOUT_DP_P / CLKOUT_BCLK1_P
AT3 DPLL_REF_SSCLK <4>
PCI_PIRQD# A44 J18 AK48
PIRQD# USBP0P TP19 CLKOUT_PCIE0N
A18 USBP1- <34> AK47
USBP1N CLKOUT_PCIE0P
From CLK BUFFER

PCI_REQ0# F51 C18 MB USB AW24
C PCI_REQ1# REQ0# USBP1P USBP1+ <34> CLK_PCIE_REQ0# CLKIN_DMI_N CLK_BUF_PCIE_3GPLL# <3> C
A46 N20 TP15 P9 BA24 CLK_BUF_PCIE_3GPLL <3>
dGPU_SELECT# REQ1# / GPIO50 USBP2N PCIECLKRQ0# / GPIO73 CLKIN_DMI_P
<24> dGPU_SELECT# B45 P20 TP13
PCI_REQ3# REQ2# / GPIO52 USBP2P
M53 J20 USBP3- <34>
REQ3# / GPIO54 USBP3N
USBP3P
L20 USBP3+ <34> USB/B-USB1-3 <28> CLK_PCH_SRC1# AM43
CLKOUT_PCIE1N CLKIN_BCLK_N
AP3 CLK_BUF_BCLK# <3>
PCI_GNT0# F48 F20 EHCI1 AM45 AP1
<9> PCI_GNT0# PCI_GNT1# GNT0# USBP4N USBP4- <34> <28> CLK_PCH_SRC1 CLKOUT_PCIE1P CLKIN_BCLK_P CLK_BUF_BCLK <3>
<9> PCI_GNT1# K45
GNT1# / GPIO51 USBP4P
G20 USBP4+ <34> BLUETOOTH
PWM_SELECT# F36 A20 R503 *Short_4 CLK_PCIE_REQ1#_R U4
<9,24> PWM_SELECT# GNT2# / GPIO53 USBP5N USBP5- <28> <28> CLKREQ_3G# PCIECLKRQ1# / GPIO18
PCI_GNT3# H53 C20 F18
<9> PCI_GNT3# GNT3# / GPIO55 USBP5P USBP5+ <28> CLKIN_DOT_96N CLK_BUF_DREFCLK# <3>
M22 E18 CLK_BUF_DREFCLK <3>
PCI_PIRQE# USBP6N USB port6/7 may not be available on all PCH sku CLKIN_DOT_96P
B41 N22 <28> CLK_PCH_SRC2# AM47
PCI_PIRQF# PIRQE# / GPIO2 USBP6P CLKOUT_PCIE2N
K53 B21 (HM55 support 12port only) <28> CLK_PCH_SRC2 AM48
PCI_PIRQG# PIRQF# / GPIO3 USBP7N CLKOUT_PCIE2P
A36 D21 AH13 CLK_BUF_DREFSSCLK# <3>
PCI_PIRQH# PIRQG# / GPIO4 USBP7P R526 *Short_4 CLK_PCIE_REQ2#_R CLKIN_SATA_N / CKSSCD_N
A48 H22 USBP8- <24> <28> PCIE_CLK_REQ2# N4 AH12 CLK_BUF_DREFSSCLK <3>
PIRQH# / GPIO5 USBP8N PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P
USBP8P
J22 USBP8+ <24> Camera
USB
PCI_RST# K6 E22
<28> PCI_RST# PCIRST# USBP9N USBP9- <34>
USBP9P
F22 USBP9+ <34> USB/B-USB1-2 AH42
CLKOUT_PCIE3N REFCLK14IN
P41 CLK_ICH_14M <3>
PCI_SERR# E44 A22 AH41
PCI_PERR# SERR# USBP10N USBP10- <28> CLKOUT_PCIE3P
E50 C22 Mini Card (3G) C722 18p/50V_4
PERR# USBP10P USBP10+ <28> CLK_PCIE_REQ3# CLK_PCI_FB
USBP11N
G24 USBP11- <34> EHCI2 A8
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK
J42
USBP11P
H24 USBP11+ <34> USB/B-USB1-1
1
PCI_IRDY# A42 L24
PCI_PAR IRDY# USBP12N USBP12- <32> XTAL25_IN
TP25 H44 M24 Card Reader AM51 AH51 R492 Y4
PCI_DEVSEL# PAR USBP12P USBP12+ <32> CLKOUT_PCIE4N XTAL25_IN XTAL25_OUT
F46 A24 AM53 AH53 1M_4 25MHz
PCI_FRAME# DEVSEL# USBP13N USBP13- <28> CLKOUT_PCIE4P XTAL25_OUT
C46 C24 Mini Card (WLAN)
2
FRAME# USBP13P USBP13+ <28> CLK_PCIE_REQ4# M9 AF38 XCLK_RCOMP R238 90.9/F_4 +1.05V C726 18p/50V_4
PCI_PLOCK# PCIECLKRQ4# / GPIO26 XCLK_RCOMP
D49
PLOCK#
B25 USB_BIAS R561 22.6/F_4
PCI_STOP# USBRBIAS# BOARD_ID1
D41 AJ50 T45
PCI_TRDY# STOP# CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
C48 D25 AJ52
TRDY# USBRBIAS CLKOUT_PCIE5P
ICH_PME# M7 CLK_PCIE_REQ5# H6 P43 BOARD_ID2
Clock Flex
TP21 PME# PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65
N16 USB_OC0#
OC0# / GPIO59 TP26 USB_OC0# <34>
PCI_PLTRST# D5 J16 USB_OC1#
PLTRST# OC1# / GPIO40 TP16 USB_OC1# <34>
F16 USB_OC2# AK53 T42 BOARD_ID3
OC2# / GPIO41 TP30 <26> CLK_PCIE_LOM# CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
R516 22_4 CLK_LPC_DEBUG_C N52 L16 USB_OC3# AK51
<28> CLK_LPC_DEBUG CLKOUT_PCI0 OC3# / GPIO42 TP17 <26> CLK_PCIE_LOM CLKOUT_PEG_B_P
CLK_PCI_PCCARD P53 E14 USB_OC4_5#
B
TP22 CLKOUT_PCI1 OC4# / GPIO43 USB_OC4_5# <34> B
R281 22_4 CLK_PCI_775_C P46 G16 R501 *Short_4 PCIE_CLK_REQB# P13 N50
<37> CLK_PCI_775 CLKOUT_PCI2 OC5# / GPIO9 <26> CLK_PCIE_LAN_REQ# PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67 dGPU_EDIDSEL# <24>
CLK_PCI_FB R277 22_4 CLK_PCI_FB_C P51 F12 USB_OC6#
CLKOUT_PCI3 OC6# / GPIO10 TP28
P48 T15 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14 TP32
IbexPeak-M_R1P0 R271 10K_4 +3V
IbexPeak-M_R1P0
+3V +3V_S5
+3V_S5
+3V_S5 R629 *10K_4 BOARD_ID1 R630 *10K_4
RP1 R276 10K_4 CLK_PCIE_REQ0#
USB_OC7# 6 5 R543 10K_4 CLK_PCIE_REQ3# R631 *10K_4 BOARD_ID2 R632 *10K_4 R310
USB_OC6# 7 4 USB_OC0# R280 10K_4 CLK_PCIE_REQ4#
2
USB_OC4_5# 8 3 USB_OC1# R283 10K_4 CLK_PCIE_REQ5# R633 *10K_4 BOARD_ID3 R634 *10K_4 2.2K_4
9 2 USB_OC2# R510 10K_4 PCIE_CLK_REQB#
+3V_S5 10 1 USB_OC3# R535 IV@10K_4 PEG_CLKREQ#_R 1 3 SMB_CLK_ME1
+3V_S5 <37> 2ND_MBCLK
Q19
8.2K_10P8R +3V 2N7002K
C507 R504 10K_4 CLK_PCIE_REQ1#_R High = JV41_CP(ZQ1) +3V_S5

+3V BOARD_ID1
.1u/10V_4 RP4 +3V Low = JM41_CP(ZQ1B)
PCI_PIRQD# 6 5
5
PCI_REQ1# 7 4 PCI_REQ3# High = 80port output to LPC

PCI_PLTRST# 2 PCI_FRAME# 8 3 PCI_PIRQB# BOARD_ID2 R311
4 PCI_TRDY# 9 2 PCI_REQ0# R294 10K_4 dGPU_SELECT# Low = 80port output to PCI
PLTRST# <4,11,26,28,32,37>
2
1 10 1 PCI_PIRQH# R304 8.2K_4 PCI_PIRQE# 2.2K_4
A
+3V A
R272 8.2K_4 PCI_PIRQF# High = Reserved
U18 R313 8.2K_10P8R R580 8.2K_4 PCI_PIRQG# BOARD_ID3 1 3 SMB_DATA_ME1
3
PCIE_CLK_REQ2# <37> 2ND_MBDATA

TC7SH08FU R576 10K_4 Low = Reserved (Default) Q20
100K_4 2N7002K
+3V R533 SW@10K/F_4 PEG_CLKREQ#_R
RP5
PCI_PIRQC# 6 5
R312 *0_4 PCI_PIRQA# 7 4 PCI_PERR#
PCI_STOP# 8 3 PCI_PLOCK# +3V_S5
PCI_IRDY# 9 2 PCI_DEVSEL#
+3V 10 1 PCI_SERR# R559
R308
10K_4
10K_4
RSV_SMBALERT#
RSV_SML0ALERT#
8.2K_10P8R R265 10K_4 RSV_SML1ALERT#
R303 2.2K_4 ICH_SMBCLK PROJECT : ZR7B
R327 2.2K_4 ICH_SMBDATA Size Document Number Rev
R536 2.2K_4 SMB_CLK_ME0 1A
R298 2.2K_4 SMB_DATA_ME0 IBEX PEAK-M 3/6
5 4 3 2 1
5 4 3 2 1
GPU RST#
D +3V D
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD) C609 *.1u_4
U36F
5
TP37 BMBUSY# Y3 AH45 1
BMBUSY# / GPIO0 CLKOUT_PCIE6N PLTRST# <4,10,26,28,32,37>
CLKOUT_PCIE6P AH46 <16> GPU_RST# 4
<37> SIO_EXT_SMI# SIO_EXT_SMI# C38 2 dGPU_HOLD_RST#
TACH1 / GPIO1
3
<37> SIO_EXT_SCI# SIO_EXT_SCI# D37 U27
TACH2 / GPIO6 TC7SH08FU R414
CLKOUT_PCIE7N AF48
MISC
TP38 BOARD_ID0 J32 AF47 100K_4
TACH3 / GPIO7 CLKOUT_PCIE7P
RSV_GPIO8 F10
<9> RSV_GPIO8 GPIO8
TP18 LAN_DISABLE# K9 U2
LAN_PHY_PWR_CTRL / GPIO12 A20GATE SIO_A20GATE <37>
CR_WAKE# T7
<9> CR_WAKE# GPIO15
dGPU_HOLD_RST# AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# <4>
<21> dGPU_PWROK F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK <4>
GPIO22 Y7 BG10
SCLOCK / GPIO22 PECI H_PECI <4>
GPIO
TP24 H10 T1
GPIO Pull-up/Pull-down
GPIO24 RCIN# SIO_RCIN# <37>
PCH_GPIO27 AB12 BE10
<9> PCH_GPIO27 GPIO27 PROCPWRGD H_PWRGOOD <4>
CPU
+3V_S5
TP_PCH_GPIO28 V13 BD10 PCH_THRMTRIP#_R R222 56/F_4
GPIO28 THRMTRIP# PM_THRMTRIP# <4>
C C
STP_PCI# M11 R217 56/F_4 +1.1V_VTT
STP_PCI# / GPIO34 TP_PCH_GPIO28 R511 10K_4
V6 GPIO45 R537 10K_4
<21,44> dGPU_VRON SATACLKREQ# / GPIO35 RST_GATE# R322 10K_4
<39> dGPU_PWR_EN# dGPU_PWR_EN# AB7 BA22 GPIO57 R309 *10K_4
SATA2GP / GPIO36 TP1 LAN_DISABLE# R279 10K_4
dGPU_PWR_EN# should be stable TP10 dGPU_PRSNT# AB13 AW22
before dGPU_VRON enable SATA3GP / GPIO37 TP2 +3V
GPIO38 V3 BB22
SLOAD / GPIO38 TP3 SIO_EXT_SMI# R299 10K_4
SAVE_LED# SAVE_LED# P3 AY45 SIO_EXT_SCI# R570 10K_4
SDATAOUT0 / GPIO39 TP4
GPIO45 H3 AY46 dGPU_PWR_EN# R251 10K_4
PCIECLKRQ6# / GPIO45 TP5
<36> RST_GATE# F1 AV43

PCIECLKRQ7# / GPIO46 TP6
SV_SET_UP AB6 AV45 +3V
SDATAOUT1 / GPIO48 TP7
<10,35,37> SML1ALERT# R256 *Short_4 SATA5GP AA4 AF13 SIO_RCIN# R515 10K_4
SATA5GP / GPIO49 TP8 SIO_A20GATE R514 10K_4
EC suggestion use GPIO49 for FAN control GPIO57 F8 M18 dGPU_HOLD_RST# R246 *10K_4
GPIO57 TP9 SATA5GP R250 10K_4
N18 GPIO22 R262 10K_4
TP10
A4 AJ24 SAVE_LED# R521 10K_4
VSS_NCTF_1 TP11 STP_PCI# R274 10K_4
A49
NCTF
VSS_NCTF_2
RSVD
SATA5GP / GPIO49 / TEMP_ALERT# is used to A5

VSS_NCTF_3 TP12
AK41
A50 GPIO38 R497 10K_4
alert for EC when CPU or Graph/Memory A52
VSS_NCTF_4
AK42
VSS_NCTF_5 TP13
B
controllers' temperature go out of limit. A53
VSS_NCTF_6
BMBUSY# R252 8.2K_4
B
So connecting GPIO49 to EC and avoid this B2 M32
VSS_NCTF_7 TP14 SV_SET_UP R257 10K_4
B4
pin to be used for other purpose VSS_NCTF_8
B52 N32
VSS_NCTF_9 TP15
B53 VSS_NCTF_10
BE1 M30 SV_SET_UP 1-X High = Strong (Default)
VSS_NCTF_11 TP16
BE53
VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
BF53
VSS_NCTF_14 GPIO57 stuff PD and not stuff PU for Intel suggestion at 6/1
BH1 H12
VSS_NCTF_15 TP18
BH2
VSS_NCTF_16 GPIO57 R301 10K_4
BH52 VSS_NCTF_17 TP19 AA23
BH53 VSS_NCTF_18
BJ1 AB45
VSS_NCTF_19 NC_1
BJ2
VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
BJ49
VSS_NCTF_22 R575 *10K_4 BOARD_ID0 R579 10K_4
BJ5 VSS_NCTF_23 NC_3 AB42 +3V
BJ50 VSS_NCTF_24
BJ52 AB41 R239 IV@10K_4dGPU_PRSNT# R240 SW@10K_4
VSS_NCTF_25 NC_4
BJ53 VSS_NCTF_26
D1 T39 dGPU always exist
VSS_NCTF_27 NC_5
D2
VSS_NCTF_28
D53
VSS_NCTF_29 TP_INT3_3V
E1 P6
VSS_NCTF_30 INIT3_3V# TP11 High = JV41/JM41
E53
VSS_NCTF_31 BOARD_ID0
C10
TP24
Low = JM51
IbexPeak-M_R1P0
High = Disable
RSV_GPIO8
A Low = Enable A

PROJECT : ZR7B
1A
IBEX PEAK-M 4/6
5 4 3 2 1
5 4 3 2 1
IBEX PEAK-M (POWER) U36G POWER VCCADAC= 69mA(15mils)

+1.05V R242 *SHORT0805
+1.05V_VCCCORE_ICH AB24 AE50 +VCCA_DAC_1_2 L52 +3V
VCCCORE[1] VCCADAC[1] PBY160808T/2A/180ohm_6
AB26
R241 *SHORT0805 VCCCORE[2]
AB28 AE52
C481 C479 VCCCORE[3] VCCADAC[2] C732 C739 C733
AD26
VCCCORE[4]
CRT
AD28 AF53
10u/6.3V_8 1u/6.3V_4 AF26
VCCCORE[5]
VCCCORE[6]
VSSA_DAC[1] .01u/25V_4 10u/10V_6 0.1u/10V_4_X7R U36J POWER VCCIO = 3.208A(150mils)
VCC CORE
AF28
VCCCORE[7] VSSA_DAC[2]
AF51 VCCACLK= 52mA(15mils)
AF30 VCCALVDS= 1mA +1.05V L48 *10uh_8 +V1.1LAN_VCCA_CLK AP51 V24 +1.05V
VCCCORE[8] C717 *10u/6.3V_6 VCCACLK[1] VCCIO[5]
AF31 V26
VCCCORE[9] C718 *1u/6.3V_4 VCCIO[6] C489 1U/6.3V_4
AH26 AP53 Y24
VCCCORE[10] VCCACLK[2] VCCIO[7]
VCCCORE(+1.05V) = 1.432A(80mils) AH28 Y26
VCCCORE[11] VCCALVDS R248 *Short_4 VCCIO[8]
AH30
VCCCORE[12] +3V VCCLAN = 320mA(30mils)
AH31 AH38 +1.05V R244 *0_6 +1.05V_VCCAUX AF23 V28 +3V_S5_VCCPUSB R305 *SHORT0805 +3V_S5
D VCCCORE[13] VCCALVDS VCCLAN[1] VCCSUS3_3[1] D
AJ30 U28
VCCCORE[14] VCCSUS3_3[2] C496 0.1u/10V_4_X7R
AJ31 AH39 AF24 U26
VCCCORE[15] VSSA_LVDS VCCLAN[2] VCCSUS3_3[3] C497 0.1u/10V_4_X7R
U24
C482 VCCSUS3_3[4] C501 0.022U/16V_4
VCCTX_LVDS= 59mA(15mils) VCCSUS3_3[5]
P28
AP43 1U/6.3V_4 TP_PCH_VCCDSW Y20 P26
VCCTX_LVDS[1] VCCTX_LVDS L33 0.1UH_8/250mA +1.8V DCPSUSBYP VCCSUS3_3[6]
AP45 N28
VCCTX_LVDS[2] VCCSUS3_3[7]
AT46 N26
LVDS
R218 *short_6 +1.05V_PCH_VCCDPLL_EXP VCCTX_LVDS[3] C468 C469 C470 C487 VCCSUS3_3[8]
+1.05V AK24 AT45 AD38 M28
VCCIO[24] VCCTX_LVDS[4] C482 change to 0 ohm resistor. VCCME[1] VCCSUS3_3[9]
1u/6.3V_4 M26
.01u/25V_4 .01u/25V_4 22u/6.3V_8 VCCSUS3_3[10]
AD39 L28
VCCSUS3_3 = 0.163A(20mils)
USB
L30 *1uh_6 +V1.1LAN_VCCAPLL_EXP VCCME[2] VCCSUS3_3[11]
40mA(15mils) +1.05V BJ24 L26
VCCAPLLEXP VCCSUS3_3[12]
AB34 AD41 J28
C437 *10u/6.3V_6 VCC3_3[2] VCCME[3] VCCSUS3_3[13]
J26
VCCSUS3_3[14] R267 *short_6
AN20
VCCIO[25] VCC3_3[3]
AB35 VCC3_3 = 357mA(30mils) AF43
VCCME[4] VCCSUS3_3[15]
H28 +1.05V
AN22 H26
HVCMOS
VCCIO[26] +3V_VCC_GIO R264 *short_6 +3V VCCSUS3_3[16]
AN23 AD35 VCCME(+1.05V) = 1.849A(100mils) AF41 G28
AN24
VCCIO[27]
VCCIO[28]
VCC3_3[4] VCCME[5] VCCSUS3_3[17]
VCCSUS3_3[18]
G26 V5REF_SUS< 1mA
AN26 C483 +1.05V R249 *SHORT0805 +1.05V_VCCEPW AF42 F28 R574 100/F_4 +5V_S5
VCCIO[29] VCCME[6] VCCSUS3_3[19]
VCCIO = 3.062A(150mils) AN28
VCCIO[30] VCCSUS3_3[20]
F26
+1.05V BJ26 .1u/16V_4 R260 *SHORT0805 V39 E28 D18 RB500V-40 +3V_S5
Clock and Miscellaneous

BJ28 E26
VCCIO[32] VCCSUS3_3[22] C788 1U/6.3V_4
AT26 V41 C28
AT28 C26
VCCIO[34] C485 22U/6.3V_8 VCCSUS3_3[24]
AU26 V42 B27
AU28
VCCIO[36]
VCCVRM= 196mA(15mils) VCCSUS3_3[26]
A28
C467 10U/6.3V_8 AV26 C491 22U/6.3V_8 Y39 A26
C446 1U/6.3V_4 VCCIO[37] +VCCVRM R235 *short_6 VCCME[10] VCCSUS3_3[27]
AV28 AT24
C458 1U/6.3V_4 AW26
VCCIO[38]
VCCIO[39]
VCCVRM[2] +V1.5S_1.8S
C488 1U/6.3V_4 Y41
VCCME[11] VCCSUS3_3[28]
U23 V5REF< 1mA
C478 1U/6.3V_4 AW28 R288 100/F_4 +5V
VCCIO[40]
DMI
C452 1U/6.3V_4 BA26 AT16 +VCCDMI R231 *Short_4 +1.1V_VTT VCCDMI= 61mA(15mils) C490 1U/6.3V_4 Y42 V23
VCCIO[41] VCCDMI[1] VCCME[12] VCCIO[56] D14 RB500V-40
BA28 +3V
VCCIO[42] V5REF_SUS
BB26 AU16 F24
C VCCIO[43] VCCDMI[2] V5REF_SUS C499 1U/6.3V_4 C
BB28
VCCIO[44] +VCCRTCEXT
BC26 V9
VCCIO[45] DCPRTC
PCI E*
BC28 C463 C492 0.1u/10V_4_X7R
VCCIO[46] 1u/10V_4
BD26
VCCIO[47] V5REF
BD28 K49
VCCIO[48] V5REF
BE26 AM16 +V1.5S_1.8S AU24
PCI/GPIO/LPC
VCCIO[49] VCCPNAND[1] VCCVRM[3]
BE28
VCCIO[50] VCCPNAND[2]
AK16 VCCPNAND= 156mA(15mils)
BG26 AK20 J38 +3V_VCCPPCI R284 *short_6 +3V
VCCIO[51] VCCPNAND[3] VCCPNAND R221 *SHORT0805 VCC3_3[8]
BG28 AK19 +1.8V BB51
VCCIO[52] VCCPNAND[4] +V1.1LAN_VCCA_A_DPL VCCADPLLA[1]
BH27
VCCIO[53] VCCPNAND[5]
AK15 68mA(15mils) BB53
VCCADPLLA[2] VCC3_3[9]
L38 VCC3_3 = 0.357A(30mils)
AK13 C476 C500 0.1u/10V_4_X7R
VCCPNAND[6]
AN30 AM12 M36
VCCIO[54] VCCPNAND[7] VCC3_3[10]
NAND / SPI
AN31 AM13 .1u/16V_4 69mA(15mils) +V1.1LAN_VCCA_B_DPL BD51
VCCIO[55] VCCPNAND[8] VCCADPLLB[1]
AM15 BD53 N36
VCCPNAND[9] VCCADPLLB[2] VCC3_3[11] C498 0.1u/10V_4_X7R
+3V R232 *short_6 +3V_VCCA3GBG AN35 +1.05V AH23 P36
VCC3_3[1] VCCIO[21] VCC3_3[12]
AJ35
VCCIO[22]
37mA(15mils) VCCIO = 3.062A(150mils) AH35
VCCIO[23] VCC3_3[13]
U35
+V1.5S_1.8S R234 *short_6 +VCCAFDI_VRM AT22
VCCVRM[1] C475 1U/6.3V_4
VCCME3_3= 85mA(15mils) AF34
VCCIO[2]
+1.05V L29 *1uH_6 +V1.1LAN_VCCAPLL_FDI BJ18 AM8 C473 1U/6.3V_4 AD13
VCCFDIPLL VCCME3_3[1] +3V_VCCME_SPIR236 *short_6 +3V C474 1U/6.3V_4 VCC3_3[14]
AM9 AH34
VCCME3_3[2] VCCIO[3]
FDI
+1.05V_VCCDPLL_FDI AM23 AP11 31mA(15mils)

C436 VCCIO[1] VCCME3_3[3] C472
AP9 AF32
*10u/6.3V_6 VCCME3_3[4] VCCIO[4] +V1.1LAN_VCCAPLL L50 *10uh_8
AK3 +1.05V
.1u/16V_4 +VCCSST VCCSATAPLL[1]
V12 AK1
C493 0.1u/10V_4_X7R DCPSST VCCSATAPLL[2] C730 C729
IbexPeak-M_R1P0 *1u/6.3V_4 *10u/6.3V_6
+V1.1LAN_INT_VCCSUS Y22 VCCIO = 3.062A(150mils)

C484 0.1u/10V_4_X7R DCPSUS +V1.1LAN_VCC_SATA R259 *SHORT1206+1.05V
AH22
R237 *short_6 VCCIO[9]
B
+1.05V B
P18 AT20 +V1.5S_1.8S C480
VCCSUS3_3[29] VCCVRM[4] 1u/10V_4
VCCSUS3_3 = 163mA(20mils)
VCCVRM=196mA(15mils) HDA_SYNC (PCH strap pin) +3V_S5 R307 *short_6 +3V_S5_VCCPSUS U19
SATA
VCCSUS3_3[30]
PCI/GPIO/LPC
AH19
R219 *short_6 VCCIO[10]
+1.8V +V1.5S_1.8S Internal weak pull-down U20
VCCSUS3_3[31]
VCCVRM=>+1.8V (default) AD20
C494 0.1u/10V_4_X7R U22 VCCIO[11]
C445 C444
external pull-up VCCSUS3_3[32]
AF22
.1u/16V_4 .1u/16V_4 VCCVRM=>+1.5V VCCIO[12]
VRM enable by strap pin GPIO27 VCC3_3 = 0.357A(30mils) VCCIO[13]
AD19
+3V R255 *short_6 +3V_VCCPCORE V15 AF20
which supply clean 1.05V for VCC3_3[5] VCCIO[14]
AF19
[VCCACLK,VCCAPLLEXP,VCCFDIPLL,VCCSATAPLL] VCCIO[15]
V16 AH20
VCC3_3[6] VCCIO[16]
C486 0.1u/10V_4_X7R Y16 AB19
VCC3_3[7] VCCIO[17]
AB20
L47 10uh_8 +V1.1LAN_VCCA_A_DPL VCCIO[18]
+1.05V AB22
VCCIO[19]
V_CPU_IO >1mA(15mils) AD22
C713 + R228 *short_6 +VTT_VCCPCPU VCCIO[20]
+1.1V_VTT AT18
V_CPU_IO[1]
VCCME = 1.849A(100mils)
220u_3528 C708 R484 AA34 +1.05V_VCCEPW
CPU
1u/10V_4 C459 4.7U/6.3V_6 VCCME[13]
*0_8 Y34
C461 0.1u/10V_4_X7R VCCME[14]
AU18 Y35
L46 10uh_8 +V1.1LAN_VCCA_B_DPL C462 0.1u/10V_4_X7R V_CPU_IO[2] VCCME[15]
AA35
VCCME[16]
C703 + VCCRTC= 2mA(15mils)
RTC
C696 +VCCRTC A12 L30 +V3.3A_1.5A_HDA_IO R273 *Short_4 +3V_S5
VCCRTC VCCSUSHDA
HDA
220u_3528 1u/10V_4
C782 0.1u/10V_4_X7R VCCSUSHDA= 6mA(15mils)
C771 0.1u/10V_4_X7R IbexPeak-M_R1P0 C502
1u/10V_4
A A

PROJECT : ZR7B
1A
IBEX PEAK-M 5/6
5 4 3 2 1
5 4 3 2 1
U36I
AY7 H49
IBEX PEAK-M (GND) B11
B15
VSS[159]
VSS[160]
VSS[259]
VSS[260] H5
J24
VSS[161] VSS[261]
D B19 VSS[162] VSS[262] K11 D
B23 VSS[163] VSS[263] K43
B31 VSS[164] VSS[264] K47
B35 VSS[165] VSS[265] K7
B39 VSS[166] VSS[266] L14
B43 VSS[167] VSS[267] L18
B47 VSS[168] VSS[268] L2
B7 VSS[169] VSS[269] L22
BG12 VSS[170] VSS[270] L32
BB12 VSS[171] VSS[271] L36
U36H BB16 L40
VSS[172] VSS[272]
AB16 VSS[0] BB20 VSS[173] VSS[273] L52
BB24 VSS[174] VSS[274] M12
AA19 VSS[1] VSS[80] AK30 BB30 VSS[175] VSS[275] M16
AA22 VSS[3] VSS[82] AK32 BB38 VSS[177] VSS[277] N38
AM19 VSS[4] VSS[83] AK34 BB42 VSS[178] VSS[278] M34
AA28 VSS[7] VSS[86] AK43 BC10 VSS[181] VSS[281] M46
AB11 VSS[11] VSS[90] AK8 BC22 VSS[185] VSS[285] N24
AB15 VSS[12] VSS[91] AL2 BC32 VSS[186] VSS[286] P11
AB23 VSS[13] VSS[92] AL52 BC36 VSS[187] VSS[287] AD15
AB30 VSS[14] VSS[93] AM11 BC40 VSS[188] VSS[288] P22
AB31 VSS[15] VSS[94] BB44 BC44 VSS[189] VSS[289] P30
AB32 VSS[16] VSS[95] AD24 BC52 VSS[190] VSS[290] P32
AB39 VSS[17] VSS[96] AM20 BH9 VSS[191] VSS[291] P34
AB43 VSS[18] VSS[97] AM22 BD48 VSS[192] VSS[292] P42
C C
AB8 VSS[21] VSS[100] AM28 BE12 VSS[195] VSS[295] R2
AC2 VSS[22] VSS[101] BA42 BE16 VSS[196] VSS[296] R52
AC52 VSS[23] VSS[102] AM30 BE20 VSS[197] VSS[297] T12
AD11 VSS[24] VSS[103] AM31 BE24 VSS[198] VSS[298] T41
AD31 VSS[29] VSS[108] AM39 BE46 VSS[203] VSS[303] U30
AD32 VSS[30] VSS[109] AM42 BE48 VSS[204] VSS[304] U31
AD34 VSS[31] VSS[110] AU20 BE50 VSS[205] VSS[305] U32
AU22 VSS[32] VSS[111] AM46 BE6 VSS[206] VSS[306] U34
AD42 VSS[33] VSS[112] AV22 BE8 VSS[207] VSS[307] P38
AD46 VSS[34] VSS[113] AM49 BF3 VSS[208] VSS[308] V11
AD49 VSS[35] VSS[114] AM7 BF49 VSS[209] VSS[309] P16
AD7 VSS[36] VSS[115] AA50 BF51 VSS[210] VSS[310] V19
AE2 VSS[37] VSS[116] BB10 BG18 VSS[211] VSS[311] V20
AE4 VSS[38] VSS[117] AN32 BG24 VSS[212] VSS[312] V22
AF12 VSS[39] VSS[118] AN50 BG4 VSS[213] VSS[313] V30
Y13 VSS[40] VSS[119] AN52 BG50 VSS[214] VSS[314] V31
AH49 VSS[41] VSS[120] AP12 BH11 VSS[215] VSS[315] V32
AU4 VSS[42] VSS[121] AP42 BH15 VSS[216] VSS[316] V34
AF35 VSS[43] VSS[122] AP46 BH19 VSS[217] VSS[317] V35
AP13 VSS[44] VSS[123] AP49 BH23 VSS[218] VSS[318] V38
AN34 VSS[45] VSS[124] AP5 BH31 VSS[219] VSS[319] V43
AF45 VSS[46] VSS[125] AP8 BH35 VSS[220] VSS[320] V45
AF46 VSS[47] VSS[126] AR2 BH39 VSS[221] VSS[321] V46
AF49 VSS[48] VSS[127] AR52 BH43 VSS[222] VSS[322] V47
AF5 VSS[49] VSS[128] AT11 BH47 VSS[223] VSS[323] V49
AF8 VSS[50] VSS[129] BA12 BH7 VSS[224] VSS[324] V5
B AG2 AH48 C12 V7 B
VSS[51] VSS[130] VSS[225] VSS[325]
AG52 VSS[52] VSS[131] AT32 C50 VSS[226] VSS[326] V8
AH11 VSS[53] VSS[132] AT36 D51 VSS[227] VSS[327] W2
AH15 VSS[54] VSS[133] AT41 E12 VSS[228] VSS[328] W52
AH16 VSS[55] VSS[134] AT47 E16 VSS[229] VSS[329] Y11
AH24 VSS[56] VSS[135] AT7 E20 VSS[230] VSS[330] Y12
AH32 VSS[57] VSS[136] AV12 E24 VSS[231] VSS[331] Y15
AV18 VSS[58] VSS[137] AV16 E30 VSS[232] VSS[332] Y19
AJ19 VSS[62] VSS[141] AV34 E46 VSS[236] VSS[336] Y31
AJ23 VSS[66] VSS[145] AV49 F49 VSS[240] VSS[340] Y46
AJ26 VSS[67] VSS[146] AV5 F5 VSS[241] VSS[341] P49
AJ28 VSS[68] VSS[147] AV8 G10 VSS[242] VSS[342] Y5
AJ32 VSS[69] VSS[148] AW14 G14 VSS[243] VSS[343] Y6
AJ34 VSS[70] VSS[149] AW18 G18 VSS[244] VSS[344] Y8
AT5 VSS[71] VSS[150] AW2 G2 VSS[245] VSS[345] P24
AJ4 VSS[72] VSS[151] BF9 G22 VSS[246] VSS[346] T43
AK12 VSS[73] VSS[152] AW32 G32 VSS[247] VSS[347] AD51
AM41 VSS[74] VSS[153] AW36 G36 VSS[248] VSS[348] AT8
AN19 VSS[75] VSS[154] AW40 G40 VSS[249] VSS[349] AD47
AK26 VSS[76] VSS[155] AW52 G44 VSS[250] VSS[350] Y47
AK22 VSS[77] VSS[156] AY11 G52 VSS[251] VSS[351] AT12
AK23 VSS[78] VSS[157] AY43 AF39 VSS[252] VSS[352] AM6
AK28 VSS[79] VSS[158] AY47 H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
IbexPeak-M_R1P0 H30 AK45
VSS[255] VSS[355]
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]
IbexPeak-M_R1P0
PROJECT : ZR7B
1A
IBEX PEAK-M 6/6
5 4 3 2 1
5 4 3 2 1
+1.5V_SUS
JDIM1B
JDIM1A M_A_DQ[63:0] <5>
<5> M_A_A[15:0] 75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ0 76 48
M_A_A1 A0 DQ0 M_A_DQ1 VDD2 VSS17
97 A1 DQ1 7 81 VDD3 VSS18 49
M_A_A2 96 15 M_A_DQ2 82 54
95 A3 DQ3 17 87 VDD5 VSS20 55
M_A_A4 92 4 M_A_DQ4 88 60
91 A5 DQ5 6 93 VDD7 VSS22 61
M_A_A6 90 16 M_A_DQ6 94 65
M_A_A7 86
A6 DQ6
18 M_A_DQ7
2.48A 99
VDD8 VSS23
66
D 89 A8 DQ8 21 100 VDD10 VSS25 71 D
M_A_A9 85 23 M_A_DQ9 105 72
PC2100 DDR3 SDRAM SO-DIMM

107 A10/AP DQ10 33 106 VDD12 VSS27 127
M_A_A11 84 35 M_A_DQ11 111 128
83 A12/BC# DQ12 22 112 VDD14 VSS29 133
M_A_A13 119 24 M_A_DQ13 117 134
80 A14 DQ14 34 118 VDD16 VSS31 138
M_A_A15 78 36 M_A_DQ15 123 139
A15 DQ15 M_A_DQ16 VDD17 VSS32

DQ16 39 124 VDD18 VSS33 144
109 41 M_A_DQ17 145
<5> M_A_BS#0 BA0 DQ17 VSS34
108 51 M_A_DQ18 199 150
<5> M_A_BS#1 BA1 DQ18 +3V VDDSPD VSS35
79 53 M_A_DQ19 151
<5> M_A_BS#2 BA2 DQ19 VSS36
114 40 M_A_DQ20 77 155
<5> M_A_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 122 156
<5> M_A_CS#1 S1# DQ21 NC2 VSS38
101 50 M_A_DQ22 125 161
<5> M_A_CLK0 CK0 DQ22 NCTEST VSS39
103 52 M_A_DQ23 162
<5> M_A_CLK0# CK0# DQ23 VSS40
102 57 M_A_DQ24 198 167
<5> M_A_CLK1 CK1 DQ24 <4> PM_EXTTS#0 EVENT# VSS41
104 59 M_A_DQ25 30 168
<5> M_A_CLK1# CK1# DQ25 <15,36> DDR3_DRAMRST# RESET# VSS42
73 67 M_A_DQ26 172
<5> M_A_CKE0 CKE0 DQ26 VSS43
74 69 M_A_DQ27 173
<5> M_A_CKE1 CKE1 DQ27 VSS44
115 56 M_A_DQ28 +SMDDR_VREF_DQ0 1 178
<5> M_A_CAS# CAS# DQ28 VREF_DQ VSS45
110 58 M_A_DQ29 +SMDDR_VREF R129 M1@0_6 +SMDDR_VREF_DIMM 126 179
<5> M_A_RAS# RAS# DQ29 VREF_CA VSS46
113 68 M_A_DQ30 184
<5> M_A_WE# WE# DQ30 VSS47
R215 10K_4 DIMM0_SA0 197 70 M_A_DQ31 R131 *M3@0_6 185
SA0 DQ31 <7,36> VREF_DQ_DIMM0 VSS48
R216 10K_4 DIMM0_SA1 201 129 M_A_DQ32 2 189
CLK_SCLK SA1 DQ32 M_A_DQ33 VSS1 VSS49
202 SCL DQ33 131 <36> +SMDDR_VREF_DQ0 3 VSS2 VSS50 190
<3,15,28> CLK_SCLK CLK_SDATA 200 141 M_A_DQ34 8 195
(204P)
<3,15,28> CLK_SDATA SDA DQ34 M_A_DQ35 VSS3 VSS51
C DQ35 143 9 VSS4 VSS52 196 C
116 130 M_A_DQ36 13
<5> M_A_ODT0 ODT0 DQ36 VSS5
120 132 M_A_DQ37 14
<5> M_A_ODT1 ODT1 DQ37 VSS6
140 M_A_DQ38 19
<5> M_A_DM[7:0] DQ38 VSS7
M_A_DM0 11 142 M_A_DQ39 20
M_A_DM1 DM0 DQ39 M_A_DQ40 VSS8
28 DM1 DQ40 147 25 VSS9
M_A_DM2 46 149 M_A_DQ41 26 203 +0.75V_DDR_VTT
M_A_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ42 31
VSS10
VSS11
VTT1
VTT2 204
M_A_DM4 136 159 M_A_DQ43 +1.5V_SUS 32
M_A_DM5 DM4 DQ43 M_A_DQ44 VSS12
153 DM5 DQ44 146 37 VSS13 GND 205
M_A_DM6 170 148 M_A_DQ45 38 206
M_A_DM7 DM6 DQ45 M_A_DQ46 VSS14 GND
187 DM7 DQ46 158 43 VSS15
160 M_A_DQ47 R120
<5> M_A_DQS[7:0] DQ47
M_A_DQS0 12 163 M_A_DQ48 *10K_4
M_A_DQS1 DQS0 DQ48 M_A_DQ49
29 DQS1 DQ49 165 DDR3-DIMM0_H=5.2_Standard
M_A_DQS2 47 175 M_A_DQ50
M_A_DQS3 DQS2 DQ50 M_A_DQ51 R122 *short_6 +SMDDR_VREF_DIMM
64 DQS3 DQ51 177 +SMDDR_VREF
M_A_DQS4 137 164 M_A_DQ52
154 DQS5 DQ53 166
M_A_DQS6 171 174 M_A_DQ54 R121 C269
<5> M_A_DQS#[7:0] 188 DQS7 DQ55 176 *10K_4 470p/X7R_4
M_A_DQS#0 10 181 M_A_DQ56
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183
M_A_DQS#2 45 191 M_A_DQ58
62 DQS#3 DQ59 193
M_A_DQS#4 135 180 M_A_DQ60
152 DQS#5 DQ61 182
B M_A_DQS#6 169 192 M_A_DQ62 B
186 DQS#7 DQ63 194
DDR3-DIMM0_H=5.2_Standard
Place these Caps near So-Dimm0.
+1.5V_SUS
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0
C371 C365 C386 C342 C337
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
C331 + C329 C391 C392 C266 C268

330u/2V_7343
10u/6.3V_6 .1u/16V_4 .1u/16V_4
C349 C332 C351 C375 C341 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4
A A
+3V +0.75V_DDR_VTT
C424 C415 C426 C425 C423 C421 C419

C409
2.2u/6.3V_6
C410
.1u/16V_4
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6
PROJECT : ZR7B
1A
DDRIII SO-DIMM-0
5 4 3 2 1
5 4 3 2 1
+1.5V_SUS
JDIM2A M_B_DQ[63:0] <5> JDIM2B
<5> M_B_A[15:0]
M_B_A0 98 5 M_B_DQ0 75 44
M_B_A1 A0 DQ0 M_B_DQ1 VDD1 VSS16
97 A1 DQ1 7 76 VDD2 VSS17 48
M_B_A2 96 15 M_B_DQ2 81 49
95 A3 DQ3 17 82 VDD4 VSS19 54
M_B_A4 92 4 M_B_DQ4 87 55
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
86 A7 DQ7 18 94 VDD8 VSS23 65
M_B_A8 89 21 M_B_DQ8 99 66
D
M_B_A9 85
A8 DQ8
23 M_B_DQ9
2.48A 100
VDD9 VSS24
71
D

107 A10/AP DQ10 33 105 VDD11 VSS26 72
M_B_A11 M_B_DQ11

84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ12 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ13 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ14 117 134
78 A15 DQ15 36 118 VDD16 VSS31 138
M_B_DQ16

DQ16 39 123 VDD17 VSS32 139
109 41 M_B_DQ17 124 144
<5> M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ18 145
<5> M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ19 199 150
<5> M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ20 151
<5> M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ21 77 155
<5> M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ22 122 156
<5> M_B_CLK0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ23 125 161
<5> M_B_CLK0# CK0# DQ23 NCTEST VSS39
102 57 M_B_DQ24 162
<5> M_B_CLK1 CK1 DQ24 VSS40
104 59 M_B_DQ25 198 167
<5> M_B_CLK1# CK1# DQ25 <4> PM_EXTTS#1 EVENT# VSS41
73 67 M_B_DQ26 30 168
<5> M_B_CKE0 CKE0 DQ26 <14,36> DDR3_DRAMRST# RESET# VSS42
74 69 M_B_DQ27 172
<5> M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ28 173
<5> M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ29 +SMDDR_VREF_DQ1 1 178
<5> M_B_RAS# RAS# DQ29 <36> +SMDDR_VREF_DQ1 VREF_DQ VSS45
113 68 M_B_DQ30 R116 M1@0_6 126 179
<5> M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R204 10K_4 DIMM1_SA0 197 70 M_B_DQ31 R127 *M3@0_6 184
SA0 DQ31 <7,36> VREF_DQ_DIMM1 VSS47
R214 10K_4 DIMM1_SA1 201 129 M_B_DQ32 185
+3V SA1 DQ32 +SMDDR_VREF_DIMM VSS48
202 131 M_B_DQ33 2 189
<3,14,28> CLK_SCLK SCL DQ33 M_B_DQ34 VSS1 VSS49
200 SDA DQ34 141 3 VSS2 VSS50 190
<3,14,28> CLK_SDATA 143 M_B_DQ35 8 195
(204P)
C DQ35 VSS3 VSS51 C
116 130 M_B_DQ36 9 196
<5> M_B_ODT0 ODT0 DQ36 VSS4 VSS52
120 132 M_B_DQ37 13
<5> M_B_ODT1 ODT1 DQ37 VSS5
140 M_B_DQ38 14
<5> M_B_DM[7:0] DQ38 VSS6
M_B_DM0 11 142 M_B_DQ39 19
M_B_DM1 DM0 DQ39 M_B_DQ40 VSS7
28 DM1 DQ40 147 20 VSS8
M_B_DM2 46 149 M_B_DQ41 25
M_B_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_B_DQ42 26
VSS9
VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM4 136 159 M_B_DQ43 31 204
M_B_DM5 DM4 DQ43 M_B_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
M_B_DM6 170 148 M_B_DQ45 37 205
M_B_DM7 DM6 DQ45 M_B_DQ46 VSS13 GND
187 DM7 DQ46 158 38 VSS14 GND 206
160 M_B_DQ47 43
<5> M_B_DQS[7:0] DQ47 VSS15
M_B_DQS0 12 163 M_B_DQ48
M_B_DQS1 DQS0 DQ48 M_B_DQ49
29 DQS1 DQ49 165
M_B_DQS2 47 175 M_B_DQ50 DDR3-DIMM1_H=5.2_Reverse
64 DQS3 DQ51 177
M_B_DQS4 137 164 M_B_DQ52
154 DQS5 DQ53 166
M_B_DQS6 171 174 M_B_DQ54
<5> M_B_DQS#[7:0] 188 DQS7 DQ55 176
M_B_DQS#0 10 181 M_B_DQ56
M_B_DQS#1 DQS#0 DQ56 M_B_DQ57
27 DQS#1 DQ57 183
M_B_DQS#2 45 191 M_B_DQ58
62 DQS#3 DQ59 193
M_B_DQS#4 135 180 M_B_DQ60
152 DQS#5 DQ61 182
B M_B_DQS#6 169 192 M_B_DQ62 B
186 DQS#7 DQ63 194
DDR3-DIMM1_H=5.2_Reverse
+1.5V_SUS Place these Caps near So-Dimm1.

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1
C376 C328 C364 C377 C370
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
C387 + C348 C394 C393 C267 C265

330u/2V_7343
10u/6.3V_6 .1u/16V_4 .1u/16V_4
C343 C389 C353 C338 C385 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4
+3V +0.75V_DDR_VTT
A C416 C429 C427 C428 C418 C422 C420 A

C404 C417 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
2.2u/6.3V_6 .1u/16V_4 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6

PROJECT : ZR7B
1A
DDRIII SO-DIMM-1
5 4 3 2 1
5 4 3 2 1
U24A
AA38 Y33 CPEG_RXP15 C176 SW@0.1u/10V_4_X7R

<4> PEG_TXP15 PCIE_RX0P PCIE_TX0P PEG_RXP15 <4>
Y37 Y32 CPEG_RXN15 C166 SW@0.1u/10V_4_X7R
<4> PEG_TXN15 PCIE_RX0N PCIE_TX0N PEG_RXN15 <4>
D D
Y35 W33 CPEG_RXP14 C163 SW@0.1u/10V_4_X7R

W36 W32 CPEG_RXN14 C148 SW@0.1u/10V_4_X7R
W38 U33 CPEG_RXP13 C153 SW@0.1u/10V_4_X7R

V37 U32 CPEG_RXN13 C137 SW@0.1u/10V_4_X7R
V35 U30 CPEG_RXP12 C132 SW@0.1u/10V_4_X7R

U36 U29 CPEG_RXN12 C136 SW@0.1u/10V_4_X7R
U38 T33 CPEG_RXP11 C121 SW@0.1u/10V_4_X7R

T37 T32 CPEG_RXN11 C113 SW@0.1u/10V_4_X7R
PCI EXPRESS INTERFACE

T35 T30 CPEG_RXP10 C123 SW@0.1u/10V_4_X7R
R36 T29 CPEG_RXN10 C131 SW@0.1u/10V_4_X7R
R38 P33 CPEG_RXP9 C107 SW@0.1u/10V_4_X7R

P37 P32 CPEG_RXN9 C99 SW@0.1u/10V_4_X7R
C C
P35 P30 CPEG_RXP8 C85 SW@0.1u/10V_4_X7R

N36 P29 CPEG_RXN8 C96 SW@0.1u/10V_4_X7R
N38 N33 CPEG_RXP7 C83 SW@0.1u/10V_4_X7R

M37 N32 CPEG_RXN7 C73 SW@0.1u/10V_4_X7R
M35 N30 CPEG_RXP6 C62 SW@0.1u/10V_4_X7R

L36 N29 CPEG_RXN6 C67 SW@0.1u/10V_4_X7R
L38 L33 CPEG_RXP5 C61 SW@0.1u/10V_4_X7R

K37 L32 CPEG_RXN5 C60 SW@0.1u/10V_4_X7R
K35 L30 CPEG_RXP4 C58 SW@0.1u/10V_4_X7R

J36 L29 CPEG_RXN4 C56 SW@0.1u/10V_4_X7R
J38 K33 CPEG_RXP3 C48 SW@0.1u/10V_4_X7R

H37 K32 CPEG_RXN3 C44 SW@0.1u/10V_4_X7R
B B
H35 J33 CPEG_RXP2 C43 SW@0.1u/10V_4_X7R

G36 J32 CPEG_RXN2 C41 SW@0.1u/10V_4_X7R
G38 K30 CPEG_RXP1 C39 SW@0.1u/10V_4_X7R

F37 K29 CPEG_RXN1 C37 SW@0.1u/10V_4_X7R
F35 H33 CPEG_RXP0 C36 SW@0.1u/10V_4_X7R

E37 H32 CPEG_RXN0 C32 SW@0.1u/10V_4_X7R
CLOCK
<10> CLK_PCIE_VGA AB35 PCIE_REFCLKP
<10> CLK_PCIE_VGA# AA36 PCIE_REFCLKN
For Broadway, Madison and Park CALIBRATION

AJ21 Y30 R33 SW@1.27K/F_4
the PWRGOOD ball must be conneccted to ground NC#1 PCIE_CALRP
AK21 NC#2
R44 SW@10K_4 R30 SW@2K/F_4 +1V
A
AH16 PWRGOOD PCIE_CALRN Y29 +1.0V A
GPU_RST#
<11> GPU_RST# AA30 PERSTB For M97, Broadway, Madison and Park PCIE_VDDC is 1.0V
SW@Madison/Broadway_M2
PROJECT : ZR7B
1A
Madison/Broadway-PCIE I/F
5 4 3 2 1
5 4 3 2 1
GPU Power-on sequence U24B U24G
1 => +3V_D
AU24 LVDS CONTROL AK27
HDMICLK+ <25> EV_LVDS_BRIGHT <24>
2 => +VGPU_CORE TXCAP_DPA3P
TXCAM_DPA3N
AV23 HDMICLK- <25>
VARY_BL
DIGON
AJ27 EV_LVDS_VDDEN <24>
3 => +VGPU_IO MUTI GFX TX0P_DPA2P

AT25
AR24
HDMITX0P <25>
R61 *SW@10K_4
TX0M_DPA2N HDMITX0N <25>
4 => +1V DPA
TX1P_DPA1P
AU26 HDMITX1P <25> TXCLK_UP_DPF3P
AK35
R66 *SW@10K_4
AV25 AL36
5 => +1.5V_GPU TX1M_DPA1N HDMITX1N <25> TXCLK_UN_DPF3N
AR8 AT27 HDMITX2P <25> AJ38
D
6 => +1.8V_GPU AU8
DVPCNTL_MVP_0
DVPCNTL_MVP_1
TX2P_DPA0P
TX2M_DPA0N
AR26 HDMITX2N <25>
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
AK37 D
AP8
7 => dGPU_PWROK NC on Park AW8
DVPCNTL_0
DVPCNTL_1 TXCBP_DPB3P
AR30
TXOUT_U1P_DPF1P
AH35
AR3 AT29 AJ36
DVPCNTL_2 TXCBM_DPB3N TXOUT_U1N_DPF1N
AR1
DVPCLK
<23> RAM_STRAP0 AU1 AV31 AG38
DVPDATA_0 TX3P_DPB2P TXOUT_U2P_DPF0P
<23> RAM_STRAP1 AU3 AU30 AH37
DVPDATA_1 DPB TX3M_DPB2N TXOUT_U2N_DPF0N
<23> RAM_STRAP2 AW3
DVPDATA_2
AP6 AR32 AF35
T34 DVPDATA_3 TX4P_DPB1P TXOUT_U3P
AW5 AT31 AG36
DVPDATA_4 TX4M_DPB1N TXOUT_U3N
AU5
DVPDATA_5
AR6 AT33
DVPDATA_6 TX5P_DPB0P LVTMDP
1.8V GPIO AW6
DVPDATA_7 TX5M_DPB0N
AU32
AU6
DVPDATA_8
AT7 AU14 AP34 EV_TXLCLKOUT+ <24>
DVPDATA_9 TXCCP_DPC3P TXCLK_LP_DPE3P
AV7 AV13 AR34 EV_TXLCLKOUT- <24>
DVPDATA_10 TXCCM_DPC3N TXCLK_LN_DPE3N
AN7
DVPDATA_11
AV9 AT15 AW37 EV_TXLOUT0+ <24>
DVPDATA_12 TX0P_DPC2P TXOUT_L0P_DPE2P
AT9 AR14 AU35 EV_TXLOUT0- <24>
DVPDATA_13 TX0M_DPC2N TXOUT_L0N_DPE2N
AR10
DVPDATA_14 DPC
AW10 AU16 AR37 EV_TXLOUT1+ <24>
AU10 AV15 AU39 EV_TXLOUT1- <24>
AP10
DVPDATA_17
AV11 AT17 AP35 EV_TXLOUT2+ <24>
AT11 AR16 AR35 EV_TXLOUT2- <24>
AR12
NC on Park AW12
DVPDATA_20
DVPDATA_21 TXCDP_DPD3P
AU20
TXOUT_L3P
AN36
AU12 AT19 AP37
+3V_D DVPDATA_22 TXCDM_DPD3N TXOUT_L3N
AP12
DVPDATA_23
AT21
TX3P_DPD2P
AR20
TX3M_DPD2N
DPD
DP Channel D is NC on PARK
AU22
R58 R67 TX4P_DPD1P SW@Madison/Broadway_M2
AV21
TX4M_DPD1N
SW@10K/F_4
SW@10K/F_4 I2C AT23
TX5P_DPD0P
AR22
TX5M_DPD0N
AK26
SCL
C AJ26 C
SDA
AD39 EV_CRT_RED <24>
GENERAL PURPOSE I/O R
AD37
RB
<23> GPU_GPIO0 AH20
GPIO_0
<23> GPU_GPIO1 AH18 AE36 EV_CRT_GRN <24>
GPIO_1 G
<23> GPU_GPIO2 AN16 AD35
GPIO_2 GB
<23> GPIO3_SMBDAT AH23
GPIO_3_SMBDATA
<23> GPIO4_SMBCLK AJ23 AF37 EV_CRT_BLU <24>
GPIO_4_SMBCLK B
AH17 AE38
T11 GPIO_5_AC_BATT DAC1 BB
<45> IO_VID0 AJ17
GPIO_6 R383 R379 R375
<24> EV_LVDS_BLON AK17 AC36 EV_HSYNC <23,24>
GPIO_7_BLON HSYNC
<23> SOUT_GPIO8 AJ13 AC38 EV_VSYNC <23,24> SW@150/F_4 SW@150/F_4
GPIO_8_ROMSO VSYNC SW@150/F_4
<23> SIN_GPIO9 AH15
GPIO_9_ROMSI
<23> SCLK_GPIO10 AJ16
+3V_D GPIO_10_ROMSCK R36 SW@499/F_4
<23> GPU_GPIO11 AK16 AB34
GPIO_11 RSET
<23> GPU_GPIO12 AL16
GPIO_12 AVDD
<23> GPU_GPIO13 AM16 AD34
GPIO_13 AVDD +1.8V_GPU
AM14 AE34
R68 T23 GPIO_14_HPD2 AVSSQ
3.3V GPIO <44> VCORE1.2ID0 AM13
GPIO_15_PWRCNTL_0 (1.8V@70mA AVDD)
SW@10K_4 AK14 AC33 VDD1DI
GPIO_16_SSIN VDD1DI AVDD L42 SW@BLM15AG121SS1/0.5A/120ohm_4
<23> ALT#_GPIO17 AG30 AC34
GPIO_17_THERMAL_INT VSS1DI
AN14
T27 GPIO_18_HPD3
AM17
GPIO_19_CTF C593 C592 C591
<44> VCORE1.2ID1 AL13 AC30
+3V_D GPIO_20_PWRCNTL_1 R2 SW@0.1u/10V_4_X7R SW@10u/6.3V_6
AJ14 AC31
R74 T14 GPIO_21_BB_EN R2B SW@1u/6.3V_4
<23> SCS#_GPIO22 AK13
*SW@10K/F_4 GPIO_22_ROMCSB
AN13 AD30
R50 SW@10K/F_4 GPIO24_TRSTB AM23 GPIO_23_CLKREQB G2
JTAG_TRSTB G2B
AD31 (1.8V@100mA VDD1DI)
R106 +3V_D R382 *SW@10K/F_4 T24 AN23
*SW@10K/F_4 27M_CLK JTAG_TDI VDD1DI L5 SW@BLM15AG121SS1/0.5A/120ohm_4
<3> 27M_CLK AK23 AF30
R98 SW@10K/F_4 JTAG_TCK B2
AL24 AF31
T28 JTAG_TMS B2B
AM24
JTAG_TDO DAC2 will be NC on future ASIC
+3V_D R386 SW@10K/F_4 AJ19 C195 C196 C198
<10> PEG_CLKREQ# GENERICA
AK19 AC32 SW@0.1u/10V_4_X7R SW@10u/6.3V_6
GENERICB C SW@1u/6.3V_4
AJ20 AD32
R105 10/5 modify GENERICC Y
AK20 AF32
GENERICD COMP
*SW@10K/F_4 AJ24
B GENERICE_HPD4 DAC2 B
AH26
GENERICF T8
GenericF/G is NC on PARK AH24
GENERICG H2SYNC
AD29
AC29
V2SYNC V2SYNC <23>
<25> HDMI_HP_EV AK24

+1.8V_GPU HPD1 VDD1DI
AG31
VDD2DI
AG32
VSS2DI +3V_D
R88 AG33 (3.3V@130mA A2VDD)

A2VDD
SW@499/F_4
AD33 A2VDDQ C174
VREFG A2VDDQ SW@0.1u/10V_4_X7R
AH13
VREFG
AF33
A2VSSQ
R89 C232 +1.8V_GPU
AA29 R37 SW@715/F_4 (1.8V@2mA A2VDDQ)
SW@249/F_4 SW@0.1u/10V_4_X7R R2SET
+1.8V(75mA) A2VDDQ L41 SW@BLM15AG121SS1/0.5A/120ohm_4
+1.8V_GPU L15 SW@BLM15AG121SS1/0.5A/120ohm_4 DPLL_PVDD DDC/AUX AM26 MXM_DDCCK <25>

PLL/CLOCK DDC1CLK C588 C587
AN26
C249 C211 C207 DPLL_PVDD AM32
DPLL_PVDD
DDC1DATA MXM_DDCDAT <25>
HDMI SW@0.1u/10V_4_X7R
AN32 AM27 SW@1u/6.3V_4
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R R410 *SW@0_4 DPLL_PVSS AUX1P T33
<3> CLK_27M_SS AL27
SW@1u/6.3V_4 AUX1N T31
DPLL_VDDC AN31 AM19
C611 SW@27p/50V_4 DPLL_VDDC DDC2CLK T26
AL19
DDC2DATA T17
+1.0V(125mA)
2
XTALI_27M AV33 AN20

L19 SW@BLM15AG121SS1/0.5A/120ohm_4 DPLL_VDDC Y3 R409 XTALO_27M XTALIN AUX2P T21
+1V AU34 AM20
SW@1M_4 XTALOUT AUX2N T18
C242 C228 C223 SW@27MHZ AL30
1
DDCCLK_AUX3P T15
AM30
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R C610 SW@27p/50V_4 DDCDATA_AUX3N T35
SW@1u/6.3V_4 AL29
DDCCLK_AUX4P T25
A
<23> GPU_D+ AF29
AG29
DPLUS THERMAL DDCDATA_AUX4N
AM29
T30
DDCxx_AUX4x is NC on PARK A
<23> GPU_D- DMINUS
+1.8V(5mA) AN21
DDCCLK_AUX5P
DDCDATA_AUX5N
AM21
EV_LVDS_DDCCLK
EV_LVDS_DDCDAT
<24>
<24>
LVDS
+1.8V_GPU L6 SW@BLM15AG121SS1/0.5A/120ohm_4 TS_VDD T19 AK32
TS_VDD TS_FDO
AJ32 AJ30
C219 C218 AJ33
TSVDD
TSVSS
DDC6CLK
DDC6DATA
AJ31
EV_CRTDCLK
EV_CRTDDAT
<24>
<24>
CRT
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R AK30
NC_DDCCLK_AUX7P T29
NC_DDCDATA_AUX7N
AK29
T20
DDCxx_AUX7x is NC on M9x and PARK
PROJECT : ZR7B
1A
Madison/Broadway-HOST I/F
5 4 3 2 1
5 4 3 2 1
VMA_DQ[63..0] VMB_DQ[63..0]
<19> VMA_DQ[63..0] <20> VMB_DQ[63..0]
VMA_DM[7..0] VMB_DM[7..0]
<19> VMA_DM[7..0] <20> VMB_DM[7..0]
U24C U24D
VMA_RDQS[7..0] DDR2 DDR2 VMB_RDQS[7..0] DDR2 DDR2
<19> VMA_RDQS[7..0] GDDR3/GDDR5 GDDR5/GDDR3 <20> VMB_RDQS[7..0] GDDR3/GDDR5 GDDR5/GDDR3
VMA_WDQS[7..0] DDR3 DDR3 VMB_WDQS[7..0] DDR3 DDR3
<19> VMA_WDQS[7..0] <20> VMB_WDQS[7..0]
VMA_DQ0 C37 G24 VMA_MA0 VMB_DQ0 C5 P8 VMB_MA0
VMA_DQ1 DQA0_0/DQA_0 MAA0_0/MAA_0 VMA_MA1 VMB_DQ1 DQB0_0/DQB_0 MAB0_0/MAB_0 VMB_MA1
C35 J23 C3 T9
MEMORY INTERFACE A
D
VMA_DQ2 DQA0_1/DQA_1 MAA0_1/MAA_1 VMA_MA2 VMB_MA[13..0] VMB_DQ2 DQB0_1/DQB_1 MAB0_1/MAB_1 VMB_MA2 D
A35 H24 E3 P9
MEMORY INTERFACE B
VMA_MA[13..0] DQA0_2/DQA_2 MAA0_2/MAA_2 <20> VMB_MA[13..0] DQB0_2/DQB_2 MAB0_2/MAB_2
VMA_DQ3 E34 J24 VMA_MA3 VMB_DQ3 E1 N7 VMB_MA3
<19> VMA_MA[13..0] DQA0_3/DQA_3 MAA0_3/MAA_3 DQB0_3/DQB_3 MAB0_3/MAB_3
VMA_DQ4 G32 H26 VMA_MA4 VMB_DQ4 F1 N8 VMB_MA4
VMA_DQ5 DQA0_4/DQA_4 MAA0_4/MAA_4 VMA_MA5 VMB_BA0 VMB_DQ5 DQB0_4/DQB_4 MAB0_4/MAB_4 VMB_MA5
D33 J26 <20> VMB_BA0 F3 N9
VMA_BA0 VMA_DQ6 DQA0_5/DQA_5 MAA0_5/MAA_5 VMA_MA6 VMB_BA1 VMB_DQ6 DQB0_5/DQB_5 MAB0_5/MAB_5 VMB_MA6
<19> VMA_BA0 F32 H21 <20> VMB_BA1 F5 U9
VMA_BA1 VMA_DQ7 DQA0_6/DQA_6 MAA0_6/MAA_6 VMA_MA7 VMB_BA2 VMB_DQ7 DQB0_6/DQB_6 MAB0_6/MAB_6 VMB_MA7
<19> VMA_BA1 E32 G21 <20> VMB_BA2 G4 U8
VMA_BA2 VMA_DQ8 DQA0_7/DQA_7 MAA0_7/MAA_7 VMA_MA8 VMB_DQ8 DQB0_7/DQB_7 MAB0_7/MAB_7 VMB_MA8
<19> VMA_BA2 D31 H19 H5 Y9
F30 H20 H6 W9
C30 L13 J4 AC8
A30 G16 K6 AC9
F28 J16 K5 AA7
VMA_DQ13 DQA0_12/DQA_12 MAA1_4/MAA_12 VMA_BA2 VMB_DQ13 DQB0_12/DQB_12 MAB1_4/MAB_12 VMB_BA2
C28 H16 L4 AA8
VMA_DQ14 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 VMA_BA0 VMB_DQ14 DQB0_13/DQB_13 MAB1_5/BA2 VMB_BA0
A28 J17 M6 Y8
VMA_DQ15 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 VMA_BA1 VMB_DQ15 DQB0_14/DQB_14 MAB1_6/BA0 VMB_BA1
E28 H17 M1 AA9
VMA_DQ16 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 VMB_DQ16 DQB0_15/DQB_15 MAB1_7/BA1
D27 M3
VMA_DQ17 DQA0_16/DQA_16 VMA_DM0 VMB_DQ17 DQB0_16/DQB_16 VMB_DM0
F26 A32 M5 H3
VMA_DQ18 DQA0_17/DQA_17 WCKA0_0/DQMA_0 VMA_DM1 VMB_DQ18 DQB0_17/DQB_17 WCKB0_0/DQMB_0 VMB_DM1
C26 C32 N4 H1
VMA_DQ19 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 VMA_DM2 VMB_DQ19 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 VMB_DM2
A26 D23 P6 T3
F24 E22 P5 T5
C24 C14 R4 AE4
A24 A14 T6 AF5
E24 E10 T1 AK6
C22 D9 U4 AK5
VMA_DQ25 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 VMB_DQ25 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
A22 V6
VMA_DQ26 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 VMA_RDQS0 VMB_DQ26 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 VMB_RDQS0
F22 C34 V1 F6
VMA_DQ27 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 VMA_RDQS1 VMB_DQ27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 VMB_RDQS1
D21 D29 V3 K3
A20 D25 Y6 P3
F20 E20 Y1 V5
D19 E16 Y3 AB5
E18 E12 Y5 AH1
C18 J10 AA4 AJ9
A18 D7 AB6 AM5
VMA_DQ34 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 VMB_DQ34 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7
F18 AB1
VMA_DQ35 DQA1_2/DQA_34 VMA_WDQS0 VMB_DQ35 DQB1_2/DQB_34 VMB_WDQS0
D17 A34 AB3 G7
VMA_DQ36 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 VMA_WDQS1 VMB_DQ36 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 VMB_WDQS1
A16 E30 AD6 K1
F16 E26 AD1 P1
D15 C20 AD3 W4
C E14 C16 AD5 AC4 C
F14 C12 AF1 AH3
D13 J11 AF3 AJ8
F12 F8 AF6 AM3
VMA_DQ43 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 VMB_DQ43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
A12 AG4
VMA_DQ44 DQA1_11/DQA_43 VMA_ODT0 VMB_DQ44 DQB1_11/DQB_43 VMB_ODT0
D11 J21 VMA_ODT0 <19> AH5 T7 VMB_ODT0 <20>
VMA_DQ45 DQA1_12/DQA_44 ADBIA0/ODTA0 VMA_ODT1 VMB_DQ45 DQB1_12/DQB_44 ADBIB0/ODTB0 VMB_ODT1
F10 G19 VMA_ODT1 <19> AH6 W7 VMB_ODT1 <20>
VMA_DQ46 DQA1_13/DQA_45 ADBIA1/ODTA1 VMB_DQ46 DQB1_13/DQB_45 ADBIB1/ODTB1
A10 AJ4
VMA_DQ47 DQA1_14/DQA_46 VMA_CLK0 VMB_DQ47 DQB1_14/DQB_46 VMB_CLK0
C10 H27 VMA_CLK0 <19> AK3 L9 VMB_CLK0 <20>
VMA_DQ48 DQA1_15/DQA_47 CLKA0 VMA_CLK0# VMB_DQ48 DQB1_15/DQB_47 CLKB0 VMB_CLK0#
G13 G27 VMA_CLK0# <19> AF8 L8 VMB_CLK0# <20>
VMA_DQ49 DQA1_16/DQA_48 CLKA0B VMB_DQ49 DQB1_16/DQB_48 CLKB0B
H13 AF9
VMA_DQ50 DQA1_17/DQA_49 VMA_CLK1 VMB_DQ50 DQB1_17/DQB_49 VMB_CLK1
J13 J14 VMA_CLK1 <19> AG8 AD8 VMB_CLK1 <20>
VMA_DQ51 DQA1_18/DQA_50 CLKA1 VMA_CLK1# VMB_DQ51 DQB1_18/DQB_50 CLKB1 VMB_CLK1#
H11 H14 VMA_CLK1# <19> AG7 AD7 VMB_CLK1# <20>
VMA_DQ52 DQA1_19/DQA_51 CLKA1B VMB_DQ52 DQB1_19/DQB_51 CLKB1B
G10 AK9
VMA_DQ53 DQA1_20/DQA_52 VMA_RAS0# VMB_DQ53 DQB1_20/DQB_52 VMB_RAS0#
G8 K23 VMA_RAS0# <19> AL7 T10 VMB_RAS0# <20>
VMA_DQ54 DQA1_21/DQA_53 RASA0B VMA_RAS1# VMB_DQ54 DQB1_21/DQB_53 RASB0B VMB_RAS1#
K9 K19 VMA_RAS1# <19> AM8 Y10 VMB_RAS1# <20>
VMA_DQ55 DQA1_22/DQA_54 RASA1B VMB_DQ55 DQB1_22/DQB_54 RASB1B
K10 AM7
VMA_DQ56 DQA1_23/DQA_55 VMA_CAS0# VMB_DQ56 DQB1_23/DQB_55 VMB_CAS0#
G9 K20 VMA_CAS0# <19> AK1 W10 VMB_CAS0# <20>
+1.5V_GPU VMA_DQ57 DQA1_24/DQA_56 CASA0B VMA_CAS1# VMB_DQ57 DQB1_24/DQB_56 CASB0B VMB_CAS1#
A8 K17 VMA_CAS1# <19> AL4 AA10 VMB_CAS1# <20>
VMA_DQ58 DQA1_25/DQA_57 CASA1B +1.5V_GPU VMB_DQ58 DQB1_25/DQB_57 CASB1B
C8 AM6
VMA_DQ59 DQA1_26/DQA_58 VMA_CS0# VMB_DQ59 DQB1_26/DQB_58 VMB_CS0#
E8 K24 VMA_CS0# <19> AM1 P10 VMB_CS0# <20>
VMA_DQ60 DQA1_27/DQA_59 CSA0B_0 VMB_DQ60 DQB1_27/DQB_59 CSB0B_0
A6 K27 AN4 L10
VMA_DQ61 DQA1_28/DQA_60 CSA0B_1 VMB_DQ61 DQB1_28/DQB_60 CSB0B_1
C6 AP3
R353 VMA_DQ62 DQA1_29/DQA_61 VMA_CS1# VMB_DQ62 DQB1_29/DQB_61 VMB_CS1#
E6 M13 VMA_CS1# <19> AP1 AD10 VMB_CS1# <20>
SW@40.2/F_4 VMA_DQ63 DQA1_30/DQA_62 CSA1B_0 R34 VMB_DQ63 DQB1_30/DQB_62 CSB1B_0
A5 K16 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 SW@40.2/F_4 DQB1_31/DQB_63 CSB1B_1
MVREFDA L18 K21 VMA_CKE0 U10 VMB_CKE0
MVREFDA CKEA0 VMA_CKE0 <19> CKEB0 VMB_CKE0 <20>
MVREFSA L20 J20 VMA_CKE1 MVREFDB Y12 AA11 VMB_CKE1
MVREFSA CKEA1 VMA_CKE1 <19> MVREFDB CKEB1 VMB_CKE1 <20>
MVREFSB AA12
R23 MP@243/F_4 VMA_WE0# MVREFSB VMB_WE0#
+1.5V_GPU L27 K26 VMA_WE0# <19> N10 VMB_WE0# <20>
R354 C548 R27 MP@243/F_4 MEM_CALRN0 WEA0B VMA_WE1# WEB0B VMB_WE1#
N12 L15 VMA_WE1# <19> AB11 VMB_WE1# <20>
SW@0.1u/10V_4_X7R R47 MP@243/F_4 AG12 MEM_CALRN1 WEA1B R31 C128 R377 SW@10K/F_4 WEB1B
MEM_CALRN2 +3V_D
SW@100/F_4 SW@0.1u/10V_4_X7R
R25 MP@243/F_4 VMA_MA13 SW@100/F_4 R39 *SW@1K_4 TESTEN VMB_MA13 R361 *SW@4.7K_4
GDDR5
M12 H23 AD28 T8
GDDR5
MEM_CALRP1 MAA0_8 TESTEN MAB0_8 +1.5V_GPU
R22 MP@243/F_4 M27 J19 W8
R65 MP@243/F_4 AH12 MEM_CALRP0 MAA1_8 MAB1_8
AK10
MEM_CALRP2 CLKTESTA R419 SW@51_4
AL10 AH11 MEM_RST# <19,20>
+1.5V_GPU CLKTESTB DRAM_RST
B B
+1.5V_GPU
TP1 AL31 R80 R86
RSVD *0_4 *0_4 C565 R92
Madison Park
R21 SW@Madison/Broadway_M2 SW@68p/50V_4 SW@10K_4
SW@40.2/F_4 SW@Madison/Broadway_M2 R40
R23, R47, R27, R25 SW@40.2/F_4
R22, R65
R20 C63
SW@0.1u/10V_4_X7R R35 C164
SW@100/F_4 SW@0.1u/10V_4_X7R
SW@100/F_4
A A

PROJECT : ZR7B
1A
Madison/Broadway-MEM I/F
5 4 3 2 1
5 4 3 2 1
VMA_DQ[63..0]
<18> VMA_DQ[63..0]
<18> VMA_DM[7..0]
VMA_DM[7..0] CHANNEL A: 512MB DDR3 (64M*16*4pcs) Park, M92M Use Channel B Memory Interface Only
VMA_RDQS[7..0] QSA[7..0]
<18> VMA_RDQS[7..0]
VMA_WDQS[7..0] QSA#[7..0]
<18> VMA_WDQS[7..0]
U20 U1 U21 U2
VREFC_VMA1 M8 E3 VMA_DQ10 VREFC_VMA2 M8 E3 VMA_DQ6 VREFC_VMA3 M8 E3 VMA_DQ54 VREFC_VMA4 M8 E3 VMA_DQ40

VREFD_VMA1 VREFCA DQL0 VMA_DQ11 VREFD_VMA2 VREFCA DQL0 VMA_DQ0 VREFD_VMA3 VREFCA DQL0 VMA_DQ53 VREFD_VMA4 VREFCA DQL0 VMA_DQ44
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 VMA_DQ9 VREFDQ DQL1 VMA_DQ7 VREFDQ DQL1 VMA_DQ55 VREFDQ DQL1 VMA_DQ45
F2 F2 F2 F2
VMA_MA0 DQL2 VMA_DQ12 VMA_MA0 DQL2 VMA_DQ1 VMA_MA0 DQL2 VMA_DQ50 VMA_MA0 DQL2 VMA_DQ42
N3 F8 N3 F8 N3 F8 N3 F8
<18>
<18>
<18>
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA1
VMA_MA2
VMA_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMA_DQ13
VMA_DQ15
VMA_DQ8 1
VMA_MA1
VMA_MA2
VMA_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMA_DQ4
VMA_DQ2
VMA_DQ5
0 VMA_MA1
VMA_MA2
VMA_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMA_DQ49
VMA_DQ48
VMA_DQ52 6
VMA_MA1
VMA_MA2
VMA_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMA_DQ46
VMA_DQ41
VMA_DQ47
5
<18> VMA_MA3 N2 G2 N2 G2 N2 G2 N2 G2
D
VMA_MA4 A3 DQL6 VMA_DQ14 VMA_MA4 A3 DQL6 VMA_DQ3 VMA_MA4 A3 DQL6 VMA_DQ51 VMA_MA4 A3 DQL6 VMA_DQ43 D
<18> VMA_MA4 P8 H7 P8 H7 P8 H7 P8 H7
VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7
<18> VMA_MA5 P2 P2 P2 P2
VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5
<18> VMA_MA6 R8 R8 R8 R8
VMA_MA7 A6 VMA_DQ20 VMA_MA7 A6 VMA_DQ25 VMA_MA7 A6 VMA_DQ63 VMA_MA7 A6 VMA_DQ32
<18> VMA_MA7 R2 D7 R2 D7 R2 D7 R2 D7
VMA_MA8 A7 DQU0 VMA_DQ19 VMA_MA8 A7 DQU0 VMA_DQ31 VMA_MA8 A7 DQU0 VMA_DQ56 VMA_MA8 A7 DQU0 VMA_DQ36
<18> VMA_MA8 T8 C3 T8 C3 T8 C3 T8 C3
VMA_MA9 A8 DQU1 VMA_DQ23 VMA_MA9 A8 DQU1 VMA_DQ27 VMA_MA9 A8 DQU1 VMA_DQ62 VMA_MA9 A8 DQU1 VMA_DQ33
R3 C8 R3 C8 R3 C8 R3 C8
<18>
<18>
<18>
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA10
VMA_MA11
VMA_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMA_DQ18
VMA_DQ22
VMA_DQ16 2
VMA_MA10
VMA_MA11
VMA_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMA_DQ28
VMA_DQ24
VMA_DQ30
3 VMA_MA10
VMA_MA11
VMA_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMA_DQ59
VMA_DQ60
VMA_DQ58 7
VMA_MA10
VMA_MA11
VMA_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMA_DQ39
VMA_DQ35
VMA_DQ37
4
<18> VMA_MA12 N7 A2 N7 A2 N7 A2 N7 A2
VMA_MA13 A12/BC DQU5 VMA_DQ21 VMA_MA13 A12/BC DQU5 VMA_DQ26 VMA_MA13 A12/BC DQU5 VMA_DQ61 VMA_MA13 A12/BC DQU5 VMA_DQ34
<18> VMA_MA13 T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 VMA_DQ17 A13 DQU6 VMA_DQ29 A13 DQU6 VMA_DQ57 A13 DQU6 VMA_DQ38
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU
VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2

<18> VMA_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA1 N8 D9
<18> VMA_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7
<18> VMA_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 VDD#K2 VDD#K2 VDD#K2
K8 K8 K8 K8
N1 N1 N1 N1
VMA_CLK0 VDD#N1 VMA_CLK0 VDD#N1 VMA_CLK1 VDD#N1 VMA_CLK1 VDD#N1
<18> VMA_CLK0 J7 N9 J7 N9 <18> VMA_CLK1 J7 N9 J7 N9
VMA_CLK0# CK VDD#N9 VMA_CLK0# CK VDD#N9 VMA_CLK1# CK VDD#N9 VMA_CLK1# CK VDD#N9
<18> VMA_CLK0# K7 R1 K7 R1 <18> VMA_CLK1# K7 R1 K7 R1
VMA_CKE0 CK VDD#R1 VMA_CKE0 CK VDD#R1 VMA_CKE1 CK VDD#R1 VMA_CKE1 CK VDD#R1
<18> VMA_CKE0 K9 R9 K9 R9 <18> VMA_CKE1 K9 R9 K9 R9
CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU
VMA_ODT0 K1 A1 VMA_ODT0 K1 A1 VMA_ODT1 K1 A1 VMA_ODT1 K1 A1

<18> VMA_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 <18> VMA_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMA_CS0# L2 A8 VMA_CS0# L2 A8 VMA_CS1# L2 A8 VMA_CS1# L2 A8
<18> VMA_CS0# CS VDDQ#A8 CS VDDQ#A8 <18> VMA_CS1# CS VDDQ#A8 CS VDDQ#A8
VMA_RAS0# J3 C1 VMA_RAS0# J3 C1 VMA_RAS1# J3 C1 VMA_RAS1# J3 C1
<18> VMA_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 <18> VMA_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMA_CAS0# K3 C9 VMA_CAS0# K3 C9 VMA_CAS1# K3 C9 VMA_CAS1# K3 C9
<18> VMA_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 <18> VMA_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMA_WE0# L3 D2 VMA_WE0# L3 D2 VMA_WE1# L3 D2 VMA_WE1# L3 D2
<18> VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 <18> VMA_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
VMA_RDQS1 VDDQ#F1 VMA_RDQS0 VDDQ#F1 VMA_RDQS6 VDDQ#F1 VMA_RDQS5 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
VMA_RDQS2 DQSL VDDQ#H2 VMA_RDQS3 DQSL VDDQ#H2 VMA_RDQS7 DQSL VDDQ#H2 VMA_RDQS4 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
VMA_DM1 E7 A9 VMA_DM0 E7 A9 VMA_DM6 E7 A9 VMA_DM5 E7 A9

VMA_DM2 DML VSS#A9 VMA_DM3 DML VSS#A9 VMA_DM7 DML VSS#A9 VMA_DM4 DML VSS#A9
C D3 B3 D3 B3 D3 B3 D3 B3 C
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMA_WDQS1 VSS#G8 VMA_WDQS0 VSS#G8 VMA_WDQS6 VSS#G8 VMA_WDQS5 VSS#G8
G3 J2 G3 J2 G3 J2 G3 J2
VMA_WDQS2 DQSL VSS#J2 VMA_WDQS3 DQSL VSS#J2 VMA_WDQS7 DQSL VSS#J2 VMA_WDQS4 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
VSS#M1 VSS#M1 VSS#M1 VSS#M1
M9 M9 M9 M9
P1 P1 P1 P1
MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1
T2 P9 T2 P9 T2 P9 T2 P9
<18,20> MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMA_ZQ1 VSS#T1 VMA_ZQ2 VSS#T1 VMA_ZQ3 VSS#T1 VMA_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R349 VSSQ#B9 R3 VSSQ#B9 R344 VSSQ#B9 R6 VSSQ#B9
D1 D1 D1 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
MP@240/F_4 D8 MP@240/F_4 D8 MP@240/F_4 D8 MP@240/F_4 D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
MP@VRAM _DDR3 MP@VRAM _DDR3 MP@VRAM _DDR3 MP@VRAM _DDR3
TOP Left BOT Left BOT Right TOP Right

Group-A0 VREF Group-A1 VREF
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R352 R336 R337 R8 R338 R348 R4 R339

MP@4.99K/F_4 MP@4.99K/F_4 MP@4.99K/F_4 MP@4.99K/F_4 MP@4.99K/F_4 MP@4.99K/F_4 MP@4.99K/F_4 MP@4.99K/F_4
VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4
R351 C545 R340 C533 R341 C534 R7 C26 R342 C535 R350 C544 R5 C23 R343 C536
MP@0.1u/10V_4_X7R MP@0.1u/10V_4_X7R MP@0.1u/10V_4_X7R MP@0.1u/10V_4_X7R MP@0.1u/10V_4_X7R MP@0.1u/10V_4_X7R MP@0.1u/10V_4_X7R MP@0.1u/10V_4_X7R
MP@4.99K/F_4 MP@4.99K/F_4 MP@4.99K/F_4 MP@4.99K/F_4 MP@4.99K/F_4 MP@4.99K/F_4 MP@4.99K/F_4 MP@4.99K/F_4
Group-A0 decoupling CAP Group-A1 decoupling CAP MEM_A1 CLK

MEM_A0 CLK
+1.5V_GPU
+1.5V_GPU
VMA_CLK1
VMA_CLK0
VMA_CLK1#
VMA_CLK0# C532 C530 C19 C15 C526 C24 C25 C22
C13 C27 C528 C523 C11 C28 C10 C529 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4
MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 R345 R346
R2 R1 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@56.2/F_4
MP@56.2/F_4 MP@56.2/F_4
MP@56.2/F_4 +1.5V_GPU
+1.5V_GPU
C519
C2 C518 C546 C16 C531 C527 C17 C542 C517 MP@0.01u/25V_4
MP@0.01u/25V_4 C12 C9 C6 C524 C21 C525 C8 C7 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4
A MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 A
MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4 MP@1u/6.3V_4
+1.5V_GPU
+1.5V_GPU
C540 C539 C522 C5 C521

C20 C3 C18 C520 C547 MP@10u/6.3V_6 MP@10u/6.3V_6
MP@10u/6.3V_6
MP@10u/6.3V_6
MP@10u/6.3V_6
MP@10u/6.3V_6
MP@10u/6.3V_6
MP@10u/6.3V_6 MP@10u/6.3V_6 MP@10u/6.3V_6 Quanta Computer Inc.
PROJECT : ZR7B
1A
MEMORY 1 channel A
5 4 3 2 1
5 4 3 2 1
<18> VMB_DQ[63..0]
VMB_DQ[63..0] CHANNEL B: 512MB DDR3 (64M*16*4pcs)
VMB_DM[7..0]
<18> VMB_DM[7..0]
VMB_RDQS[7..0] QSA[7..0]
<18> VMB_RDQS[7..0]
VMB_WDQS[7..0] QSA#[7..0]
<18> VMB_WDQS[7..0]
U3 U23 U26 U5
VREFC_VMB1 M8 E3 VMB_DQ6 VREFC_VMB2 M8 E3 VMB_DQ17 VREFC_VMB3 M8 E3 VMB_DQ36 VREFC_VMB4 M8 E3 VMB_DQ54

VREFD_VMB1 VREFCA DQL0 VMB_DQ3 VREFD_VMB2 VREFCA DQL0 VMB_DQ23 VREFD_VMB3 VREFCA DQL0 VMB_DQ39 VREFD_VMB4 VREFCA DQL0 VMB_DQ51
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 VMB_DQ5 VREFDQ DQL1 VMB_DQ18 VREFDQ DQL1 VMB_DQ33 VREFDQ DQL1 VMB_DQ53
F2 F2 F2 F2
VMB_MA0 DQL2 VMB_DQ1 VMB_MA0 DQL2 VMB_DQ16 VMB_MA0 DQL2 VMB_DQ34 VMB_MA0 DQL2 VMB_DQ50
N3 F8 N3 F8 N3 F8 N3 F8
<18>
<18>
<18>
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ7
VMB_DQ0
VMB_DQ4
0 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ20
VMB_DQ22
VMB_DQ19
2 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ37
VMB_DQ32
VMB_DQ38
4 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ52
VMB_DQ48
VMB_DQ55
6
<18> VMB_MA3 N2 G2 N2 G2 N2 G2 N2 G2
D
VMB_MA4 A3 DQL6 VMB_DQ2 VMB_MA4 A3 DQL6 VMB_DQ21 VMB_MA4 A3 DQL6 VMB_DQ35 VMB_MA4 A3 DQL6 VMB_DQ49 D
<18> VMB_MA4 P8 H7 P8 H7 P8 H7 P8 H7
VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7
<18> VMB_MA5 P2 P2 P2 P2
VMB_MA6 A5 VMB_MA6 A5 VMB_MA6 A5 VMB_MA6 A5
<18> VMB_MA6 R8 R8 R8 R8
VMB_MA7 A6 VMB_DQ24 VMB_MA7 A6 VMB_DQ15 VMB_MA7 A6 VMB_DQ62 VMB_MA7 A6 VMB_DQ41
<18> VMB_MA7 R2 D7 R2 D7 R2 D7 R2 D7
VMB_MA8 A7 DQU0 VMB_DQ31 VMB_MA8 A7 DQU0 VMB_DQ10 VMB_MA8 A7 DQU0 VMB_DQ56 VMB_MA8 A7 DQU0 VMB_DQ46
<18> VMB_MA8 T8 C3 T8 C3 T8 C3 T8 C3
VMB_MA9 A8 DQU1 VMB_DQ28 VMB_MA9 A8 DQU1 VMB_DQ14 VMB_MA9 A8 DQU1 VMB_DQ63 VMB_MA9 A8 DQU1 VMB_DQ40
R3 C8 R3 C8 R3 C8 R3 C8
<18>
<18>
<18>
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ30
VMB_DQ26
VMB_DQ27
3 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ11
VMB_DQ12
VMB_DQ9
1 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ58
VMB_DQ61
VMB_DQ57
7 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ42
VMB_DQ44
VMB_DQ45
5
<18> VMB_MA12 N7 A2 N7 A2 N7 A2 N7 A2
VMB_MA13 A12/BC DQU5 VMB_DQ25 VMB_MA13 A12/BC DQU5 VMB_DQ13 VMB_MA13 A12/BC DQU5 VMB_DQ60 VMB_MA13 A12/BC DQU5 VMB_DQ43
<18> VMB_MA13 T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 VMB_DQ29 A13 DQU6 VMB_DQ8 A13 DQU6 VMB_DQ59 A13 DQU6 VMB_DQ47
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU
VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2

<18> VMB_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9
<18> VMB_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7
<18> VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
K8 K8 K8 K8
N1 N1 N1 N1
VMB_CLK0 VDD#N1 VMB_CLK0 VDD#N1 VMB_CLK1 VDD#N1 VMB_CLK1 VDD#N1
<18> VMB_CLK0 J7 N9 J7 N9 <18> VMB_CLK1 J7 N9 J7 N9
VMB_CLK0# CK VDD#N9 VMB_CLK0# CK VDD#N9 VMB_CLK1# CK VDD#N9 VMB_CLK1# CK VDD#N9
<18> VMB_CLK0# K7 R1 K7 R1 <18> VMB_CLK1# K7 R1 K7 R1
VMB_CKE0 CK VDD#R1 VMB_CKE0 CK VDD#R1 VMB_CKE1 CK VDD#R1 VMB_CKE1 CK VDD#R1
<18> VMB_CKE0 K9 R9 K9 R9 <18> VMB_CKE1 K9 R9 K9 R9
CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU
VMB_ODT0 K1 A1 VMB_ODT0 K1 A1 VMB_ODT1 K1 A1 VMB_ODT1 K1 A1

<18> VMB_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 <18> VMB_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMB_CS0# L2 A8 VMB_CS0# L2 A8 VMB_CS1# L2 A8 VMB_CS1# L2 A8
<18> VMB_CS0# CS VDDQ#A8 CS VDDQ#A8 <18> VMB_CS1# CS VDDQ#A8 CS VDDQ#A8
VMB_RAS0# J3 C1 VMB_RAS0# J3 C1 VMB_RAS1# J3 C1 VMB_RAS1# J3 C1
<18> VMB_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 <18> VMB_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMB_CAS0# K3 C9 VMB_CAS0# K3 C9 VMB_CAS1# K3 C9 VMB_CAS1# K3 C9
<18> VMB_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 <18> VMB_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMB_WE0# L3 D2 VMB_WE0# L3 D2 VMB_WE1# L3 D2 VMB_WE1# L3 D2
<18> VMB_WE0# WE VDDQ#D2 WE VDDQ#D2 <18> VMB_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
VMB_RDQS0 VDDQ#F1 VMB_RDQS2 VDDQ#F1 VMB_RDQS4 VDDQ#F1 VMB_RDQS6 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
VMB_RDQS3 DQSL VDDQ#H2 VMB_RDQS1 DQSL VDDQ#H2 VMB_RDQS7 DQSL VDDQ#H2 VMB_RDQS5 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
VMB_DM0 E7 A9 VMB_DM2 E7 A9 VMB_DM4 E7 A9 VMB_DM6 E7 A9

VMB_DM3 DML VSS#A9 VMB_DM1 DML VSS#A9 VMB_DM7 DML VSS#A9 VMB_DM5 DML VSS#A9
C D3 B3 D3 B3 D3 B3 D3 B3 C
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMB_WDQS0 VSS#G8 VMB_WDQS2 VSS#G8 VMB_WDQS4 VSS#G8 VMB_WDQS6 VSS#G8
G3 J2 G3 J2 G3 J2 G3 J2
VMB_WDQS3 DQSL VSS#J2 VMB_WDQS1 DQSL VSS#J2 VMB_WDQS7 DQSL VSS#J2 VMB_WDQS5 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
M9 M9 M9 M9
P1 P1 P1 P1
MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1
T2 P9 T2 P9 T2 P9 T2 P9
<18,19> MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMB_ZQ1 VSS#T1 VMB_ZQ2 VSS#T1 VMB_ZQ3 VSS#T1 VMB_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R26 VSSQ#B9 R360 VSSQ#B9 R384 VSSQ#B9 R59 VSSQ#B9
D1 D1 D1 D1
SW@240/F_4 D8 SW@240/F_4 D8 SW@240/F_4 D8 SW@240/F_4 D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SW@VRAM _DDR3 SW@VRAM _DDR3 SW@VRAM _DDR3 SW@VRAM _DDR3
BOT Down TOP Down TOP Up BOT Up
Group-B0 VREF Group-B1 VREF

+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R355 R16 R367 R357 R390 R392 R45 R64

SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4
VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2 VREFC_VMB3 VREFD_VMB3 VREFC_VMB4 VREFD_VMB4
R24 C65 R19 C51 R365 C569 R356 C559 R389 C594 R391 C589 R53 C183 R63 C190
SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R
SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4 SW@4.99K/F_4
Group-B0 decoupling CAP Group-B1 decoupling CAP MEM_B1 CLK

MEM_B0 CLK
+1.5V_GPU +1.5V_GPU
VMB_CLK1
VMB_CLK0 VMB_CLK1#
C86 C614 C553 C564 C554 C45 C154 C552 C192 C217 C224 C181 C583 C193 C201 C585
VMB_CLK0# SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 R71 R76
SW@56.2/F_4
R18 R17 SW@56.2/F_4
SW@56.2/F_4 +1.5V_GPU +1.5V_GPU
SW@56.2/F_4
A C203 A
C600 C165 C40 C47 C602 C566 C42 C142 C571 C604 C14 C209 C186 C575 C581 C601 SW@0.01u/25V_4
C556 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4
SW@0.01u/25V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4
+1.5V_GPU +1.5V_GPU
C69 C33 C570 C613 C557 C252 C168 C579 C4 C577

SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6
SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 PROJECT : ZR7B
1A
MEMORY 2 channel B
5 4 3 2 1
5 4 3 2 1
U24F
U24E
For DDR3, MVDDQ = 1.5V (7.5A)
+1.5V_GPU MEM I/O +1.8V_GPU
PCIE (1.8V@400mA PCIE_VDDR) 180 ohm/1.5A AB39 A3
PCIE_VDDR L4 SW@HCB1608KF-181T15/180ohm/1.5A_6 PCIE_VSS#1 GND#1
AC7 AA31 E39 A37
VDDR1#1 PCIE_VDDR#1 PCIE_VSS#2 GND#2
AD11 AA32 F34 AA16
AF7 AA33 F39 AA18
C77 C49 C551 C90 C555 VDDR1#3 PCIE_VDDR#3 C125 C145 C129 C143 C177 C144 C124 C185 PCIE_VSS#4 GND#4
AG10 AA34 G33 AA2
SW@10u/6.3V_6 SW@10u/6.3V_6 VDDR1#4 PCIE_VDDR#4 SW@0.1u/10V_4_X7R SW@1u/6.3V_4 SW@1u/6.3V_4 SW@10u/6.3V_6 PCIE_VSS#5 GND#5
AJ7 V28 G34 AA21
SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 VDDR1#5 PCIE_VDDR#5 SW@0.1u/10V_4_X7R SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 PCIE_VSS#6 GND#6
AK8 W29 H31 AA23
D VDDR1#6 PCIE_VDDR#6 PCIE_VSS#7 GND#7 D
AL9 W30 H34 AA26
G11 Y31 H39 AA28
G14 J31 AA6
VDDR1#9 PCIE_VSS#10 GND#10
G17 J34 AB12
VDDR1#10 +1V PCIE_VSS#11 GND#11
G20 G30 K31 AB15
C155 C89 C54 C126 C122 C55 VDDR1#11 PCIE_VDDC#1 PCIE_VSS#12 GND#12
G23
VDDR1#12 PCIE_VDDC#2
G31 (1.0V@1.1A PCIE_VDDC) K34
PCIE_VSS#13 GND#13
AB17
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 G26 H29 K39 AB20
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 VDDR1#13 PCIE_VDDC#3 PCIE_VSS#14 GND#14
G29 H30 L31 AB22
VDDR1#14 PCIE_VDDC#4 PCIE_VSS#15 GND#15
H10 J29 L34 AB24
VDDR1#15 PCIE_VDDC#5 C71 C68 C74 C98 C87 C80 C108 C57 PCIE_VSS#16 GND#16
J7 J30 M34 AB27
VDDR1#16 PCIE_VDDC#6 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@10u/6.3V_6 PCIE_VSS#17 GND#17
J9 L28 M39 AC11
VDDR1#17 PCIE_VDDC#7 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 PCIE_VSS#18 GND#18
K11 M28 N31 AC13
K13 N28 N34 AC16
K8 R28 P31 AC18
C187 C172 C64 C100 C59 C175 VDDR1#20 PCIE_VDDC#10 PCIE_VSS#21 GND#21
L12 T28 P34 AC2
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 VDDR1#21 PCIE_VDDC#11 PCIE_VSS#22 GND#22
L16 U28 P39 AC21
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 VDDR1#22 PCIE_VDDC#12 +VGPU_CORE PCIE_VSS#23 GND#23
L21 R34 AC23
VDDR1#23 PCIE_VSS#24 GND#24
L23
VDDR1#24 (30A or more) T31
PCIE_VSS#25 GND#25
AC26
L26 AA15 T34 AC28
VDDR1#25 CORE VDDC#1 PCIE_VSS#26 GND#26
L7 AA17 T39 AC6
VDDR1#26 VDDC#2 PCIE_VSS#27 GND#27
M11 AA20 U31 AD15
VDDR1#27 VDDC#3 C109 C127 C91 C140 C104 C149 C151 C93 C117 C111 PCIE_VSS#28 GND#28
N11 AA22 U34 AD17
C157 C76 C53 C52 C194 VDDR1#28 VDDC#4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 PCIE_VSS#29 GND#29
P7 AA24 V34 AD20
SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R VDDR1#29 VDDC#5 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 PCIE_VSS#30 GND#30
R11 AA27 V39 AD22
SW@1u/6.3V_4 SW@0.1u/10V_4_X7R SW@0.1u/10V_4_X7R VDDR1#30 VDDC#6 PCIE_VSS#31 GND#31
U11 AB16 W31 AD24
U7 AB18 W34 AD27
Y11 AB21 Y34 AD9
Y7 AB23 Y39 AE2
AB26 AE6
VDDC#11 GND#36
AB28 AF10
VDDC#12 C139 C150 C158 C120 C105 C75 C118 C94 C112 C103 GND#37
AC17 AF16
VDDC#13 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 GND#38
AC20 AF18
LEVEL VDDC#14 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 GND#39
AC22 AF21
(1.8V@110mA VDD_CT) TRANSLATION VDDC#15
VDDC#16
AC24 GND GND#40
GND#41
AG17 PowerXpress control signal for Madsion and Park only
POWER
L2 SW@BLM15AG121SS1/0.5A/120ohm_4 VDDC_CT AF26 AC27 F15 AG2 If not used, can be disconnected.
+1.8V_GPU VDD_CT#1 VDDC#17 GND#100 GND#42
AF27 AD18 F17 AG20 PX_EN = LOW, turn on
VDD_CT#2 VDDC#18 GND#101 GND#43
AG26 AD21 F19 AG22 PX_EN = HIGH, turn off
C180 C178 C169 VDD_CT#3 VDDC#19 GND#102 GND#44
C AG27 AD23 F21 AG6 PX_EN is used to turn ON/OFF some C
SW@1u/6.3V_4 VDD_CT#4 VDDC#20 GND#103 GND#45
AD26 F23 AG9 regulators for PowerXpress mode. An
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R VDDC#21 C159 C92 C160 C110 C138 C102 C141 C119 C171 C152 GND#104 GND#46
AF17 F25 AH21
I/O VDDC#22 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 GND#105 GND#47 output high 3.3V will turn the regulators
(3.3V@60mA)) VDDC#23
AF20 F27
GND#106 GND#48
AJ10
OFF. An output low 0V will turn the
+3V_D AF23 AF22 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 F29 AJ11
VDDR3#1 VDDC#24 GND#107 GND#49 regulators ON. PX_EN outputs low (0V)
AF24 AG16 F31 AJ2
VDDR3#2 VDDC#25 GND#108 GND#50 by default.
AG23 AG18 F33 AJ28
C255 C179 C170 C173 VDDR3#3 VDDC#26 GND#109 GND#51 If this signal is unused, it can be NC (not
AG24 AG21 F7 AJ6
SW@1u/6.3V_4 SW@1u/6.3V_4 VDDR3#4 VDDC#27 GND#110 GND#52
AH22 F9 AK11 connected) or connected to ground.
SW@10u/6.3V_6 SW@1u/6.3V_4 VDDC#28 GND#111 GND#53
AH27 G2 AK31
VDDC#29 C156 C130 C88 C114 C135 C133 GND#112 GND#54 +3V_D
AF13 AH28 G6 AK7
VDDR4#4 VDDC#30 SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 GND#113 GND#55
AF15 M26 H9 AL11
VDDR4#5 VDDC#31 SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 GND#114 GND#56
AG13 N24 J2 AL14
L11 SW@BLM15AG121SS1/0.5A/120ohm_4 VDDR4 VDDR4#7 VDDC#32 GND#115 GND#57 R78
+1.8V_GPU AG15 N27 J27 AL17
VDDR4#8 VDDC#33 GND#116 GND#58
R18 J6 AL2
VDDC#34 GND#117 GND#59 *10K_4
VDDC#35
R21 BIF_VDDC should be connected to VDDC if BACO feature not used. J8
GND#118 GND#60
AL20
C230 C231 AD12 R23 K14 AL21
SW@0.1u/10V_4_X7R AF11 VDDR4#1 VDDC#36 For BACO, refer to the databook GND#119 GND#61
R26 K7 AL23
SW@1u/6.3V_4 VDDR4#2 VDDC#37 GND#120 GND#62
AF12 T17 L11 AL26
VDDR4#3 VDDC#38 GND#121 GND#63 R75
AG11 T20 L17 AL32
VDDR4#6 VDDC#39 +VGPU_CORE GND#122 GND#64
T22 L2 AL6
VDDC#40 GND#123 GND#65 *SW@0_4
T24 L22 AL8
VDDC#41 R28 SW@0_4 GND#124 GND#66
T27 L24 AM11
VDDC#42 C95 C115 GND#125 GND#67
U16 L6 AM31
T2 VDDC#43 GND#126 GND#68
M20 U18 M17 AM9
T1 NC_VDDRHA VDDC#44 SW@1u/6.3V_4
SW@1u/6.3V_4 GND#127 GND#69
M21 U21 M22 AN11
NC_VSSRHA VDDC#45 GND#128 GND#70
U23 M24 AN2
VDDC#46 GND#129 GND#71
U26 N16 AN30
T5 VDDC#47 +VGPU_CORE +VGPU_IO GND#130 GND#72
V12 V17 N18 AN6
T4 NC_VDDRHB VDDC#48 GND#131 GND#73
U12 V20 N2 AN8
NC_VSSRHB VDDC#49 GND#132 GND#74
V22 N21 AP11
V24 N23 AP7
(For M97, Broadway, Madison and Park SPV10 = 1.0V) VDDC#52
V27 VDDCI and VDDC should have seperate regulators with a merge option on PCB N26
GND#135 GND#77
AP9
Y16 For Madison and Park, VDDCI and VDDC can share one common regulator N6 AR5
PLL VDDC#53 GND#136 GND#78
(1.8V@40mA PCIE_PVDD) VDDC#54
Y18 R15
GND#137 GND#79
AW34
L40 SW@BLM15AG121SS1/0.5A/120ohm_4 PCIE_PVDD AB37 Y21 R17 B11
+1.8V_GPU PCIE_PVDD VDDC#55 GND#138 GND#80
Y23 R2 B13
MPV18 VDDC#56 GND#139 GND#81
H7 Y26 R20 B15
B
C572 C573 C574 MPV18#1 VDDC#57 GND#140 GND#82 B
H8 Y28 R22 B17
SW@1u/6.3V_4 MPV18#2 VDDC#58 GND#141 GND#83
R24 B19
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R +VGPU_IO GND#142 GND#84
R27 B21
SPV18 GND#143 GND#85
AM10
SPV18 (DDR3 1.12V@4A VDDCI) or more R6
GND#144 GND#86
B23
(1.8V@75mA/Park & 150mA/Madison MPV18) VDDCI#1
AA13 T11
GND#145 GND#87
B25
L1 SW@BLM15AG121SS1/0.5A/120ohm_4 SPV10 AN9 AB13 T13 B27
+1.8V_GPU SPV10 VDDCI#2 GND#146 GND#88
AC12 T16 B29
VDDCI#3 C72 C147 C161 C106 C101 C162 C146 C81 C78 C79 GND#147 GND#89
AN10 AC15 T18 B31
C46 C50 C66 SPVSS VDDCI#4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 GND#148 GND#90
AD13 T21 B33
SW@1u/6.3V_4 VDDCI#5 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 GND#149 GND#91
AD16 T23 B7
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R VDDCI#6 GND#150 GND#92
M15 T26 B9
VDDCI#7 GND#151 GND#93
M16 U15 C1
VOLTAGE VDDCI#8 GND#153 GND#94
M18 U17 C39
SENESE VDDCI#9 GND#154 GND#95
(1.8V@75mA SPV18) VDDCI#10
M23 U2
GND#155 GND#96
E35
+1.8V_GPU L12 SW@BLM15AG121SS1/0.5A/120ohm_4 N13 PIN different between Broadway and Madison U20 E5
VDDCI#11 GND#156 GND#97
T9 AF28 N15 U22 F11
FB_VDDC VDDCI#12 C70 C134 C82 Pin Broadway Madison GND#157 GND#98
N17 U24 F13
C214 C206 VDDCI#13 SW@10u/6.3V_6 GND#158 GND#99
N20 U27
SW@0.1u/10V_4_X7R VDDCI#14 SW@10u/6.3V_6 SW@10u/6.3V_6 N27 VDDC BIF_VDDC GND#159
T10 AG28 N22 U6
SW@10u/6.3V_6 FB_VDDCI ISOLATED VDDCI#15 T27 GND#160
R12 V11
CORE I/O VDDCI#16 R13 V16
GND#161
VDDCI#17 AL31 TS_A NC_TS_A GND#163
T12 AH29 R16 V18
FB_GND VDDCI#18 GND#164
(1.0V@120mA SPV10) VDDCI#19
T12 V21
GND#165
+1V L7 SW@BLM15AG121SS1/0.5A/120ohm_4 T15 V23
VDDCI#20 AL21 GND PX_EN GND#166
V15 V26
VDDCI#21 GND#167
Y13 W2
C215 C205 VDDCI#22 GND#168
W6
SW@0.1u/10V_4_X7R GND#169
Y15
SW@10u/6.3V_6 SW@Madison/Broadway_M2 GND#170
Y17
GND#171
Y20
VDDC_SENSE/VSS_SENSE and VDDCI_SENSE/VSS_SENSE route as differetial pair GND#172
Y22 A39
GND#173 VSS_MECH#1
Y24 AW1
+3V GND#174 VSS_MECH#2
Y27 AW39
GND#175 VSS_MECH#3
U13
GPU +3V power GPU all PWROK +3V_S5 V13
GND#152
+3V +3V +3V GND#162
R109 SW@Madison/Broadway_M2
A SW@10K_4 A
1
R111 R123
SW@4.7K_4 SW@10K_4 dGPU_PWROK <11>
3
R110
dGPU_VRON_N 2 *SW@0_6 dGPU_VRON_N2 Q55 R768
*SW@0_6
SW@AO3413 SW@AO3413 Q10
2
3
Q7 SW@2N7002E
0.5A 0.5A
3
R100 *SW@0_4 2 Q5
+1.5V_GPU
SW@PDTC143TT
+3V_D +3V_D_S
1
C254 C615 C620 C621 C943 C944 C945 +1.8V_GPU 2

R101
PROJECT : ZR7B
1
<11,44> dGPU_VRON
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@10u/6.3V_6 SW@.1u/10V_4
*SHORT0402 SW@10u/6.3V_6 SW@0.1u/10V_4_X7R SW@1u/10V_4 Q8 Size Document Number Rev
1
SW@PDTC143TT 1A
Madison/Broadway (PWR/GND)
5 4 3 2 1
5 4 3 2 1
+1.8V_GPU +1V
(1.8V@130mA DPA_VDD18) U24H (1.0V@110mA DPA_VDD10)
DPA_VDD10 L8 SW@BLM15AG121SS1/0.5A/120ohm_4
L10 SW@BLM15AG121SS1/0.5A/120ohm_4 DPA_VDD18 DP C/D POWER DP A/B POWER
DPA_VDD18 AP20 AN24 DPA_VDD18 C216 C197 C213

C222 C220 C212 DPC_VDD18#1 DPA_VDD18#1 SW@1u/6.3V_4
AP21 DPC_VDD18#2 DPA_VDD18#2 AP24
SW@1u/6.3V_4 SW@10u/6.3V_6 SW@0.1u/10V_4_X7R
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R
D D
DPA_VDD10 AP13 AP31 DPA_VDD10
DPC_VDD10#1 DPA_VDD10#1
AT13 DPC_VDD10#2 DPA_VDD10#2 AP32
AN17 DPC_VSSR#1 DPA_VSSR#1 AN27

AP16 DPC_VSSR#2 DPA_VSSR#2 AP27
AP17 DPC_VSSR#3 DPA_VSSR#3 AP28
AW14 DPC_VSSR#4 DPA_VSSR#4 AW24
AW16 DPC_VSSR#5 DPA_VSSR#5 AW26
DPA_VDD18 AP22 AP25 DPA_VDD18

DPD_VDD18#1 DPB_VDD18#1
AP23 DPD_VDD18#2 DPB_VDD18#2 AP26
DPA_VDD10 AP14 AN33 DPA_VDD10

DPD_VDD10#1 DPB_VDD10#1
AP15 DPD_VDD10#2 DPB_VDD10#2 AP33
C AN19 DPD_VSSR#1 DPB_VSSR#1 AN29 C

AP18 DPD_VSSR#2 DPB_VSSR#2 AP29
AP19 DPD_VSSR#3 DPB_VSSR#3 AP30
AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
AW22 DPD_VSSR#5 DPB_VSSR#5 AW32
R104 SW@150/F_4 DPCD_CALR AW18 AW28 DPAB_CALR R408 SW@150/F_4 +1.8V_GPU

DPCD_CALR DPAB_CALR
(1.8V@20mA DPA_PVDD)
DPA_PVDD L17 SW@BLM15AG121SS1/0.5A/120ohm_4
DP E/F POWER DP PLL POWER
AH34 DPE_VDD18#1 DPA_PVDD AU28
DPE_VDD18 AJ34 AV27 C244 C237 C238
DPE_VDD18#2 DPA_PVSS SW@1u/6.3V_4
SW@10u/6.3V_6 SW@0.1u/10V_4_X7R +1.8V_GPU
AL33 AV29 DPB_PVDD (1.8V@20mA DPB_PVDD) L16 SW@BLM15AG121SS1/0.5A/120ohm_4

DPE_VDD10 DPE_VDD10#1 DPB_PVDD
AM33 DPE_VDD10#2 DPB_PVSS AR28
+1.8V_GPU (1.8V@400mA DPE/F_VDD18)
C243 C236 C235
L3 SW@BLM15AG121SS1/0.5A/120ohm_4DPE_VDD18 SW@1u/6.3V_4
AN34 AU18 SW@10u/6.3V_6 SW@0.1u/10V_4_X7R +1.8V_GPU
DPE_VSSR#1 DPC_PVDD
AP39 DPE_VSSR#2 DPC_PVSS AV17
B C167 C182 C184 AR39 DPC_PVDD L14 SW@BLM15AG121SS1/0.5A/120ohm_4 B
SW@1u/6.3V_4 DPE_VSSR#3
AU37 DPE_VSSR#4 (1.8V@20mA DPC_PVDD)
SW@0.1u/10V_4_X7R SW@10u/6.3V_6 AW35 DPE_VSSR#5 C246 C234 C240
DPD_PVDD AV19
AR18 SW@1u/6.3V_4
DPD_PVSS SW@10u/6.3V_6 SW@0.1u/10V_4_X7R +1.8V_GPU
AF34 DPF_VDD18#1
DPE_VDD18 AG34 DPD_PVDD L18 SW@BLM15AG121SS1/0.5A/120ohm_4
+1V DPF_VDD18#2
(1.0V@400mA DPE/F_VDD10) DPE_PVDD AM37
DPE_PVSS AN38 (1.8V@20mA DPD_PVDD)
L9 SW@BLM15AG121SS1/0.5A/120ohm_4 DPE_VDD10 C245 C233 C239
AK33 SW@1u/6.3V_4
DPE_VDD10 DPF_VDD10#1 SW@10u/6.3V_6 SW@0.1u/10V_4_X7R
AK34 DPF_VDD10#2
C226 C221 C210 AL38
SW@1u/6.3V_4 NC_DPF_PVDD
NC_DPF_PVSS AM35
SW@0.1u/10V_4_X7R SW@10u/6.3V_6
AF39 DPF_VSSR#1
AH39 +1.8V_GPU
DPF_VSSR#2
AK39 DPF_VSSR#3 (1.8V@40mA DPE/F_PVDD)
AL34 DPE_PVDD L43 SW@BLM15AG121SS1/0.5A/120ohm_4
DPF_VSSR#4
AM34 DPF_VSSR#5
C595 C599 C598
SW@1u/6.3V_4
A R70 SW@150/F_4 DPEF_CALR AM39 SW@10u/6.3V_6 SW@0.1u/10V_4_X7R A
DPEF_CALR
PROJECT : ZR7B
1A
Madison/Broadway (DP_PWR/GND)
5 4 3 2 1
5 4 3 2 1
PIN STRAPS
CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
+3V_D Memory Aperture size THEY MUST NOT CONFLICT DURING RESET
R57 *SW@10K/F_4 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS DEFAULT REMARK

<17> GPU_GPIO0 GPIO[13:11] Size
R52 *SW@10K/F_4
<17> GPU_GPIO1
TX_PWRS_ENB GPIO0 0 = 50% TX OUTPUT SWING 0
D 1 = FULL TX OUTPUT SWING D
000 128MB
TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0
R51 *SW@10K/F_4 001 256MB 0 = TX DE-EMPHASIS DISABLED
<17> GPIO3_SMBDAT
1 = TX DE-EMPHASIS ENABLED
R48 *SW@10K/F_4 ENABLE EXTERNAL BIOS ROM
<17> GPIO4_SMBCLK
010 64MB BIOS_ROM_EN GPIO_22_ROMCSB 0 = DISABLE 0
1 = ENABLE
SCS#_GPIO22 R418 *SW@10K/F_4
011 32MB ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 000 See Memory Aperture size
NUMONYX M25P10A : 101
R81 *SW@10K/F_4
<17> GPU_GPIO13
R69 *SW@10K/F_4 BIF_GEN2_EN_A GPIO2 0 = PCIE DEVICE AS 2.5GT/S CAPABLE 0
<17> GPU_GPIO12
1 = PCIE DEVICE AS 5GT/S CAPABLE
R79 *SW@10K/F_4
<17> GPU_GPIO11
GPIO_8_ROMSO GPIO8
H2SYNC H2SYNC Reserved Only 0
R82 *SW@10K/F_4 GPIO_21_BB_EN GPIO21
<17> GPU_GPIO2 ROM Table
AUD[1:0]
R42 SW@10K/F_4 EXT_HSYNC EXT_VSYNC AUD[1] HSYNC 00: NO AUDIO FUNCTION.
<17,24> EV_HSYNC Discription 01: AUDIO FOR DISPLAYPORT AND HDMI IF
R43 SW@10K/F_4 AUD[0] VSYNC ADAPTER IS DETECTED. 11 See Audio table
<17,24> EV_VSYNC
0 0 No Audio 10: AUDIO FOR DISPLAYPORT ONLY.
SIN_GPIO9 R96 *SW@10K/F_4 11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.
R38 *SW@10K/F_4 0 1 Any one by dectec

<17> V2SYNC
GPIO_9_ROMSI GPIO9 0 = VGA controller capacity enable 0
C C
1 0 DP only
VIP_DEVICE_STRAP_ENA V2SYNC 0 = DRIVER would ignore the value sample on VHAD_0 during RESET. 0
1 1 Both DP & HDMI
DDR3 Memory Aperture size

EEPROM
U29
SIN_GPIO9 5 2 SOUT_GPIO8
<17> SIN_GPIO9
6
D Q SOUT_GPIO8 <17>
DDR3 Memory Aperture size
<17> SCLK_GPIO10 C
SCS#_GPIO22 1 RAM_STRAP2 RAM_STRAP1 RAM_STRAP0
<17> SCS#_GPIO22 S
Vendor Vendor P/N STN B/S P/N Size
+3V_D_S 7 HOLD DVPDATA_2 DVPDATA_1 DVPDATA_0
R424 *SW@10K_4 3
W
8 VCC VSS 4 512MB 1 1 0
R428
*SW@10K_4C619 *SW@M25P10-AVMN6P Hynix H5TQ1G63BFR-12C AKD5LZGTW04
*SW@0.1u/10V_4 (64M*16) 1GB 1 0 0
B B
2GB 1 0 1
Thermal Sensor NS none 512MB
WINDBOND AL83L771K02 K4W1G1646E-HC12 AKD5LGGT506
GMT AL000780003 Samsung (64M*16) 1GB 0 0 0
K4W2G1646B-HC12 AKD5MGGT500 2GB 0 0 1
AMD 23EY2387MA12-SZ AKD5LGGT700 1GB
+3V_D_S 0 1 0
+3V_D_S +1.8V_GPU
R430 R423
SW@10K_4
SW@10K_4 C623 SW@0.1u/10V_4_X7R R422 *VRAM@10K/F_4
<17> RAM_STRAP2
U31 R421 VRAM@10K/F_4
<37> MXM_SMCLK12 8 SCLK VCC 1 GPU_D+ <17>

A A
<37> MXM_SMDATA12 7
SDA DXP
2 C617
<17> RAM_STRAP1
R427 *VRAM@10K/F_4 RAM_STRAP2 SET DDR3 Vendor
<17> ALT#_GPIO17 6 3 SW@2200p/50V_4 R426 VRAM@10K/F_4 RAM_STRAP[1:0] SET SIZE.
ALERT# DXN
GPU_D- <17>
<37> VGA_THERM# 4 5
OVERT# GND R416 *VRAM@10K/F_4
SW@G780-1P81U(MSOP) R415 VRAM@10K/F_4

<17> RAM_STRAP0
ADDRESS: 9AH PROJECT : ZR7B
1A
Strip/Thermal
5 4 3 2 1
1 2 3 4 5 6 7 8
CRT Switch CRT updatefootprint 12/11

+5V +5V C257 0.1u/10V_4_X7R
IV@ 3.3V or 5V level? F1

D10 SSM22LLPT CRTVDD5
16
2 1
SW@ C277
U9
C250
U8
+5V
SMD1206P110TFT
CN13
CRT
SW@0.22u/6.3V_4 16 8 SW@0.22u/6.3V_4 16 8 6
VCC GND VCC GND VGA_RED L22 BLM18BA750SN1D/0.3A/75ohm_6 CRT_R1 CRT_11
1 11 T66
7
2 EV_CRTDCLK 2 VGA_GRN L21 BLM18BA750SN1D/0.3A/75ohm_6 CRT_G1 2 12 DDCDAT_1
<17> EV_CRT_BLU IA0 <17> EV_CRTDCLK IA0
5 4 VGA_BLU EV_CRTDDAT 5 4 CRTDCLK 8
<17> EV_CRT_GRN IB0 YA <17> EV_CRTDDAT IB0 YA
11 EV_LVDS_DDCDAT 11 VGA_BLU L20 BLM18BA750SN1D/0.3A/75ohm_6 CRT_B1 3 13 CRTHSYNC
<17> EV_CRT_RED IC0 <17> EV_LVDS_DDCDAT IC0
14 7 VGA_GRN EV_LVDS_DDCCLK 14 7 CRTDDATA 9
ID0 YB <17> EV_LVDS_DDCCLK ID0 YB
4 14 CRTVSYNC
A A
3 9 VGA_RED INT_CRT_DDCCLK 3 9 LCD_EDIDDATA R134 R132 R115 C279 C275 C263 C270 C271 C276 10
<8> INT_CRT_BLU IA1 YC <8> INT_CRT_DDCCLK IA1 YC
6 INT_CRT_DDCDAT 6 5 15 DDCCLK_1
<8> INT_CRT_GRN IB1 <8> INT_CRT_DDCDAT IB1
10 12 INT_LVDS_EDIDDATA 10 12 LCD_EDIDCLK 150/F_4 150/F_4 150/F_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4
<8> INT_CRT_RED IC1 YD <8> INT_LVDS_EDIDDATA IC1 YD
13 INT_LVDS_EDIDCLK 13
ID1 <8> INT_LVDS_EDIDCLK ID1
17
dGPU_SELECT# 1 15 1 15
S OE <10> dGPU_EDIDSEL# S OE
SW@SN74CBT3257CPWR SW@SN74CBT3257CPWR
S Yn +5V
dGPU_SELECT# Output
0 EV L EV_LVDS
C278
U10 INT_CRT_RED R133 IV@0_4 VGA_RED
1 IV H INT_LVDS +3V
SW@0.22u/6.3V_4
16 8 INT_CRT_GRN R112 IV@0_4 VGA_GRN
VCC GND INT_CRT_BLU R113 IV@0_4 VGA_BLU C642 U32
INT_VSYNC R130 IV@0_4 VSYNC CRTVDD5 1 16 CRT_VSYNC2 R437 *Short_4 CRTVSYNC C646 *.1u/10V_4 CRTVDD5
INT_HSYNC R125 IV@0_4 HSYNC 0.1u/10V_4_X7R VCC_SYNC SYNC_OUT2 CRT_HSYNC2 R438 *Short_4 CRTHSYNC
<17> EV_LVDS_BLON 2 14
IA0 LVDS_BLON INT_CRT_DDCDAT R93 IV@0_4 CRTDDATA SYNC_OUT1 C648 *10p/50V_4 CRTVSYNC
<17> EV_LVDS_VDDEN 5 4 7
IB0 YA INT_CRT_DDCCLK R103 IV@0_4 CRTDCLK C632 .22u/25V_6 CRT_BYP VCC_DDC
<17,23> EV_HSYNC 11 8
IC0 LVDS_VDDEN INT_LVDS_EDIDDATA R114 IV@0_4 LCD_EDIDDATA BYP VSYNC CRTVDD5 C649 *10p/50V_4 CRTHSYNC
<17,23> EV_VSYNC 14 7 15
ID0 YB INT_LVDS_EDIDCLK R102 IV@0_4 LCD_EDIDCLK SYNC_IN2 HSYNC +3V
+3V 2 13
HSYNC VCC_VIDEO SYNC_IN1 C631 10p/50V_4 DDCCLK_1
<8> INT_LVDS_BLON 3 9
IA1 YC INT_LVDS_DIGON RN5
<8> INT_LVDS_DIGON 6 1 2 IV@0_4P2RLVDS_VDDEN C643 R431 R436
IB1
<8> INT_HSYNC 10 12 VSYNC INT_LVDS_BLON 3 4 LVDS_BLON CRT_R1 3 10 CRTDCLK R432 2.7K_4 C647 10p/50V_4 DDCDAT_1
IC1 YD 0.1u/10V_4_X7R CRT_G1 VIDEO_1 DDC_IN1 CRTDDATA R433 2.7K_4 2.7K_4 2.7K_4
<8> INT_VSYNC 13 4 11
ID1 CRT_B1 VIDEO_2 DDC_IN2
5
VIDEO_3 DDCCLK_1
9
dGPU_SELECT# DDC_OUT1 DDCDAT_1
1 15 6 12
S OE GND DDC_OUT2
SW@SN74CBT3257CPWR CM2009-02QR
B B
LVDS Switch LVDS LCD Power

+3V VIN
U6
+3V
46 6 TXLCLKOUT+
<17> EV_TXLCLKOUT+ A2P C2P
45 7 TXLCLKOUT- C241 C256
<17> EV_TXLCLKOUT- A2N C2N C116 C97
44 9 TXLOUT2+ +1.8V 0.1u/10V_4_X7R C247 U7
<17> EV_TXLOUT2+ A1P C1P
43 10 TXLOUT2- 1000p/50V_4 4.7u/25V_8 1000p/50V_4
<17> EV_TXLOUT2- A1N IN_A OUT_C C1N 1U/6.3V_4 6 1 LCDVCC
TXLOUT1+ IN OUT
<17> EV_TXLOUT1+ 41 15
3
A0P C0P TXLOUT1-

<17> EV_TXLOUT1- 40 16 4 2
A0N C0N IN GND C262 C259 C260 C261 C258
39 18 TXLOUT0+ LVDS_VDDEN 3 5
<17> EV_TXLOUT0+ ACLKP CCLKP ON/OFF GND
38 19 TXLOUT0- 2 *.1u/10V_4 *2.2u/10V_8 0.1u/10V_4_X7R.01u/25V_4 22u/6.3V_8
<17> EV_TXLOUT0- ACLKN CCLKN dGPU_SELECT# <10>
Q6 AAT4280-4
SW@2N7002K CN5
G_0
+3V LCDVCC
1
1 R97
<8> INT_TXLCLKOUT+ 35
B2P dGPU_SELECT_R 2
<8> INT_TXLCLKOUT- 34 13
B2N SEL 3 G_1
R95 2.2K_4 LCD_EDIDCLK 4 100K_4
<8> INT_TXLOUT2+ 33
B1P R99 R94 2.2K_4 LCD_EDIDDATA 5
<8> INT_TXLOUT2- 32
B1N 6
1
VSS SW@100K_4 TXLOUT0- 7
<8> INT_TXLOUT1+ 30 3
B0P VSS TXLOUT0+ 8
<8> INT_TXLOUT1- 29 5
B0N IN_B VSS 9
8
VSS TXLOUT1- 10
<8> INT_TXLOUT0+ 28 11
BCLKP VSS TXLOUT1+ 11
<8> INT_TXLOUT0- 27 14
+1.8V BCLKN VSS 12
17
VSS TXLOUT2- 13
48 20
C248 SW@1000p/50V_4 VDD VSS TXLOUT2+ 14
36 22
C202 SW@1000p/50V_4 VDD VSS 15 G_2
25 24
C229 SW@0.22u/6.3V_4 VDD VSS TXLCLKOUT- 16
C
C225 SW@0.1u/10V_4_X7R
23
21
VDD VSS
26
31
S Yn TXLCLKOUT+ 17 Backlight Control C
C253 SW@0.1u/10V_4_X7R VDD VSS 18

12 37
VDD VSS 19
C251 SW@2.2u/6.3V_6
4
2
VDD VSS
42
47
0 EV <37> PANEL_COLOR 20
VDD VSS 21
22
1 IV LVDS_BRIGHT R614 23
SW@TS3DV421DGVR 24
BL_ON BLM15AG121SS1/0.5A/120ohm_4
VIN 25
<37> PANEL_ENG 26
27
LID591#,EC intrnal PU
dGPU_SELECT# Output 0.8A 28 G_4
R29 *SHORT0805 LID591# <34,37>
R32 *SHORT0805 INVCC0 29
30
G_3
L EV_LVDS
INT_TXLCLKOUT- RN1 1 2 IV@0_4P2R TXLCLKOUT- LVD-A30SFYG+ +3V
INT_TXLCLKOUT+ 3 4 TXLCLKOUT+ H INT_LVDS
1
INT_TXLOUT0- RN4 1 2 IV@0_4P2R TXLOUT0-
INT_TXLOUT0+ 3 4 TXLOUT0+ D3
INT_TXLOUT1- RN3 1 2 IV@0_4P2R TXLOUT1- BAS316
INT_TXLOUT1+ 3 4 TXLOUT1+ CN4
INT_TXLOUT2- RN2 1 2 IV@0_4P2R TXLOUT2- +3V 8 10 R55
2
INT_TXLOUT2+ 3 4 TXLOUT2+ 7 9
USBP8-_R 6 R41 10K_4
USBP8+_R 5 BL_ON
4 10K_4
3
3
+3V DMIC_CLK_1 2
<30> DMIC_CLK_1
3
<30> DMIC0_1 DMIC0_1 1
BL# 2
8P CON 2 EC_FPBACK# <37>
3
C188 Q2
2N7002K Q1
SW@0.22u/6.3V_4 DTC144EUA
1
LVDS_BLON 2
U4 R91 *0_4
Q3
D R49 *SHORT0402 5 6 L13 R46 2N7002K D
<37> CONTRAST VCC S PWM_SELECT# <9,10>
2 1 USBP8-_R
<10> USBP8-
1
2 1 USBP8+_R 100K_4
<10> USBP8+ 3 4
R56 *0_4 LVDS_BRIGHT 3 4
<17> EV_LVDS_BRIGHT 3 4
B0 YA RFCMF1632100M3T/200mA/90ohm
R90 *0_4
<8> INT_LVDS_BRIGHT 1 2
B1 GND
SW@74LVC1G3157GW
R62 IV@0_4
PROJECT : ZR7B
1A
CRT/LVDS/CAMERA/LID
1 2 3 4 5 6 7 8
5 4 3 2 1
SW@HDMI-detect
+3V +3V
I@ HDMI LEVEL SHIFTER
<9> HDMI_HPD_PCH#
R639 *0_4 To MXM
R441 R442
+3V 10K_4 SW@10K_4
HDMI_MB_HP
MB_HDMI_DDCDATA HDMI_HPD_EC# HDMI_HP_EV <17>
<37> HDMI_HPD_EC#
MB_HDMI_DDCCLK
IV@
3
C325 C383 C687 C327 C680 +3V R164 *4.7K_4 HDMI_HPD_EC# +5V
IV@2.2u/6.3V_6 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 DDCBUF_EN

D
SW@ CFG
+3V +3V R138
2 D
3
Active Buffer *10K_4 Q34
SP@ +3V
close to pin2/11/15/21/26/33/40/46 SW@2N7002E
1
HDMI_MB_HP
36
35
34
33
32
31
30
29
28
27
26
25
U13 2
CCT2
CCT1
OE#
HPD_SINK
SDA_SINK
SCL_SINK
GND
VCC
DDC_EN
GND
GND
VCC
C686 C688 Q33
2N7002E
from PCH
1
*IV@.1u/10V_4 *IV@.1u/10V_4 37 24
GND GND MB_HDMITX0N
<8> INT_HDMITX0N 38 23
IN_D1- OUT_D1- MB_HDMITX0P
<8> INT_HDMITX0P 39 22
IN_D1+ OUT_D1+
+3V 40 21 +3V
VCC VCC MB_HDMITX2N
<8> INT_HDMITX2N 41 20
IN_D2- OUT_D2- MB_HDMITX2P
<8> INT_HDMITX2P 42 19
IN_D2+ OUT_D2+
43 18
GND GND MB_HDMITX1P
44 17
<8> INT_HDMITX1P
<8> INT_HDMITX1N 45
IN_D3-
IN_D3+
OUT_D3-
OUT_D3+
16 MB_HDMITX1N I2C
+3V 46 15 +3V
VCC VCC MB_HDMICLK+
<8> INT_HDMICLK+ 47 14
IN_D4- OUT_D4- MB_HDMICLK-
<8> INT_HDMICLK- 48 13
IN_D4+ OUT_D4+ D12 2 1RB501V-40
HPDEN
49
HPD_S
SDA_S
SCL_S
GND +5V
REXT
TRIM
GND
GND
GND
VCC
VCC
NC
1
2
3
4
5
6
7
8
9
10
11
12
IV@PS8101 R443 +5V R147
+3V SW@1.5K/F_4 1.5K/F_4 NV suggestion near
HDMI connector
2
R142 4.7K_4 PC0 Q45 SW@BSN20
R143 *4.7K_4 +3V +3V
LS_REXT
PC0 1 3
<17> MXM_DDCCK
R141 *4.7K_4 PC1 PC1
C C
R166 *4.7K_4 DDCBUF_EN from PCH
R165 *4.7K_4 R151 IV@499/F_4 MB_HDMI_DDCCLK R610 IV@0_4 HDMI_DDCCLK_MB
R167 *4.7K_4 CFG Control by pin4 HPDEN_R

R168 *4.7K_4 +5V D11 2 1RB501V-40 C324
<8> INT_HDMI_HPD
*.1u/10V_4
+5V
R150 IV@0_4 HDMI_DDCDATA_SW R444 R140
<8> SDVO_CTRLDAT
SW@1.5K/F_4 1.5K/F_4
2
R149 IV@0_4 HDMI_DDCCLK_SW Q46 SW@BSN20
<8> SDVO_CTRLCLK
Equalization Control
PC0 internal PD <17> MXM_DDCDAT 1 3
PC1 PC0 PC1 internal PD
PIN4 PIN3 EQ Control DDCBUF_EN internal PD R145 IV@2.2K_4
L L 8dB CFG internal PD +3V R146 IV@2.2K_4 MB_HDMI_DDCDATA R611 IV@0_4 HDMI_DDCDATA_MB
L H 4dB DDC_EN internal PU
H L 12dB
H H 0dB C317
*.1u/10V_4
B B
Switchable Graphic HDMI source ESD Protect

EMI HDMI connector
MB_HDMITX2P CN15
C374 SW@0.1u/10V_4_X7R MB_HDMITX0N 20
<17> HDMITX0N SHELL1
C369 SW@0.1u/10V_4_X7R MB_HDMITX0P R156 *100/F_4 MB_HDMITX2P 1
<17> HDMITX0P D2+
2
C367 SW@0.1u/10V_4_X7R MB_HDMITX2N MB_HDMITX2N MB_HDMITX2N D2 Shield
<17> HDMITX2N 3
C355 SW@0.1u/10V_4_X7R MB_HDMITX2P MB_HDMITX1P D2-
4
To MXM <17> HDMITX2P
MB_HDMITX1P 5
D1+
D1 Shield
C352 SW@0.1u/10V_4_X7R MB_HDMITX1P MB_HDMITX1N 6
<17> HDMITX1P D1-
C347 SW@0.1u/10V_4_X7R MB_HDMITX1N R155 *100/F_4 MB_HDMITX0P 7
<17> HDMITX1N D0+
8
C340 SW@0.1u/10V_4_X7R MB_HDMICLK+ MB_HDMITX1N MB_HDMITX0N D0 Shield
<17> HDMICLK+ 9 23
C333 SW@0.1u/10V_4_X7R MB_HDMICLK- MB_HDMICLK+ D0- GND
<17> HDMICLK- 10
MB_HDMITX0P CK+
11 22
MB_HDMICLK- CK Shield GND
12
R445 R446 R447 R449 R450 R451 R452 R453 R158 *100/F_4 +5V CK-
13
SW@499/F_4 SW@499/F_4 SW@499/F_4 SW@499/F_4 CE Remote
14
SW@499/F_4 SW@499/F_4 SW@499/F_4 SW@499/F_4 MB_HDMITX0N F2 HDMI_DDCCLK_MB NC
15
SMD1206P110TFT HDMI_DDCDATA_MB DDC CLK
16
MB_HDMICLK+ D17 SSM22LLPT DDC DATA
2 1 17
3
GND
18
R153 *100/F_4 HDMI_MB_HP +5V
19
Q35 HP DET
21
MB_HDMICLK- SHELL2
+5V 2
R137 HDMI
R448 SW@2N7002E 100K_4
SW@100K_4
1
A A

PROJECT : ZR7B
1A
HDMI (PS8101)
5 4 3 2 1
5 4 3 2 1
Giga-LAN AR8151
+3V_S5 +3V_LAN
R226 *short_6 +3V_LAN

D C448 C447 C450 C451 C449 D
10u/6.3V_8 10u/6.3V_8 1u/6.3V_4 0.1u/10V_4 *1000p/50V_4 U16
1 22 AVDDH C430 0.1u/10V_4

VDD33 AVDDH
2 PERSTn CLKREQn/LED2 23
<4,10,11,28,32,37> PLTRST#
3 24 DVDDL C434 0.1u/10V_4
<8,28> PCIE_WAKE# WAKEn DVDDL
R220 *Short_4 BCM_CLKREQ# 4 25 SMCLK_8151 R227 *0_4
<10> CLK_PCIE_LAN_REQ# CLKREQn SMCLK SMB_CLK_ME0 <10>
C714 0.1u/10V_4 +VDDCT 5 VDDCT
AR8151
5X5mm SMDATA 26 SMDATA_8151 R223 *0_4
SMB_DATA_ME0 <10>
C710 1u/6.3V_4 AVDDL 6 40-Pin QFN 27
AVDDL_REG TESTMODE
C707 0.1u/10V_4 XTLO 7 28 R613 *0_4 AVDDH
XTLO TEST_RST
XTLI 8 29 PCIE_RXN1_LAN_R 0.1u/10V_4_X7R C465
XTLI TX_N PCIE_RX1- <10>
C700 1u/6.3V_4 AVDDH 9 30 PCIE_RXP1_LAN_R 0.1u/10V_4_X7R C466
AVDDH_REG TX_P PCIE_RX1+ <10>
C701 0.1u/10V_4 R205 2.37K/F_4 RBIAS 10 31 AVDDL C453 0.1u/10V_4
RBIAS AVDDL
C C
<27> LAN_TRD0P 11 TRXP0 REFCLK_N 32
CLK_PCIE_LOM# <10>
<27> LAN_TRD0N 12 TRXN0 REFCLK_P 33

CLK_PCIE_LOM <10>
C699 0.1u/10V_4 AVDDL 13 34 AVDDL C454 0.1u/10V_4
NC/AVDDL AVDDL
<27> LAN_TRD1P 14 TRXP1 RX_P 35 PCIE_TX1+ <10>
<27> LAN_TRD1N 15 TRXN1 RX_N 36 PCIE_TX1- <10>

C698 0.1u/10V_4 AVDDH 16 37 DVDDL C455 1u/6.3V_4
NC/AVDDH DVDDL_REG
C435 33p/50V_4 XTLO 17 38 LAN_ACTLED C456 0.1u/10V_4
<27> LAN_TRD2P NC/TRXP2 LED0 LAN_ACTLED <27>
1
18 39 LAN_LINKLED#
<27> LAN_TRD2N NC/TRXN2 LED1 LAN_LINKLED# <27>
1.2H Y1
25MHz C697 0.1u/10V_4 AVDDL 19 40 LX L31 4.7uH/1A_2X2 +VDDCT
NC/AVDDL LX
2
C433 33p/50V_4 XTLI 20 41 C457 C460 C464

<27> LAN_TRD3P NC/TRXP3 GND
21 10u/6.3V_8 0.1u/10V_4 *1000p/50V_4
<27> LAN_TRD3N NC/TRXN3
AR8151
B B
LAN_TRD0P
LAN_TRD1P
LAN_TRD2P
LAN_TRD3P
LAN_TRD0N
LAN_TRD1N
LAN_TRD2N
LAN_TRD3N
R213
R212
R211
R210
R209
R208
R207
R206
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
LAN_N1
LAN_N2
LAN_N3
LAN_N4
C408 C407 C406 C405

A A
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4

PROJECT : ZR7B
1A
GLAN BCM57780
5 4 3 2 1
1 2 3 4 5 6 7 8
L28 +VDDCT
PBY160808T-181Y-N/2A/180ohm_6
C399 C395 C396 C397
A C403 1U/10V_4 A
0.1u/10V_4_X7R 0.1u/10V_4_X7R 0.1u/10V_4_X7R 0.1u/10V_4_X7R
CN16
Close to Transformer pin 1,4,7,10 TRANSFORMER R456 220_8 LAN_ACT_LED_PWR
9 YELLOW_N
<26> LAN_ACTLED 10 YELLOW_P
R454 5.1K_4 14 R203 *0_6
X-TX0P GND2 R171 *0_6
1 0+ GND1 13
U34 X-TX0N 2
X-TX1P 0-
1 TCT1 MCT1 24 3 1+
LAN_TRD0P 2 23 X-TX0P X-TX2P 4
<26> LAN_TRD0P TD1+ MX1+ 2+
LAN_TRD0N 3 22 X-TX0N X-TX2N 5
<26> LAN_TRD0N TD1- MX1- 2-
X-TX1N 6
X-TX3P 1-
4 TCT2 MCT2 21 7 3+
LAN_TRD1P 5 20 X-TX1P X-TX3N 8
<26> LAN_TRD1P TD2+ MX2+ 3-
LAN_TRD1N 6 19 X-TX1N
<26> LAN_TRD1N TD2- MX2-
<26> LAN_LINKLED#
7 18 LAN_LINKLED# 11
LAN_TRD2P TCT3 MCT3 X-TX2P R487 220_8 LAN_LNK_LED_PWR GREEN_N
<26> LAN_TRD2P 8 TD3+ MX3+ 17 +3V_LAN 12 GREEN_P
<26> LAN_TRD2N TD3- MX3- RJ45
B 10 TCT4 MCT4 15 B
LAN_TRD3P 11 14 X-TX3P
<26> LAN_TRD3P TD4+ MX4+
<26> LAN_TRD3N TD4- MX4-
LFE9276A-R
LAN_ACT_LED_PWR
R177 R184 R191 R200
75/F_8 75/F_8 75/F_8 75/F_8 LAN_LINKLED#
Delta LFE9276C-R (DB0ZR1LAN00)
FCE NS892407 (DB0LL1LAN00) C378 C716
Bothhand GST5009B (DB0Z06LAN00) *0.1u//50V_8 *0.1u//50V_8
C390
1500p/3KV_18
C C
D D

PROJECT : ZR7B
1A
LAN Transformer and RJ45
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
MINI-CARD WLAN(MPC)
Check LED signal. (active high or low) +3V +WL_VDD
+3.3V: 1000mA R590 *Short_4 CL_DATA1_WLAN
+3.3Vaux:330mA <10> PCI_RST#
<10> CLK_LPC_DEBUG
R606 *Short_4 CL_CLK1_WLAN H=5.6mm R544 *SHORT0805 +WL_VDD
CN21 LTS_AAA-PCI-046-K01
+1.5V:500mA
51 52 +WL_VDD
R585 *0_4 CL_RST1#_WLAN Reserved +3.3V C776 C778 C772 C774
<10> CL_RST1# 49 Reserved GND 50
R589 *0_4 CL_DATA1_WLAN 47 48 +1.5V 10u/10V_8 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
<10> CL_DATA1 Reserved +1.5V
R594 *0_4 CL_CLK1_WLAN 45 46
<10> CL_CLK1 Reserved LED_WPAN#
43 44 RF_LED#
Reserved LED_WLAN# RF_LED# <33,37>
+WL_VDD 41 42
Reserved LED_WWAN#
39 40
Reserved GND
A 37 38 USBP13+ <10> A
Reserved USB_D+
35 GND USB_D- 36 USBP13- <10>
<10> PCIE_TX6+ 33 PETp0 GND 34
<10> PCIE_TX6- 31 PETn0 SMB_DATA 32
29 30 CLK_SDATA <3,14,15>
GND SMB_CLK CLK_SCLK <3,14,15>
27 GND +1.5V 28 +1.5V
25 26 +1.5V
<10> PCIE_RX6+ PERp0 GND
<10> PCIE_RX6- 23 PERn0 +3.3Vaux 24 +WL_VDD
21 22 PLTRST#
GND PERST#
19 20 RF_EN <37>
UIM_C4 W_DISABLE#
17 18
UIM_C8 GND
A_LFRAME#_R R552 *0_4
Debug
15 GND UIM_VPP 16 LPC_LFRAME# <9,37>
13 14 A_LAD3_R R553 *0_4 C773 C775 C770
<10> CLK_PCH_SRC2 REFCLK+ UIM_RST LPC_LAD3 <9,37>
11 12 A_LAD2_R R554 *0_4 1000p/50V_4 0.1u/10V_4 10u/6.3V_8
<10> CLK_PCH_SRC2# REFCLK- UIM_CLK LPC_LAD2 <9,37>
9 10 A_LAD1_R R555 *0_4
GND UIM_DATA LPC_LAD1 <9,37>
7 8 A_LAD0_R R556 *0_4
<10> PCIE_CLK_REQ2# CLKREQ# UIM_PWR LPC_LAD0 <9,37>
5 6 +1.5V
Reserved +1.5V
3 4
GND
GND
PCIE_WAKE#_R Reserved GND
1 WAKE# +3.3V 2 +WL_VDD
+WL_VDD
53
54
2
Q41 modify 10/19

*DTC144EUA
3 1 PCIE_WAKE#_R
<8,26> PCIE_WAKE#
B
MINI-CARD 3G(MNC)Reserve for JV41-CP B
+1.5V_Mini2_VDD
+3V_Mini2_VDD H=7.0mm
+3V_Mini2_VDD
CN12 3G@LTS_AAA-PCI-049-K01 +1.5V +1.5V_Mini2_VDD +3V_Mini2_VDD
51 R395 *10K_4 Active Low
Reserved +3.3V 52 +3V
R398 *0_8
49
Reserved GND 50
47
Reserved +1.5V 48
1
3G_WAKE_1_R 45 R393 *Short_4 3G_MINI_LED# C605 C204 C208
T32 Reserved LED_WPAN# 46 R397 *0_4
3G_MINI_LED# <33>
C563 C582
43 44
Reserved LED_WLAN# 3G_LED# R394 *Short_4 R396 *0_4 RF_LED# *0.1u/10V_4 *0.47u/10V_6 *10u/6.3V_8 3G@0.1u/10V_4 *10u/6.3V_8
41 LED_WWAN# 42
2
Reserved
39
Reserved GND 40
37
Reserved USB_D+ 38 USBP10+ <10>
35
GND USB_D- 36 USBP10- <10>
33
<10> PCIE_TX2+ PETp0 GND 34 3G_SMDATA
31
<10> PCIE_TX2- PETn0 SMB_DATA 32 3G_SMCLK
29
GND SMB_CLK 30
27
GND +1.5V 28 7/15 modify
<10> PCIE_RX2+ 25 PERp0 GND 26
<10> PCIE_RX2- 23 24
PERn0 +3.3Vaux PLTRST# +3V +3V_Mini2_VDD
21
GND PERST# 22 PLTRST# <4,10,11,26,32,37>
R369 *Short_4
19 UIM_C4 W_DISABLE# 20 3G_EN <37>
17 R77 *0_8
UIM_C8 GND 18 R368 *0_4 RF_EN
1
15 16 UIM_VPP
GND UIM_VPP UIM_RST +3VSUS C612 C607 C576 C562 C578 C558
<10> CLK_PCH_SRC1 13 REFCLK+ UIM_RST 14
11 12 UIM_CLK 3G@10u/6.3V_8 3G@0.1u/10V_4 3G@0.1u/10V_4
<10> CLK_PCH_SRC1#
2
REFCLK- UIM_CLK UIM_DATA R411 3G@0_8 3G@0.1u/10V_4 3G@0.47u/10V_6 3G@10p/50V_4
9 10
GND UIM_DATA UIM_PWR
<10> CLKREQ_3G# 7 CLKREQ# UIM_PWR 8
5 6
Reserved +1.5V
C 3 4 C
GND
GND
3G_WAKE_2_R Reserved GND

T3 1
WAKE# +3.3V
2 A:(10/17)FAE confirm:
3G module need +3VSUS and no need +1.5V and no need SMBUS
53
54
+3V_Mini2_VDD
modify 10/19
ESD1 +3V_Mini2_VDD +3V_Mini2_VDD

*CM1293-04SO
UIM_RST_C 1 6 UIM_VPP
CH1 CH4
4
2
2 5
VN VP RP3
UIM_CLK_C 3 4 UIM_DATA_C
CH2 CH3 Q27 *4.7K_4P2R
2
2
C30 C38 *2N7002E
SIM CARD(RFM)Reserve for JV41-CP
3
1
3G@10p/50V_4 3G@33p/50V_4 3 1 3G_SMDATA
1
1
<3,14,15> CLK_SDATA
R385 *0_4
JSIM1 +3V_Mini2_VDD
UIM_CLK R15 *Short_4 UIM_CLK_C 6 1
R12 *0_4 USBP5-_R 7 CLK(C3) GND(C5) UIM_PWR Q26
<10> USBP5- 2
N/A(C8) VCC(C1)
2
R13 *0_4 USBP5+_R 8 3 UIM_VPP *2N7002E
<10> USBP5+ N/A(C4) VPP(C6)
9 4 UIM_RST_C R10 *Short_4 UIM_RST UIM_PWR C29 3G@27p/50V_4
CT RST(C2) UIM_DATA_C R11 *Short_4 UIM_DATA 3G_SMCLK
10 CD DATA(C7) 5 3 1
<3,14,15> CLK_SCLK
GND
GND
GND
GND
D
2 1 D
C31 3G@1u/10V_6 R373 *0_4
3G@SIM-Conn The value of the capacitor is suggest by Siemens HQ expert.
13
11
12
14
For against 900MHz RF interference. The value of capacitor is 27pF. 7/15 modify
For against 1800MHz RF interference. The value of capacitor is 10pF. UIM_DATA C35 3G@10p/50V_4
SIM CARD SIGNALS 1nF/10nF value capacitor use for against ESD purpose.
ROUTE PARALLEL
UIM_RST C34 3G@27p/50V_4
PROJECT : ZR7B
Closed JSIM1 1A
MINI PCI-E card/TV
1 2 3 4 5 6 7 8
1 2 3 4
EE RETURN-PATH CAPACITORS
MAIN SATA HDD
+5V C516 *.01u/25V_4 VIN
CN18 VIN
23 C630 *.01u/25V_4
GND23
A A
1 C1 0.1u/25V_4_X5R
GND1 SATA_TXP0_C C748 .01u/25V_4 +5V
RXP 2 SATA_TXP0 <9>
3 SATA_TXN0_C C743 .01u/25V_4 SATA_TXN0 <9> C541 0.1u/25V_4_X5R
RXN
GND2 4
5 SATA_RXN0 C737 .01u/25V_4 +3V C506 *.01u/25V_4 VIN C503 *.1u/10V_4 C622 0.1u/25V_4_X5R
TXN SATA_RXN0_C <9>
6 SATA_RXP0 C736 .01u/25V_4
TXP SATA_RXP0_C <9>
7 C756 *.1u/10V_4 C618 0.1u/25V_4_X5R
GND3
+5V_S5 C512 *.1u/10V_4 C693 *.1u/10V_4 C537 0.1u/25V_4_X5R

3.3V 8
9 C511 *.01u/25V_4 C657 *.1u/10V_4 C538 0.1u/25V_4_X5R
3.3V
3.3V 10
11 C504 *.1u/10V_4 C690 0.1u/25V_4_X5R
GND
GND 12
13 C651 *.1u/10V_4 C543 0.1u/25V_4_X5R
GND +5V_HDD
5V 14
15 C694 *.1u/10V_4 C689 0.1u/25V_4_X5R
5V
5V 16
17 C757 *.1u/10V_4 C84 0.1u/25V_4_X5R
GND
RSVD 18
GND 19
B C754 *.01u/25V_4 B
12V 20 +5V +3V
12V 21
12V 22
R482 *SHORT0805+5V_HDD C495 *.1u/10V_4 +3V
+5V
GND24 24
C695 C702 C712 C711 C709 C706
MAIN_SATA +
100u/6.3V_3528 10u/10V_6 *.1u/16V_4 *.1u/16V_4 .01u/25V_4 .01u/25V_4
Q32
ODD (SATA) ODD POWER(ODD) +3VPCU
+5V AO6402A +5V_ODD +5V
6 R439
5 4
2
1
CN14 1 *0_8
14 R359
C GND14 100K_4 C
R119
3
1 +15V 2 1 MOD_EN_5V
GND SATA_TXP1_C C318 .01u/25V_4
2 SATA_TXP1 <9> 100K_4
2
A+
1
3 SATA_TXN1_C C315 .01u/25V_4 SATA_TXN1 <9>
A- C264
GND 4
5 SATA_RXN1 C305 .01u/25V_4
Connect to PCH(GPIO21) pin Y9 0.1u/25V_6
SATA_RXN1_C <9>
2
B-
B+ 6 SATA_RXP1 C302 .01u/25V_4
SATA_RXP1_C <9> and EC pin28(GPIO53) 2
GND 7
3
+5V_ODD Q25
DMN601K-7
8 SATA_DPR440 1K_4
1
DP R363 *Short_4 ODD_EN
5V 9 <37> ODD_POWER 2
5V 10
1
C654 C653 C652 C655 C656 C650 R358 *0_4 Q24
+
MD 11 <9> PCH_ODD_EN
12 DMN601K-7
GND .01u/25V_4 .01u/25V_4 *.1u/16V_4 *.1u/16V_4 10u/10V_6 100u/6.3V_3528 R362
13
1
GND *100K_4
15
2
GND15
SATA_ODD
D D

PROJECT : ZR7B
1A
SATA-HDD/ODD/USB-ESATA
1 2 3 4
5 4 3 2 1
Mute(ADO) +3V +5VA
HP <31> HP-L
reverse R441 R615 R599
<31> HP-R R539 *0_4 ADOGND
*10K_4 1K_4
R532 *Short_4 MIC1-VREFO-L
MIC1-VREFO-L <31>
PD# *BAS316 D20 EAPD#
MIC1-VREFO-R
MIC1-VREFO-R <31>
D ADOGND BAS316 D21 D
AMP_MUTE# <37>
R538 *0_4 MIC1-VREFO-L
C760 10u/6.3V_6 BAS316 D22 PCH_AZ_CODEC_RST#

Codec(ADO) ADOGND
C761
+ Place next to pin 27
2.2u/6.3V_6
C759 C768
C762 ADOGND +5VA
+5VA + 10u/6.3V_6 0.1u/10V_4
Place next to pin 25
2.2u/6.3V_6
C764 C766 C509 C508

10u/6.3V_6 0.1u/10V_4
36
35
34
33
32
31
30
29
28
27
26
25
U39
0.1u/10V_4 10u/6.3V_6
CBP
CPVEE
HP-OUT-L
MIC1-VREFO-L
MIC2-VREFO
LDO-CAP
AVSS1
AVDD1
CBN
HP-OUT-R
MIC1-VREFO-R
VREF
ADOGND ADOGND
ANALOG
Place next to pin 38
Spilt by AGND 37 AVSS2 LINE1-R 24 T77
ADOGND
38 23 T79
AVDD2 LINE1-L
+5V R558 *short_6 +5VPVDD1 39 22 MIC1-R

PVDD1 MIC1-R MIC1-R <31>
C784 C780 C783 C779

<31> L_SPK+ L_SPK+ 40
SPK-L+ MIC1-L
21 MIC1-L
MIC1-L <31>
MIC
<31> L_SPK- L_SPK- 41 20
10u/6.3V_6 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 SPK-L- MONO-OUT
C C
GND_EARTH R566 20K/F_4
42
PVSS1 (Vista Premium Version) JDREF
19 ADOGND
43 18
PVSS2 Sense-B
<31> R_SPK- R_SPK- 44 17
SPK-R- MIC2-R
<31> R_SPK+ R_SPK+ 45 16
SPK-R+ MIC2-L
+5V R581 *short_6 +5VPVDD2 46 15

PVDD2 LINE2-R
GPIO0/DMIC-DATA
EAPD#
GPIO1/DMIC-CLK
47 14
C792 C793 C790 C789 SPDIFO2/EAPD LINE2-L
48 13 SENSEA R578 39.2K/F_4 LINEOUT_JD
SDATA-OUT
SPDIFO Sense A LINEOUT_JD <31>
10u/6.3V_6 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
49 R583 20K/F_4 MIC1_JD
DVDD1
DVSS2
PGND MIC1_JD <31>
SYNC
ANALOG
PD#
Place next to pin 46 Spilt by DGND ALC271X
1
10
11
12
PCBEEP dont coupling any signals if possible
DIGITAL 8/17 separate PCBEEP to Digital from Realtek suggestion
1.6Vrms
<31> SPDIF_OUT +3V
PCBEEP C800 1u/10V_6 BEEP_1 R597 47K/F_4
SPKR <9>
C807 R596
C799 C806 4.7K_4
0.1u/10V_4 10u/6.3V_6 100p/50V_4
B Place next to pin 1 B

R587 *short_6 +3V
<24> DMIC0_1 L58 DMIC0
SBK160808T-301Y-N/0.2A/300ohm_6
<24> DMIC_CLK_1 L57 DMIC_CLK C802 C801
SBK160808T-301Y-N/0.2A/300ohm_6
PCH_AZ_CODEC_RST# <9>
0.1u/10V_4 10u/6.3V_6
EMI request C795
PCH_AZ_CODEC_SYNC <9>
C810 C809
*33p/50V_4 *33p/50V_4 ACZ_SDIN0_R R598 22_4 *100p/50V_4
PCH_AZ_CODEC_SDIN0 <9>
PCH_AZ_CODEC_SDOUT <9>
Place next to pin 9
PD#
PCH_AZ_CODEC_BITCLK <9>
0V : Power down Class D SPK amplifer
3.3V : Power up Class D SPK amplifer C808 *22p/50V_4
Power (ADO)
DIGITAL ANALOG R595 *0_6
+5V L56 UPB201209T-310Y-N/6A/31ohm_8 R603 *0_6
+5VA
U38 GND_EARTH don't coupling AGND and SPK signals
3 4 R493 *short_6
IN OUT
2 R502 *0_6 GND_EARTH R577 *short_6
GND R602 *0_6
A A
1 5 R540 *29.4K/F_4 R490 *0_6 R565 *0_6
SHDN SET R517 *0_6 R571 *0_6
*G923-330T1UF
R534 + C767 C765 C751 *1000p/50V_4
*10K/F_4 C752 *1000p/50V_4
10u/10V_3216 0.1u/10V_4
C755 C763 R317 *short_6
+ R519 **0_4
0.1u/10V_4 10u/10V_3216
ADOGND PROJECT : ZR7B

ADOGND Size Document Number Rev
ADOGND 1A
C730, C787 close U37 pin3 and L65 REALTEK ALC663&888/MDC
5 4 3 2 1
5 4 3 2 1
MIC <30> MIC1-VREFO-R MIC1-VREFO-R

MIC1-VREFO-L Internal Speaker
<30> MIC1-VREFO-L
Normal OPEN Jack
R525 R500
4.7K/F_4 4.7K/F_4
CN19 PINK
1 7
D C753 4.7u/6.3V_6 MIC1_L2 R524 1K/F_4 MIC1_L3 L55 MIC1_L 2 CN7 D
<30> MIC1-L
BLM15AG121SS1/0.5A/120ohm_4 6 <30> R_SPK- R_SPK-R176 *short_6 R_SPK-_1
C746 4.7u/6.3V_6 MIC1_R2 R512 1K/F_4 MIC1_R3 L51 MIC1_R R_SPK+R175 *short_6 R_SPK+_1 1
<30> MIC1-R 3 <30> R_SPK+ 25
BLM15AG121SS1/0.5A/120ohm_4 MIC1_JD 4 <30> L_SPK- L_SPK-R174 *short_6 L_SPK-_1
L_SPK+R173 *short_6 L_SPK+_1 36
<30> MIC1_JD 8 <30> L_SPK+ 4
5
MIC
C731 C758 C381 C382 C380 C379 SPEAKER-CONN
Max. 100mVrms input for Mic-IN 470p/50V_4 470p/50V_4 *0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6
MIC1_JD ADOGND
1
ADOGND
D13
*VPORT_6
ADOGND
C C
HP/SPDIF
CN20
HP_JD 1
2
HP-L R291 56/F_4 HPL-1 L34 BLM15AG121SS1/0.5A/120ohm_4 HPL_SYS 3

<30> HP-L
HP-R R315 56/F_4 HPR-1 L37 BLM15AG121SS1/0.5A/120ohm_4 HPR_SYS 4
<30> HP-R
ADOGND 5
R319 R290 C515 C505 7

+3V_SPD LED
8 Drive
*1K_4 *1K_4 2200p/50V_4 2200p/50V_4 6 IC
SPDIF_BLACK
ADOGND
B B
SPDIF_OUT L39 BLM15AG121SS1/0.5A/120ohm_4 SPDIF_OUT_R

<30> SPDIF_OUT
+5VA
+3V_SPD
+3V 1 3 LINEOUT_JD LINEOUT_JD <30>

R300
3
Q43 C510 +5VA

ME2347 10K_4
2
0.22u/6.3V_4 HP_JD
LINE_JD# 2
R320 Q40
3
1
ADOGND
20K_4 2N7002ESPT D19
1
A HP_JD 2 *VPORT_6 A
2
Q42
2N7002ESPT ADOGND
ADOGND Quanta Computer Inc.
1
ADOGND PROJECT : ZR7B

1A
AMP /AUDIO JACK CONN
5 4 3 2 1
A B C D E
CN9
4 IN 1 CARD READER (MMC)
XD_RDY 1 20 MS_DATA1
CARD READER Controller XD_RE#
XD_CE#
XD_CLE
2
3
XD-R/B
XD-RE
XD-CE
MS-DATA1
MS-BS
4IN1-GND2
21
22
MS_BS
VCC_XD
4 XD-CLE SD-VCC 23 VCC_XD
XD_ALE 5 24 SD_CLK
XD_WE# XD-ALE SD-CLK SD_DAT0
6 XD-WE SD-DAT0 25
XD_WP# 7 26 XD_D2
XD_D0 XD-WP XD-D2 XD_D3
8 XD-D0 XD-D3 27
4 XD_D1 DATA4 4
9 XD-D1 XD-D4 28
SD_DAT2 10 29 SD_DAT1
SD_DAT3 SD-DAT2 SD-DAT1 DATA5
11 SD-DAT3 XD-D5 30
SD_CMD 12 31 DATA6
SD-CMD XD-D6 DATA7
13 4IN1-GND1 XD-D7 32
VCC_XD 14 MS-VCC XD-VCC 33
MS_SCLK 15 34 XD_CD#
MS_DATA3 MS-SCLK XD-CD-SW SD_WP
16 MS-DATA3 SD-WP-SW 35
MS_INS# 17 36 SD_CD#
MS_DATA2 MS-INS SD-CD-SW
18 MS-DATA2
MS_DATA0 19 MS-DATA0 VCC_XD
SHIELD1-GND 37
38 R496 C738 C740
SHIELD2-GND
SHIELD3-GND 41
*5.1K_4 4.7u/10V_6 0.1u/16V_4
CONN_CARDREADER modify for ESD
Close to CN14 pin 14 & pin23

+1.8V_VDD
C743 close PIN46, 47 4.7u CAP close to pin23
C708 close PIN48, 47
+3V_VDD T76
T78
R548 *Short_4 XTALSEL C513 C514
Main DFHD36MS006 SD_DAT0
3 Clock input selection 0.1u/16V_4 0.1u/16V_4 3
XTALSEL
CRMD_N
DATA0 MS_DATA0
'1' for 48MHz input [Default]
DATA1
DATA0
DATA7
DATA6
CTRL1
CTRL3
NBMD
'0' for 12MHz input Second DFHD36MS012 XD_D0
8/14 ZH7 remove R136, R591 and C775 SD_DAT1
R549 *100K_4 DATA1 MS_DATA1
48
47
46
45
44
43
42
41
40
39
38
37
+3V_VDD U40
R550 *Short_4
<4,10,11,26,28,37> PLTRST#
CTRL0, CRTL 1 trace length shorter , XD_D1
GND
VDD
NBMD
VDDHM
TRIST
XTALSEL
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6
C777 *0.47u/10V_6 and surround with GND.
SD_DAT2
+3V R545 *short_6 +3V_VDD
C769 1 36 CTRL0 DATA2 MS_DATA2
GPON7 CTRL0 DATA5
2 EXT48IN DATA5 35
4.7u/10V_6 3 34 CTRL2 XD_D2
R567 330_4 RSTN CTRL2 GPI4
4 REXT GPI4 33
5 32 DATA4 T80 SD_DAT3
VD33P DATA4 DATA3
<10> USBP12+ 6 DP DATA3 31
7 AU6437-GBL 30 DATA2 DATA3 MS_DATA3
<10> USBP12- DM DATA2
8 29 XD_WP#
C791 C794 XI VS33P XDWPN GPI2 XD_D3
9 XI GPI2 28
XO 10 27 XD_CE# T81
*5p/50V_4 *5p/50V_4 XO XDCEN EEPDATA
+1.8V_VDD 11 VDD EEPDATA 26
GPI1 T82
8/14 C707 close PIN11, 12
12 VDD GPI1 25
T83
Close to connector
SDWPEN
AGND5V
EEPCLK
CF_V33
VDDHM
XDCDN
VCC33
CTRL4
R494 SD_CLK
GND
VDD
V18
V33
2 BLM15AG121SS1/0.5A/120ohm_4 2
CTRL0 XD_ALE
C735
13
14
15
16
17
18
19
20
21
22
23
24
MS_BS *10p/50V_4
crystal trace width needs at least 10 mils.
EEPCLK T84 SD_WP
C804
VCC_XD
8/14 pin13 output 20mils

C797 18p/50V_4 XI CTRL1 XD_CLE
4.7u/10V_6
R520 MS_SCLK
Y7 R584 BLM15AG121SS1/0.5A/120ohm_4
12MHz 270K_4 SD_CMD
*0_4 R604 C749
VCC_XD
C803 18p/50V_4 XO XD_CD# CTRL2 XD_RDY *10p/50V_4

CTRL4 SD write protect
+1.8V_VDD 1:decided by SDWP[Default] SD_CD#
0:letting SD always
+3V_VDD CTRL3 XD_WE#
+3V_VDD write-able
C811 C812 MS_INS#
4.7u/10V_6 0.1u/16V_4 CTRL4 XD_RE#
1 1

PROJECT : ZR7B
1A
AU6433 CardReader
A B C D E
5 4 3 2 1
LED
POWER BOARD CONN(UIF)
+3V_S5
D D
POWER Amber
PWRLED# LED1
<37> SUSLED# <37> PWRLED#
R329 90.9/F_4 4 2
<37> SUSLED#
+3V_S5
R328 37.4/F_4 3 1
<37> PWRLED#
1
+3VPCU +3V_S5 LED_A/B
Blue
1
2
PIPE LED will flash while R332 *1M_4
battery insert at C-test +3VPCU
R347
1
SUSLED# 2 Q22 R333 *1M_4
*100K/F_6 BSS84 +3VPCU
3
Q23 Battery
2 *BSS84 +3V Amber
<37> ACPRN POWER/B LED2
3
12 R331 90.9/F_4 4 2
<37> BATLED1#
Q21 PWR_LED 11 14
*BSS84 SUS_LED 10 13 R330 37.4/F_4 3 1
<37> BATLED0#
3
C PIPE_LED C
9
D2 BAS316 8 LED_A/B
<37> NBSWON#
7
<37> NUMLED# 6
5
Blue
<37> CAPSLED#
SATA_LED#_R 4
3 RF_LED_EN# +3V
2
2
+3V 1 Q47
CN1 3 1
BSS84
R9
<28,37> RF_LED# Amber
5
10K/F_4 1 LED3
4 SATA_LED#_R R642 *0_4 R335 90.9/F_4 4 2 R643 *0_4
<37> RF_LED_EN#
<9> SATA_ACT# 2
U22 <28> 3G_MINI_LED# R334 37.4/F_4 3 1
3
*TC7SH08FU
LED_A/B
R14 *Short_4
B B
Blue
SW /B
+3V +3V
CN3
1 +3V
R87 330_4 P_SAVE_LED 1
1 3 2
2
<37> ODD_EJ 3
3 C227
<37> POWER_SAVE 4
Q4 4 7
5 7
2
BSS84 5 8 0.1u/10V_4
<37> P_SAVE_LED# 6 8
R607 R608 6
A A
SW/LED
100K_4 100K_4
PROJECT : ZR7B
11/3 modify Size Document Number Rev
1A
POWER/MMB/LAUNCH/LED
5 4 3 2 1
5 4 3 2 1
USB +5V_S5
C471
U17
1U/6.3V_4 2 8 USBPWR1
3
IN1
IN2
OUT3
OUT2 7 BLUETOOTH CONNECTOR
6 C719 C715
D OUT1 + D
4 EN#
<37> USBON# 1000p/50V_4 11/13 modify
1 GND
OC# 5
330u/6.3V_6X5.7 CN8
G547F2P81U +3V_S5 1 3 BT_POWER
5
Q13 USBP4+_R 4
<10> USB_OC0# + C400 3
C402 USBP4-_R
2
AO3413 1000p/50V_4 BT_LED 2 7
CN17 2.2u/6.3V_6 T54 1 6
1 1 8 8 <37> BT_POWERON#
USBP1-_R 2 7 BT_CONN
USBP1+_R 2 7
3 3 6 6
4 5 R199 *Short_4 C401
4 5 *.01u/16V_4
R230 *0_4 USB_MB_Turbo L27
3 4 USBP4+_R
<10> USBP4+ 3 4
L32 2 1 USBP4-_R
<10> USBP4- 2 1
2 1 USBP1-_R
<10> USBP1- 2 1
1
3 4 USBP1+_R *RFCMF1632100M3T/200mA/90ohm
<10> USBP1+ 3 4 RV2 RV1 R198 *Short_4
DLW21HN900SQ2L/300mA/90ohm
R229 *0_4 *EGA-0402 *EGA-0402
2
C C
USB/B
R321 *0_4 +5V_S5 CN10
L38 1
<10> USBP3- 2 1 USBP3-_R 2
2 1 USBP3+_R
<10> USBP3+ 3 3 4 4 3
4
DLW21HN900SQ2L/300mA/90ohm 5
R324 *0_4 6
7
8
B R316 *0_4 9 B
<37> USBON#
<10> USB_OC1# 10
L36 11
<10> USB_OC4_5#
2 1 USBP9-_R +3VPCU 12
<10> USBP9- 2 1
3 4 USBP9+_R 13
<10> USBP9+ 3 4 <24,37> LID591#
14
DLW21HN900SQ2L/300mA/90ohm 15
R314 *0_4 USBP3-_R 16
USBP3+_R 17
18
R306 *0_4 USBP9-_R 19
USBP9+_R 20
L35 21
2 1 USBP11-_R USBP11-_R 22
<10> USBP11- 2 1
3 4 USBP11+_R USBP11+_R 23
<10> USBP11+ 3 4
24
DLW21HN900SQ2L/300mA/90ohm
R297 *0_4
Aces 88501-240N
R230, R229, R321, R324, R316, R314, R306, R297

A A

PROJECT : ZR7B
1A
USB/ BT
5 4 3 2 1
5 4 3 2 1
K/B CN2 CPU FAN

MY0 1
<37> MY0
7 8 MX2 MY1 2
<37> MY1
5 6 MX3 MY2 3
<37> MY2
3 4 MX4 MY3 4
<37> MY3
1 2 MX5 MY4 5
<37> MY4 +5V +5V
CP6 *100p/50Vx4 MY5 6 +3V +3V +3V
<37> MY5
7 8 MX6 MY6 7
<37> MY6
5 6 MX7 MY7 8
D <37> MY7 D
3 4 MY17 MY8 9
<37> MY8
1 2 MY16 MY9 10 R378 R374 R370 R371
<37> MY9
CP5 *100p/50Vx4 MY10 11
<37> MY10
7 8 MY3 MY11 12 10K_4 10K_4 10K_4 10K_4
<37> MY11
5 6 MY2 MY12 13
<37> MY12
3 4 MY1 MY13 14 R372
<37> MY13
1 2 MY0 MY14 15 FAN_PWM_E
<37> MY14
CP1 *100p/50Vx4 MY15 16 *10K_4 CN11
<37> MY15 <37> FANSIG
7 8 MY7 MY16 17
<37> MY16 1
2
5 6 MY6 MY17 18
<37> MY17 2
3
3 4 MY5 MX7 19
<37> MX7 3
1 2 MY4 MX6 20 2 Q29 1 3 FAN_PWM_CN
<37> MX6 <10,11,37> SML1ALERT# 4
CP2 *100p/50Vx4 MX5 21 MMBT3904
<37> MX5
7 8 MY11 MX4 22 Q28 30mil FAN
<37> MX4
1
5 6 MY10 MX3 23 MMBT3904
<37> MX3
3 4 MY9 MX2 24 27
<37> MX2 <37> CPUFAN#
1 2 MY8 MX1 25 28
<37> MX1
CP3 *100p/50Vx4 MX0 26
<37> MX0
7 8 MY15
5 6 MY14 KB
3 4 MY13 +3VPCU
1 2 MY12
CP4 *100p/50Vx4
C
C549 *100p/50V_4 MX1
MX0
RP2 10K_10P8R TOUCHPAD & Switch CONN. C
C550 *100p/50V_4 10 1 MX3
MX4 9 2 MX2
MX5 8 3 MX1
MX6 7 4 MX0
MX7 6 5 +5V +5V
L24 *SHORT0805 +TPVDD
C283
H-C157D63PT R136 R135 0.1u/10V_4_X7R

10K_4 10K_4
HOLE2 HOLE1 HOLE7 HOLE30 HOLE31 HOLE28 HOLE22 CN6
*HG-C315D110P2 *HG-C315D110P2 *O-ZR7-1 *H-C91D91N *Hg-c276d110p2 *h-c157d79pt *h-c157d102pt 1
7 6 7 6 7 6 7 6 L25 *short_6 2
<37> TPDATA
8 5 8 5 8 5 8 5 TPDATA_R 3
9 4 9 4 9 4 9 4 L23 *short_6 TPCLK_R 4
<37> TPCLK
5
C293 C291 6
1
2
3
1
2
3
1
2
3
1
2
3
1
RIGHT# 7
*.01u/25V_4 8
*.01u/25V_4 9
HOLE17 HOLE21 HOLE24 HOLE25 HOLE3 10 13
B *h-c236d142p2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 HOLE20 HOLE19 11 14 B
7 6 7 6 7 6 7 6 7 6 *hg-c315d110p2 *H-C91D91N LEFT# 12
8 5 8 5 8 5 8 5 8 5 7 6
9 4 9 4 9 4 9 4 9 4 8 5 Aces 88501-120N
9 4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
SW3 SW2
H-C236D157PB RIGHT# 3 2 LEFT# 3 2
HOLE16 HOLE15 HOLE29 HOLE12 HOLE26 HOLE6 HOLE27 HOLE9 1 4 1 4
*H-C236D157PB *H-C236D157PB *hg-c236d110p2 *hg-c355d110p2 *hg-c394d110p2 *h-c276d110p2 *h-c236d161pb *h-c236d142pb
7 6 7 6 7 6 SWITCH_1.5 SWITCH_1.5
8 5 8 5 8 5
9 4 9 4 9 4
1
1
2
3
1
2
3
1
2
3
H-C197D122PB h-c236d118p2 H-C236D142PB

HOLE4 HOLE5 HOLE8 HOLE18 HOLE23 HOLE14 HOLE13 HOLE10 HOLE11
A *H-C197D122PB *H-C197D122PB *H-C197D122PB *H-C236D161PB *H-C236D161PB *H-C236D142PB *H-C236D142PB *H-C236D142PB *H-C236D142PB A

1
PROJECT : ZR7B
1A
KB/FAN/TP+FP
5 4 3 2 1
1 2 3 4 5 6 7 8
EMI decoupling
VIN VIN_SRC
+0.75V_DDR_VTT +1.5V_CPUVDDQ
<38> CSOP_1
C813 C814 C815 C821 C817
10u/25V_1206 10u/25V_1206 *10u/25V_1206*10u/25V_1206 *10u/25V_1206 PR85 PR86
A +3V A
22_8 220_8
C822
C828 10u/25V_1206
C823 C824 C825 C826 C827 2200p/50V_4
3
*1u/25V_6 *1u/25V_6 *1u/25V_6 *1u/25V_6 *1u/25V_6
<47> MAINON_DIS_G 2 <47> MAINON_DIS_G 2
PQ21 PQ20
<38> VDC DMN601K-7 DMN601K-7
1
C816
EC1 EC2 C818 C819 C820 10u/25V_1206
22u/25V_1210 22u/25V_1210 10u/25V_1206 10u/25V_1206 10u/25V_1206
C330 *.1u_4
C321 *.1u_4
+1.5V_SUS +1.5V_CPUVDDQ
C319 *.1u_4
C316 *.1u_4
B B
+3V_S5
+3V_S5 +1.5V_SUS
R108
R323
5
*10K/F_4 U19 *1K_4

R318 2 R546
DDR3_DRAMRST# <14,15>
*10K/F_4 4 PM_DRAM_PWRGD <4,8>
3
3
1 Q9
Q17 *1.5K/F_4
+1.5V_CPUVDDQ *2N7002E *TC7SH08FU
3
2 R547 <11> RST_GATE# 2

*750/F_4 R107
3
*Short_4
*BSS138
2 Q16
1
1
*PDTC143TT
PWRGD_1.5VCPU <43> <4> CPU_DDR3_DRAMRST#

1
C C
+1.5V_SUS +1.5V_SUS
+1.5V_SUS
R126 R118
*1K/F_4 *1K/F_4
PQ12
1
2
5
6
R154 R152
+SMDDR_VREF_DQ0 <14> +SMDDR_VREF_DQ1 <15>
*AO6402A
3
<39,43,47> MAIND 3
Q12 Q11 *SHORT1206
*SHORT1206
R124 R117
RST_GATE#_R 2 *1K/F_4 RST_GATE#_R 2 *1K/F_4
4
+1.5V_CPUVDDQ
*A03402 *A03402
6A/maximum
1
<7,14> VREF_DQ_DIMM0 <7,15> VREF_DQ_DIMM1

D D

PROJECT : ZR7B
1A
S3 power saving
1 2 3 4 5 6 7 8
5 4 3 2 1
EC(KBC) L45 PBY160808T-250Y-N/3A/25ohm_6 +A3VPCU

+3V
I/O ADDRESS SETTING(KBC)
C596 C597
30mil
0.1u/10V_4_X7R
10u/10V_6
+3VPCU E775AGND
R54 2.2_6 D15 C560 C561
1 2 +3VPCU_EC 0.03A(30mils)
BAS316 4.7U/6.3V_6 0.1u/10V_4_X7R
C590 C586 C199 C200 C584 C567
115
102
19
46
76
88
4
4.7U/6.3V_6 0.1u/10V_4_X7R
*.1u/16V_4 0.1u/10V_4_X7R
*.1u/16V_4 0.1u/10V_4_X7R U25
AVCC
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
E775AGND C606 10u/6.3V_8 ICMNT SHBM=0: Enable shared memory with host BIOS
D D
C603 0.01u/16V_4
<9,28> LPC_LFRAME# 3 LFRAME GPIO90/AD0 97 TEMP_MBAT <38>
126 98 WL_SW T22
<9,28> LPC_LAD0 LAD0 GPIO91/AD1
127 99 SHBM SHBM_R R407 10K_4
<9,28> LPC_LAD1 LAD1 GPIO92/AD2 SML1ALERT# <10,11,35>
<9,28> LPC_LAD2 128 LAD2 A/D GPIO93/AD3 100 ICMNT <38>
<9,28> LPC_LAD3 1 LAD3 GPIO05 108
CLK_PCI_775 CLK_PCI_775 2 96 R645 *0_4 1/13 Comfirm by vendor mail :
<10> CLK_PCI_775 LCLK GPIO04 VGA_THERM# <23>
Disabled ('1') if using FWH device on LPC.
<8> CLKRUN# 8 GPIO11/CLKRUN
101
Enabled ('0') if using SPI flash for both system BIOS and EC firmware
GPIO94/DA0 POWER_SAVE <33>
R366 121 105
<11> SIO_A20GATE GPIO85/GA20 GPI95/DA1
*22_4
D/A GPI96/DA2 106
<11> SIO_RCIN# 122 KBRST/GPIO86 GPI97 107
<11> SIO_EXT_SCI#
D16 BAS316 29
ECSCI/GPIO54 LPC SM BUS PU(KBC) +3VPCU
64 ACIN <38>
C568 EC_FPBACK# GPIO01/TB2
<24> EC_FPBACK# 6 95 NBSWON# <33>
GPIO24/LDRQ GPIO03 MBCLK R72 10K_4
*10p/50V_4 93 LID591# <24,34>
NOCIR# GPIO06/IOX_DOUT MBDATA R73 10K_4
T7 124 94 SUSB# <8>
GPIO10/LPCPD GPIO07
119 MXM_SMCLK12 <23>
PLTRST# GPIO23/SCL3 +3V_D_S
<4,10,11,26,28,32> PLTRST# 7 109 ACPRN <33>
LREST GPIO30/CIRTX2 MXM_SMCLK12 R380 2.2K_4
120 MXM_SMDATA12 <23>
USBON# GPIO31/SDA3 MXM_SMDATA12 R376 2.2K_4
<34> USBON# 123 65 BATLED0# <33>
GPIO67/PWUREQ GPIO32/D_PWM
GPIO33/H_PWM 66 BATLED1# <33>
IRQ_SERIRQ 125 15 +3V
<9> IRQ_SERIRQ SERIRQ GPIO36 VRON <40>
16 SUSLED# <33>
GPIO40/F_PWM AC_OFF ODD_EJ R406 *10K_4
<11> SIO_EXT_SMI# 9 17 T60
GPIO65/SMI GPIO42/TCK 2ND_MBCLK R85 10K_4
GPIO GPIO43/TMS
20
3G_SW
AMP_MUTE# <30>
2ND_MBDATA R84 10K_4
21 T6
MX0 GPIO44/TDI
<35> MX0 54 22 CPUFAN# <35>
MX1 KBSIN0 GPIO45/E_PWM PANEL_COLOR ODD_POWER R364 10K_4
<35> MX1 55 KBSIN1 GPIO46/CIRRXM/TRST 23 PANEL_COLOR <24>
MX2 56 24
<35> MX2 KBSIN2 GPO47/SCL4 VIN_ON <38>
MX3 57 25
C <35> MX3 KBSIN3 GPIO50/TDO D/C# <38> C
MX4 58 26
<35> MX4 KBSIN4 GPIO51 S5_ON <39,48>
MX5 59 27
<35>
<35>
MX5
MX6
MX6
MX7
60
KBSIN5
KBSIN6
GPIO52/CIRTX2/RDY
GPIO53/SDA4 28
HDMI_HPD_EC# <25>
ODD_POWER <29>
ACER ID(KBC)
<35> MX7 61 KBSIN7 GPIO81 91 DNBSWON# <8>
GPO82/TEST 110 T16
MY0 53 112
<35> MY0 KBSOUT0/JENK GPO84/TRIST 10/27 modify RF_LED_EN# <33>
MY1 52 80 PANEL_ENG
<35> MY1 KBSOUT1/TCK GPIO41 PANEL_ENG <24>
MY2 51
<35> MY2 KBSOUT2/TMS
MY3 50
<35> MY3 KBSOUT3/TDI
MY4 49 KB 31 ODDLED T61
<35> MY4 KBSOUT4/JEN0 GPIO56/TA1
MY5 48 117
<35> MY5 KBSOUT5/TDO GPIO20/TA2/IOX_DIN SUSON <39,43>
MY6 47 63
<35> MY6 KBSOUT6/RDY GPIO14/TB1 FANSIG <35>
MY7 43
<35> MY7 KBSOUT7
MY8 42 TIMER 32
<35> MY8 KBSOUT8 GPIO15/A_PWM CONTRAST <24>
MY9 41 118
<35> MY9 KBSOUT9/SDP_VIS GPIO21/B_PWM NUMLED# <33>
MY10 40 62
<35> MY10 KBSOUT10/P80_CLK GPIO13/C_PWM PWRLED# <33>
MY11 39 81
<35> MY11 KBSOUT11/P80_DAT GPIO66/G_PWM CAPSLED# <33>
MY12 38
<35> MY12 KBSOUT12/GPIO64
MY13 37
<35>
<35>
MY13
MY14
MY14
MY15
36
KBSOUT13/GPIO63
KBSOUT14/GPIO62 GPIO77/SPI_DI
84
SHBM_R
ODD_EJ <33>
SPI FLASH(KBC) +3VPCU
<35> MY15
MY16
35
KBSOUT15/GPIO61/XOR_OUT SPI GPO76/SPI_DO/SHBM
83
RF_LED_R R542 *0_4
3G_EN <28>
U28
<35> MY16 34 82 RF_LED# <28,33>
MY17 GPIO60/KBSOUT16 GPIO75/SPI_SCK 10/27 modify SPI_SDI_uR R420 22_4 SPI_SDI_uR_R
<35> MY17 33 2 8
GPIO57/KBSOUT17 SO VDD
75 RSMRST#_uR R402 *Short_4 R425 *100K_4 SPI_SDO_uR 5 7 C191
GPIO72/IRRX1/SIN2 ICH_RSMRST# <8> SI HOLD
MBCLK 70 73
<38> MBCLK GPIO17/SCL1 GPIO70/IRRX2_IRSL0 SUSC# <8> 7/24 modify
MBDATA 69 74 PWROK_EC_uR R83 *Short_4 SPI_SCK_uR 6 3 0.1u/10V_4
<38> MBDATA GPIO22/SDA1 GPIO71/IRTX/SOUT2 PWROK_EC <8> SCK WP
<10> 2ND_MBCLK 2ND_MBCLK 67 SMB IR 113
GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR RF_EN <28>
<10> 2ND_MBDATA 2ND_MBDATA 68 14 CIRR_X2 T59 +3VPCU R429 10K_4 SPI_CS0#_uR 1 4
GPIO74/SDA2 GPIO34/CIRRXL HWPG CE VSS
114
GPIO16/CIRTX P_SAVE_LED# W25X40BVSSIG
111 P_SAVE_LED# <33>
TPCLK GPO83/SOUT_CR/XORTR
<35> TPCLK 72 GPIO37/PSCLK1
TPDATA 71 1/13 Comfirm by vendor mail :
<35> TPDATA GPIO35/PSDAT1
B PCH_ACIN 10 86 SPI_SDI_uR If the Southbridge enables 'Long Wait Abort' by B
<8> PCH_ACIN GPIO26/PSCLK2 F_SDI
11 PS/2 87 SPI_SDO_uR_R R404 22_4 SPI_SDO_uR
<34> BT_POWERON# GPIO27PSDAT2 F_SDO default, the flash device should be 50MHz (or faster)
12 FIU 90 SPI_CS0#_uR
<41,42,43,47> MAINON GPIO25/PSCLK3 F_CS0
T62 MAINOND 13 92 SPI_SCK_uR_R R403 22_4 SPI_SCK_uR
GPIO12/PSDAT3 F_SCK
<8> ICH_SUSCLK R400 *Short_4 E775_32KX1 77 30 ECDB_CLOCK T58
GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN +3V
VCC_POR
85 VCC_POR# R405 47K/F_4 +3VPCU HWPG(KBC)
VCORF
AGND
GND1
GND2
GND3
GND4
GND5
GND6
R399 *20M_6 E775_32KX2 79 104 VREF_uR R388 *Short_4 +A3VPCU R381

GPIO02 VREF
R412 NPCE781 10K_4

5
18
45
78
89
116
103
VCORF_uR 44
D4 BAS316 HWPG
Y2 *33K/F_4 SM BUS ARRANGEMENT TABLE <41> HWPG_VTT
1 4 D9 BAS316
<47> HWPG_1.8V
SM Bus 1 Battery R387
L44 PBY160808T-250Y-N/3A/25ohm_6 D7 BAS316 *Short_4
<42> HWPG_1.05V
C608 *32.768KHz C616 C580 SM Bus 2 PCH D8 BAS316
<43> HWPG_1.5V
*15p/50V_4 *15p/50V_4
MPWROK <4>
1u/6.3V_4 D6 BAS316
<39> SYS_HWPG
E775AGND E775AGND SM Bus 3 MMB3 and EEPROM
D5 BAS316
<46> HWPG_GFX
SM Bus 4 HDMI Controller, MMB1, MMB2 and VGA Thermal
POWER-ON Switch(KBC) INTERNAL KEYBOARD STRIP SET(KBC)

A A
+3VPCU
SW1
*MSK:NTCQ31-AB1G-A160T MY0 R60 10K_4
NBSWON# 1 2
3 4
2
5
D1 6
*VPORT_6 Quanta Computer Inc.
1
PROJECT : ZR7B
1A
WPCE781 & FLASH
5 4 3 2 1
5 4 3 2 1
VA PD4 PR130
VDC <36> PQ29 VIN_SRC PQ33
PL4 SBR1045SP5-13 0.01/F_7520
PJ2 UPB201212T-800Y-N/5A/80ohm_8 1 FDD6685 FDD6685
1 VDC 3 VA1 3 4 1 2 3 4 BAT-V
2 2
3
4
1
1
PC124 PC117 PC116 PC113 PR126 PC15 PC13 PR134
POWER_JACK 2200p/50V_6 PL5 0.1u/50V_6 0.1u/50V_6 PD5 0.1u/50V_6 220K/F_6 0.1u/50V_6 2200p/50V_6 33K_6
UPB201212T-800Y-N/5A/80ohm_8 SMAJ20A VIN_SRC
9/1 modify
2
D PC123 PC120 CSIP_1 D
0.1u/50V_6 0.1u/50V_6 1 6 PR137
10K_6
PD1 PR121 2 5
SW1010CPT 220K/F_6
3 4
3
PQ30
IMD2AT108
<37> D/C# 2
PQ36
DMN601K-7
1
VIN_SRC VIN_SRC
CSIP_1 PC32
1u/16V_6
PR40 PR39
10/F_6 10/F_6
PR34 PC24
PC34 4.7_6 PC26 10u/25V_1206
0.1u/50V_6 1u/16V_6
PC129
CSIP CSIN 0.1u/50V_6
PD6 PC130
33
32
31
30
28
27
26
21
C C
1
+3VPCU PC31 +3VPCU *RB500V-40 2200p/50V_6
5
6
7
8
PU2 0.1u/50V_6
CSSP
VDDP
NC
GND
GND
GND
GND
CSSN
VCC
CM1293A-04SO
1 6 MBDATA PR38 PC29
CH1 CH4 2.7_6 0.1u/50V_8 88731_DH 4
2 5 PR37 MBDATA 11 25
VN VP +3VPCU VDDSMB BOOT
100K/F_6 PQ5
TEMP_MBAT 3 4 MBCLK AO4468 0.01_3720
CH2 CH3 MBCLK 9 SDA UGATE 24 PR138
PL6
6.8uH
3
2
1
10 23 88731_LX 1 2 BAT-V
<37> ACIN SCL PHASE
5
6
7
8
13 ACOK LGATE 20
PR21
PC28 88731_DL 4 2.2_6 PC7
PR35 0.1u/50V_6 19 0.01u/50V_6
PR9 49.9/F_6 PGND
*Short_6 DCIN 22 DCIN PU3 PR32 PQ4 PC18
PR43 ISL88731A 10/F_6 AO4710 2200p/50V_6 PC111
82.5K/F_6 18 CSOP CSOP_1
CSOP_1 <36>
2200p/50V_6
3
2
1
CSOP PC8 PC112
2 ACIN
PC110 10u/25V_1206 10u/25V_1206
0.1u/50V_6 PC27
2 1 PR42 3 0.1u/50V_6
VREF
B
22K/F_6
CSON 17 CSON BAT-V
B
PC109 4 PR33 CSOP_1 VIN_SRC VIN

100p/50V_6 ICOMP 10/F_6 PQ26
NC 16
BAT-V AOL1413
5 PR36 1
UPB201212T-800Y-N/5A/80ohm_8 NC SHORT_PAD_4 2 5
PJ1 PL2 15 BAT-V 3
MBAT+ BAT-V VBF
10 1 6 VCOMP
29 PR12
2 GND 100_4
GND
4
3
ICM
PL1 PC232 PR17
NC
NC
4 UPB201212T-800Y-N/5A/80ohm_8 1u/25V_6 150K_6
5 PD3 7
14
12
6 RB500V-40
7 PR41
9 8 TEMP_MBAT 2.21K/F_6
TEMP_MBAT <37>
Batt_Conn PR13
PC5 PC6 *0_6 reserve 0.1u cap PR18
10/1 modify 47p/50V_6 47p/50V_6 39K_6
ICMNT <37>
PC38
+3VPCU
0.01u/50V_6
3
PR19
100K/F_6
2
PR10 PR11 PC35

100_4 100_4 *1u/16V_6 PC37 2
<37> VIN_ON
PC36 *0.01u/50V_6
1
MBCLK <37> 0.01u/50V_6 PQ3

DMN601K-7
A A
1
MBDATA <37>
PC33
3300p/50V_4

1
PR20 PC14
*100K/F_6 0.01u/50V_6
PROJECT : ZR7
2

1A
CHARGER (ISL88731)
5 4 3 2 1
5 4 3 2 1
MAIND
MAIND <36,43,47>
PR105 SHORT_PAD_4 VL
<4,48> SYS_SHDN#
VIN_SRC
1
D D
PR243 VIN_SRC
39.2K/F_4 VL
Add 100u cap
PC215 PC218
2
+ 0.1u/50V_6 10u/25V_1206 PC199
2
3V5V_EN 4.7u/10V_8
PR107
PC214 PC102 SHORT_PAD_4
1
2200p/50V_6 10u/25V_1206 PR239
PR251 PR252 SHORT_PAD_4
1
SHORT_PAD_4 SHORT_PAD_4
PC223 PR102 PC92 PR106 PC101 PC98
390K_4 PC198 1u/16V_6 *0_4 0.1u/50V_6 10u/25V_1206
2
5V_EN
3V_EN
100u/25V_6X5.7 0.1u/50V_6 PC95
5
6
7
8
PC197 2200p/50V_4
OCP:10A
2
0.01u/16V_4 PC94 OCP : 8A
0.1u/50V_6
1
REF +3VPCU
L(ripple current) 4
1
3V_DH PQ70
=(19-5)*5/(2.2u*0.4M*19)
8
7
6
5
OCP: 10A PR103 *0_6 AO4468
~4.18A PR101
+5VPCU 150K_4
8
7
6
5
4
3
2
1
Iocp=10-(4.18/2)=7.91A 4 5V_DH
PL15
LDOREFIN
LDO
VIN
NC
ONLDO
VCC
TON
REF
3
2
1
Vth=7.91A*14.2mOhm=112.322mV 2.2uH_14A
R(Ilim)=(112.322mV*10)/5uA PQ68
AO4468 PR110 3V_LX
~220K
5
6
7
8
1
+5VPCU 9 32 REFIN2 182K/F_6
PL16 BYP REFIN2 PR114 change to 330u/6.3V_6x5.7
10 31 1 2
1
2
3
2.2uH_14A OUT1 ILIM2
C 11 FB1 OUT2 30 *2.2_6 C
5V_LX 1 2 12 PU11 29 SKIP 4
PR111 200K/F_6 DDPWRGD_R 13 ILIM1 RT8206B SKIP# DDPWRGD_R +
28
2
PGOOD1 PGOOD2
1
8
7
6
5
change to 330u/6.3V_6x5.7 5V_EN 14 27 3V_EN
PR247 PR267 EN1 EN2 PR245
15 DH1 DH2 26
*0_4 *2.2_6 16 25 PC100 SHORT_PAD_6 PC194
PC201 5V_DL LX1 LX2 *2200p/50V_6 330u/6.3V_6X5.7
4 37 PAD
+ 36
2
3
2
1
PAD
PGND
PVCC
PC91 PQ69
BST1
BST2
GND
PAD
PAD
PAD
DL1
DL2
0.1u/50V_6 PC204 PC205 AO4710 PD10
NC
330u/6.3V_6X5.7 PC224 0.1u/50V_6 0.1u/50V_6 SX34 1 2
PR108 *2200p/50V_6 PQ71 PR255 PR246 *0_4
35
34
33
17
18
19
20
21
22
23
24
SHORT_PAD_4 AO4710 PR256 1/F_6 1 2
1
2
3
1/F_6 1 2 PR249 SHORT_PAD_4

PD13 1 2 3V_DL
SX34 PC191
0.1u/50V_6
PC93 PR258 VL PR240 SKIP PR112 *0_6 REF
10u/25V_1206 *0_6 SHORT_PAD_6 PR109
PC209 *0_6
2 0.1u/50V_6 PC207
PD11 1u/16V_6
CHN217UPT 3
+5VPCU 1 3 +5V_GPU
OCP:8A PR250
1 SHORT_PAD_6 +3VPCU
PQ59 0.75A PR257 L(ripple current) 0 ohm change to shot pad 2/12 09
PR220 AO3413 SHORT_PAD_6
2
PC99 2 =(19-3.3)*3.3/(2.2u*0.5M*19)
+5V 10K_4 0.1u/50V_6 PD12 ~2.48A
CHN217UPT 3 PR104
B B
PC210 Iocp=8-(2.48/2)=6.67A 100K/F_4
1 0.1u/50V_6
PR211 Vth=6.67A*15mOhm=94.714mV
PR264
3
R(Ilim)=(94.714mV*10)/5uA
10K_4 +15V_ALWP DDPWRGD_R
+15V ~191K SYS_HWPG <37>
dGPU_5V_EN 2 PR248 SHORT_PAD_4
22_8 PC221
3
PQ63 0.1u/50V_6
DMN601K-7
+5VPCU +3VPCU
1
<11> dGPU_PWR_EN# 2
PQ60
DMN601K-7
7/7 Add +5V_GPU 8/12 modify
1
5
6
7
8
5
6
7
8
VIN_SRC +1.5V_SUS +SMDDR_VREF +15V
MAIND 4 MAIND 4
VIN_SRC +3V_S5 +5V_S5 +15V +5VPCU +3VPCU
+3VPCU
PR75 PR79 PR76 PR74 PQ24 PQ23
1M_6 22_8 22_8 3G@1M_6 AO4496 AO4496
PR233 PR215 PR223 PR212 +3V
3
1
2
5
6
1M_6 22_8 22_8 1M_6
3
2
1
3
2
1
5
6
7
8
SUSD 3
S5D 2 L26 2.17A 3.11A
3
A S5D 4 3 *3G@0_8 A
3
+5V +3V
4
3
PQ22 2 2A 7/28 BOM option for 3G or WL

<37,43> SUSON
3
AO3404 2 PC65
+3VSUS
1
2 2 2 PQ13
<37,48> S5_ON
2 PR77 2.2n/50V_4 3G@AO6402A
+3V_S5
1
2 2 PC185 PQ17 1M_6

3
2
1
PR232 PQ25 0.23A DTC144EU PQ15 PQ16 PQ14

1
PQ57 1M_6 DMN601K-7 DMN601K-7

1
DTC144EU AO4496 3G@DMN601K-7

PROJECT : ZR7
1
PQ61 PQ62 PQ58 2.2n/50V_4

1
DMN601K-7 DMN601K-7 DMN601K-7 Size Document Number Rev

+5V_S5 7/9 add +3VSUS for 3G option 1A
SYSTEM 5V/3V (RT8206)
2.85A Date: Friday, March 05, 2010 Sheet 39 of 50
5 4 3 2 1
5 4 3 2 1
[PWM] PR71, PR72, PR73, PR74, PR75, PR76, and PR77 deleted
VR_PWRGD_CK505# <3> VIN
DELAY_VR_PWRGOOD <4,8>
1
1
+
PC159 PC59 PC61 PC164 PC150
2200p/50V_6 0.1u/50V_6 10u/25V_1206 10u/25V_1206 100u/25V_6X7.7
2
PQ44
5
AOL1448
8/4 EMI request

62882_DH1 4
D D
1
2
3
+VCC_CORE
VIN +3V
PL11 0.36uH
62882_LX1 1 2
PR72 PQ48 PQ49
4
5
5
SHORT_PAD_6 AOL1718 AOL1718 PR73
+ PC66
PR177 PR163 *2.2/F_6
+5V_S5 1.91K/F_4 1.91K/F_4 4 4 330u/2V_7343
PC62
1
2
3
1
2
3
PR71 0.22u/25V_6 5/12 Change pr144 from 10K to 1.91K PC63
10_6 *1000p/50V_6
PR60 SHORT_PAD_8
PR176 PR179
16
17
40
1
PU8 SHORT_PAD_4
SHORT_PAD_4
CLK_EN#
VDD
VIN
PGOOD
PC60
1u/6.3V_4
41 PAD
+1.1V_VTT
UGATE1 20
7/16 modify PR59 10K/F_4
BOOT1 19 1 2
PR165
*499/F_4 PSI# PR164 10K/F_4 2 PR190 VSUM+ PR175 3.65K/F_4
<6> H_PSI# PSI# 2.2_6 PC166
PR64 147K/F_6 3 0.22u/25V_6
RBIAS VSUM- PR178 1/F_4
21
PHASE1
<4> H_PROCHOT# 4
VR_TT# 62882_DL1A
23
PR188 PR53 LGATE1a PR63 10K/F_4
C Close to Phase 1 Inductor *470K_4 NTC *4.02K/F_4 C
5 VIN
PC56 NTC
*0.01u/16V_4 24 62882_DL1B
LGATE1b
1
1 2
1
22 +
VSSP1 PC177 PC75 PC74 PC176 PC179
11 62882_ISEN1 2200p/50V_6 0.1u/50V_6 10u/25V_1206 10u/25V_1206 100u/25V_6X7.7
2
H_VID0 ISEN1
<6> H_VID0 31 VID0
1
H_VID1 32
<6> H_VID1 VID1 PC153 PQ52 8/4 EMI request
5
H_VID2 33 0.22u/10V_4 AOL1448
<6> H_VID2
2
VID2 VSUM-
H_VID3 34 8/10 modify
<6> H_VID3 VID3 62882_DH2 4
H_VID4 35 25 PR198 SHORT_PAD_4 +5V_S5
<6> H_VID4 VID4 VCCP
ISL62882
1
2
3
H_VID5 36 PC168 1u/6.3V_4
<6> H_VID5 VID5 +VCC_CORE
1 2
H_VID6 37
<6> H_VID6 VID6 PC64 1u/6.3V_4 PL12 0.36uH
VR_ON 38 1 2 62882_LX2 1 2
<37> VRON VR_ON PQ51 PQ50
5
DPRSLPVR 39 29 AOL1718 AOL1718
<6> H_DPRSLPVR
4
DPRSLPVR UGATE2
2
PR180 30 1 2 PR83
PR183 499/F_4 BOOT2 62882_DL2 4 + PC70
4
100K/F_4 PR193 *2.2/F_6
2.2_6 PC167 330u/2V_7343
1
1
2
3
1
2
3
8 0.22u/25V_6
FB
28
PHASE2 PR161 PR167
PR65 PC151 26
*10K/F_4 22p/50V_4 LGATE2 PC73 SHORT_PAD_4
SHORT_PAD_4
9 27 *1000p/50V_6
FB2 VSSP2
B B
PR54 10 62882_ISEN2
412K/F_4 PC52 ISEN2
2 1
1
150p/50V_4 7 PC152
COMP 0.22u/10V_4
2
VSUM-
8/10 modify
PC154
10p/50V_4 PR52 6
8.06K/F_4 VW
18 I_MON <6>
IMON
PR51 10K/F_4
1
PR191 PC165
PC53 9.76K/F_4 0.033u/16V_4
1000p/50V_4 VSUM+ PR160 3.65K/F_4
2
5/12 Change pr24 rom 2.87K to 2.8K

ISUM+
ISUM-
VSEN
VSSSENSE
RTN
PR55 VSUM- PR166 1/F_4
5/12 Change pc92 rom 0.33u_4 to 0.22u_6

12
13
14
15
2.7K/F_4 5/12 stuff pc26 0.068u_6 PR58 10K/F_4
PC162 PC161
PR56 PC55 0.22u/10V_6 0.068u/25V_6
562/F_4 390p/50V_4 VSUM+
1
+VCC_CORE 1 2 PR171 PR57

PR61 *27.4_4 82.5/F_4 2.61K/F_4
2
PC57
PC160 PR184
PR62 SHORT_PAD_4 330p/50V_4 11K/F_4
<6> VCCSENSE
Parallel PC155 PC156 PR194
2700p/50V_4
2
A PR68 SHORT_PAD_4 330p/50V_4 0.01u/16V_4 10K _6_NTC Panasonic A

<6> VSSSENSE
PC58
PR185 ERT-J1VR103J
1
1 2 1000p/50V_4 SHORT_PAD_4
PR67 *27.4_4
VSUM-
5/12 Change pr34 rom 1K to 1.24K
PR181
1.24K/F_4 PC158
0.1u/10V_4 Close to Phase 1 Inductor
PC157 PR174 Load Line setting to 2mV/A
*1000p/50V_4 *100/F_4
PROJECT : ZR7
5/12 un-stuff PC76,PR140 1A
CPU Core ( ISL62882)
5 4 3 2 1
5 4 3 2 1
[PWM]
VIN
+5V_S5
PR153 PD7
10_6 RB500V-40
5
D PR149 D
2.2/F_6
1
PR155
1M/F_6 PC138 4 1.05V/15A
4.7u/6.3V_6 OCP: 18A
2
PR154 PC141 PC140 PC42
1
2
3
PU6 SHORT_PAD_6 PQ39 2200p/50V_4 0.1u/50V_6 10u/25V_1206
PR156 UP6111AQDD AOL1448 PC41
SHORT_PAD_6 PC143 *10u/25V_1206
15 13 0.1u/50V_6
<37,42,43,47> MAINON EN/DEM BOOT PL9
+3V 16 12 UGATE-VTT 2.2uH
PC45 TON UGATE
*0.1u/50V_6 1 11 PHASE-VTT
VOUT PHASE +1.1V_VTT
2 10 PR152 3.92K/F_6
VDD OC
5
PR45 2.2uH
*10K/F_6 3 9 PC139 PL8
FB VDDP + +
4 8 1u/16V_6 LGATE-VTT 4 PR147
<37> HWPG_VTT PGOOD LGATE *4.7_6
6 7 PQ38 PC39
1
2
3
C GND PGND AOL1718 330u/2V_7343 C
5 NC TPAD 17
PC137
14 *680p/50V_6
NC
1
PC43 PC135
330u/2V_7343 0.1u/50V_6
PC40 PC44 PC136
2
1u/16V_6 *1000p/50V_6 10u/10V_8
VOUT=(1+R1/R2)*0.75
PR151 PC142
R1 4.02K/F_6 *33p/50V_6
PR44 VTT_FB
SHORT_PAD_6
B B
PR150
R2 10K/F_6
AO1718 Rdson=3~4.3mOhm
TON=3.85p*RTON*Vout/(Vin-0.5)
L(ripple current)
Frequency=Vout/(Vin*TON) =(19-1.05)*1.05/(1u*272k*19)
~3.64A
9/4 modify
TON=3.85p*1M*1/(Vin-0.5) 4.3m*18=RILIM*20uA
RILIM=3.87K --- 3.92K
Frequency=1/(0.0036767)=272K
A A

PROJECT : ZR7
1A
+VTT (UP6111A)
5 4 3 2 1
5 4 3 2 1
VIN
+5V_S5
PR116 PD14
D D
10/F_6 RB500V-40
5
6
7
8
1
PR272
PR265 2.2/F_6 PC230 4 1.05V/8A
1M_6 4.7u/6.3V_6 PQ72 OCP: 10A
2
PR266 AO4468 PC105 PC225 PC227
PU13 SHORT_PAD_6 2200p/50V_4 0.1u/50V_6 10u/25V_1206
PR115 UP6111AQDD
SHORT_PAD_6 PC222
15 13 0.1u/50V_6
<37,41,43,47> MAINON
3
2
1
EN/DEM BOOT PL18
+3V 16 12 UGATE-1.05V 2.2uH_8A
PC219 TON UGATE
*0.1u/50V_6 1 11 PHASE-1.05V
VOUT PHASE +1.05V
PR271 2 10 PR117 3.9K/F_6 8/24 modify
VDD OC
5
6
7
8
*10K/F_6
3 9 PC228
FB VDDP 1u/16V_6
C C
4 8 LGATE-1.05V 4 PR273
<37> HWPG_1.05V PGOOD LGATE +
*4.7_6
6 7
Rds*OCP=RILIM*20uA
GND PGND
5 NC TPAD 17
PQ73 PC231
14 AO4710 *680p/50V_6
3
2
1
NC
1
PC104
10u/10V_8
PC106 PC220 PC103
2
1u/16V_6 *1000p/50V_6 0.1u/50V_6

PC229
560u/2.5V_6X5.7
B B
PR268 PC226
R1 4.02K/F_6 *33p/50V_6
1.05V_FB
VOUT=(1+R1/R2)*0.75
PR269
10K/F_6
R2 PR270
SHORT_PAD_6
TON=3.85p*RTON*Vout/(Vin-0.5)
AO4710 Rdson=11.7~14.2mOhm
Frequency=Vout/(Vin*TON) L(ripple current)
A =(19-1.05)*1.05/(1u*272k*19) A
TON=3.85p*1M*1/(Vin-0.5) ~3.646A Quanta Computer Inc.
Frequency=1/(0.0036767)=272K 14.2m*10=RILIM*20uA PROJECT : ZR7
RILIM=7.1K--- 7.15K 1A
VCCP 1.05V(UP6111A)
5 4 3 2 1
5 4 3 2 1
[PWM]
36
D D
PC174
10u/10V_8
PR206 PC175
SHORT_PAD_6 0.1u/50V_6
+0.75V_DDR_VTT
VIN
8207_DH
PC172 PC173
2A 10u/10V_8 10u/10V_8 8207_LX
5
8207_DL
PC178 PC76 PC180
25
24
23
22
21
20
19
1
2
3
PQ53 2200p/50V_6 10u/25V_1206 10u/25V_1206
AOL1448 PL13 12A
LL
DRVL
VTT
VBST
GND
VLDOIN
DRVH
1.5uH
+1.5V_SUS
1 VTTGND PGND 18
2 17
VTTSNS CS_GND + +
5
3 RT8207A 16
GND PU9 CS +5V_S5 PR84
PR82 4 *4.7_6
C +1.5V_SUS 4 4.99K/F_6 C
MODE V5IN 15
PR205 PQ54
1
2
3
5.1/F_6 AOL1718
+SMDDR_VREF 5 VTTREF V5FILT 14
1
PC69 PC77
0.003A
VDDQSNS
VDDQSET
PC71 +5V_S5 6 13 1u/6.3V_4 PC170 *680p/50V_6 PC171 PC169 PC72
2
0.033u/50V_6 COMP PGOOD 1u/6.3V_4 560u/2.5V_6x5.7 *560u/2.5V_6x5.7 10u/10V_8
2
NC
NC
PR204 100K/F_6
S3
S5
+3VPCU
change to 560u/2.5V_6x5.7
FOR DDR III
7
10
11
12
HWPG_1.5V <37>
AO1412 Rdson=3.8~4.6mOhm
PR201 (For RT8207A 400KHZ )
620K/F_4
VIN OCP=12.21+0.5A
S5_1.8V PR199
L(ripple current)
SHORT_PAD_6SUSON <37,39>
=(19-1.5)*1.5/(2.2u*400k*19)
S3_1.8V PR200 SHORT_PAD_6
MAINON <37,41,42,47>
PR78 *0/F_6
PWRGD_1.5VCPU <36> Add it for S3 leakage circuit ~1.57A
PR202
*0/F_6 +5V_S5 7/23 modify
4.6m*12=RILIM*10uA
PR81
RILIM=5.62K
SHORT_PAD_6
PC67 PR203
(10u*PR35)/Rdson+Delta_I/2=Iocp
*33p/50V_6 10K/F_4
Vout = (PR150/PR149) X 0.75 + 0.75
B B
PR80 +1.5V_SUS
10K/F_4 PC68
*0.033u/50V_6
3
MAIND 2
<36,39,47> MAIND
+1.5V_SUS
SW@ PQ18
AO3404
1
VIN +15V
PR69
+1.5V
5
6
7
8
SW@1M/F_6 PR50
SW@1M/F_6
4 2.03A
3
3
PQ9
A PR66 SW@AO4496 A
2 SW@1M/F_6 2
<47> PG_1.5V_EN PC49
3
2
1
PQ10 *SW@2.2n/50V_4
1
PQ11 SW@DMN601K-7
1
PR70 SW@DTC144EUA
1
*SW@100K_4
+1.5V_GPU
2
3.94A PROJECT : ZR7

1A
DDR III 1.5V(TPS51116)
5 4 3 2 1
1 2 3 4 5
+5V_GPU
VIN
PC121
SW @10u/25V_1206
+3V_D_S
PR125 29A
*SW @0_4 OCP=35A
PR16 PC19 PC21
5
SW @200K/F_4 SW @0.1u/50V_6 SW @10u/25V_1206 +VGPU_CORE
PC4 SW @1u/10V_6 2 7 8792TON
VDD TON PQ37
A A
PR4 5 8792DH 4 SW @AOL1448
SW @100K_4 PC2 SW @1u/10V_6 8792VCC DH PC20
13 VCC SW @2200p/50V_4 PC122
1
2
3
6 8792BST SW @10u/25V_1206
8792PGD BST PR15 PC12
<45> PG_GPUIO_EN 14 PGOOD SW @1_6 SW @0.22u/25V_6 PL7
8792EN 1 PU1 SW @0.36uH
<11,21> dGPU_VRON EN 8792LX
LX 4
PR119 change net name MAX8792ETD+T
*SW @0_4 PC1 8792SKIP# 12
SKIP# 8792DL
DL 3
5
+3V_D_S SW @0.1u/10V_4 PR8 *SW @0_4
8792REFIN 10 PR22
PR120 REFIN SW @1_8
FB 8
SW @SHORT_PAD_4
PR118 4 4 + + +
REF-2V
SW @100K_4 8792REF 11 9 8792ILIM PC30
1
2
3
1
2
3
REF ILIM *SW @330u/2V
PC17
EP
SW @1000p/50V_4
PR127
15
SW @44.2K/F_4
PR128
SW @62K/F_4 PR1 PC16
SHORT_PAD_6 *SW @4700P/25V_4 PQ35 PQ34 PC133 PC134 PC25
SW @AOL1718 SW @AOL1718 SW @0.1u/50V_6 SW @330u/2V SW @330u/2V
Place near GND pin15
PR123 PC11
3
B SW @470K/F_4 SW @1000P/50V_4 B
PR14
VID1 SW @100K_4
2 PQ27
<17> VCORE1.2ID0 SW @2N7002E Frequency(PR220=200K) 300K
PR122
SW @100K_4 PR129 Madison VID Table
1
SW @49.9K/F_4
VID1 VID2
changed value on 09/17 PR127 = 44.2K
VCORE1.2ID0 VCORE1.2ID1 +VCC_GFX_CORE PR129 = 49.9K
PC108 PR123 = 470K
SW @0.01u/16V_4 LOW (0) LOW (0) 1.05V PR5 = 220K
HIGH (1) LOW (0) 1.0V

changed to vga_gnd LOW (0) HIGH (1) 0.95V
PR5
3
SW @220K/F_4 HIGH (1) HIGH (1) 0.90V

VID2
2 PQ1
<17> VCORE1.2ID1 SW @2N7002E
PR3 PARK VID Table

SW @100K_4 PR127 = 39.2K CS33922FB15
VID1 VID2
1
PR129 = 49.9K
VCORE1.2ID0 VCORE1.2ID1 +VCC_GFX_CORE PR123 = 332K CS43322FB15
PR5 = 130K CS41302FB00
C LOW (0) LOW (0) 1.12V C
PC3
SW @0.01u/16V_4 HIGH (1) LOW (0) 1.05V VIN_SRC +VGPU_CORE
LOW (0) HIGH (1) 0.95V
HIGH (1) HIGH (1) 0.90V
PR7 PR2
SW @1M_6 SW @22_8
3
change net name
3
2
8792EN 2
PR6 PQ2
PQ28 SW @1M_6 SW @MF2N7002E-G
1
SW @DTC144EU
take out PR318, PQ79, PC258, and PR320
take out PR322
D D

PROJECT : ZR7
1A
GPU CORE(MAX8792)
1 2 3 4 5
5 4 3 2 1
[PWM] PC119 +5V_GPU

SW@10u/10V_8
62872_PVCC2
2
PR131
SW@0_6 PR132
SW@2.2_6 VIN
D D
1
62872_DL
20
1
5
6
7
8
PC22
PC118 SW@0.1u/50V_6 +VGPU_IO
LGATE
PVCC2
SW@10u/10V_8
PR133 4
SW@0_6 2 19
PGND VCC
1
82872_AGND PC115 PC114
82872_AGND 3 18 1 2 SW@2.2n/50V_4 SW@10u/25V_1206 JP4
GND BOOT PC9 PC10 SHORT PAD
PR136 *SW@0_4 PR135 PC126 SW@0.1u/50V_6 SW@10u/25V_1206
4.5A
3
2
1
2
4 17 SW@2.2_6 SW@0.22u/25V_6 62872_DH PQ32
<44> PG_GPUIO_EN EN UGATE DCR(max)=20mohm
SW@AO4468
C IO_VID1_R 5 16 62872_LX C
VID1 PHASE
PR144 *0_4 PU5 PL3
IO_VID0_R 6 SW@ISL62872 15 SW@2.2uH_8A
<17> IO_VID0 VID0 NC
5
6
7
8
+
62872_SREF 7 14 62872_OCSET 8/24 modify
SREF OCSET PR124
4 *4.7_6
2
PR29 8 13 PR23 PR26

SET0 VO
1
SW@15.8K/F_6 SW@0_4 SW@0_4
9 12 62872_FB
2
SET1 FB
PGOOD
PC23 PC107
1
SW@47n/16V_6 *680p/50V_6
SET2
3
2
1
PQ31 PC132 PC127 PC125
2
SW@AO4710 SW@560u/2.5V_6X5.7SW@10u/10V_8 SW@0.1u/50V_6

PR28
10
11
82872_AGND SW@26.7K/F_6 change to 560u/2.5V_6x5.7

PC131
B B
SW@2700p/50V_4
1
2 1 PR25
SW@17.4K/F_6
2
PR30 2 1
PG_1V_EN_1 SW@100/F_6
PR143 PC128
SW@11.5K/F_6 SW@0.1u/25V_4
1
2 1 2 1 2 1 8/10 modify
+3VPCU
PR27 PR145 PR31 PR142
SW@249K/F_6 SW@28K/F_6 SW@24K/F_6 SW@17.4K/F_6
82872_AGND 2 1
8/24 modify
PR141 PR24
*10K/F_4 *10K/F_4
+3V_D_S
IO_VID0_R IO_VID1_R change to "stuff"
A A
PR275 SW@0_4
PR140
SW@10K/F_4
PR139 PR146
SW@10K/F_6
PG_1V_EN_1 Quanta Computer Inc.
SW@10K/F_4
PR274 *SW@0_4 PROJECT : ZR7

PG_GPUIO_EN Size Document Number Rev
<47> PG_1V_EN PG_GPUIO_EN <44>
1A
+VGPU_IO(ISL62872)
5 4 3 2 1
A B C D E F G H
Int_VGA [PWM]
<6> GFX_VID0
<6> GFX_VID1 +1.1V_VTT +1.1V_VTT

<6> GFX_VID2
<6> GFX_VID3
1 PR98 PR97 PR217 PR96 PR93 PR88 PR87 1

<6> GFX_VID4
*0_6 *0_6 *0_6 *0_6 *0_6 *0_6 *0_6
<6> GFX_VID5
<6> GFX_VID6
GFX_VID6 GFX_VID5 GFX_VID4 GFX_VID3 GFX_VID2 GFX_VID1 GFX_VID0
PC193
*0.01u/25V_4
62881_GND 2 1
PR222 SHORT_PAD_4
<6> GFX_ON
PR227 SHORT_PAD_4
<6> GFX_DPRSLPVR
PR219 short VIN
62881_GND
62881DPRSLPVR
62881_GND
62881VR_ON
1
GFX_VID6
GFX_VID5
GFX_VID4
GFX_VID3
GFX_VID2
PC78 PC79 PC182
10u/25V_1206 10u/25V_1206 PC183
2
+3V 0.1u/50V_6 2.2n/50V_4
29
28
27
26
25
24
23
22
5
PR234
VID6
VID5
VID4
VID3
VID2
GND
DPRSLPVR
VR_ON
GFX_VID1
GFX_VID0
1.91K/F_4
1
CLK_EN#
2 4 2
PR99 SHORT_PAD_4 62881PGOOD 2 21 +5V_S5
<37> HWPG_GFX PGOOD VID1
1
2
3
PQ56
PR225 47K/F_4 62881RBIAS 3 20 AOL1448
62881_GND RBIAS VID0
PR226
*150K/F_4 PC80 0616 change to 0.56uH
PR235 8.06K/F_4 62881VW 4 19 1 2
62881_GND VW VCCP
PU4
PC88 4.7u/6.3V_6
22A
ISL62881HRZ-T 18 62881LGATE
1000p/50V_4 62881COMP 5 LGATE PL14 +VGFX_AXG
COMP 0.56uH
PR237 PC195 0616 change to 22pF 17
820K/F_4 22p/50V_4 VSSP
62881FB 6
FB
16 62881PHASE
PC196 0616 change to 8.87k PHASE
DCR=1.6~1.8mOhm
100p/50V_4 PR100
Load Line=7mV/A
5
8.87K/F_4 15 62881UGATE
62881VSEN UGATE PR91 + + 1.6m*0.6168=0.986m
7
VSEN PR207 3.65K/F_4 0.986m/.49K=396p
ISUM+
BOOT
ISUM-
IMON *4.7_6
4 4
VDD
RTN
392p*2*8.87K=7.03m
VIN
PR236 PC89
PR95 PR209 OCP
1
2
3
1
2
3
PQ55 PQ19 2.61K/F_4 10K _6_NTC
20u/2*2.49K=24.9m
8
10
11
12
13
14
17.8K/F_4 150p/25V_4 PC86 PR90 PC81 AOL1718 AOL1718
PC90 330p/50V_4 62881BOOT 1 2 PC181 24.9m/0.6168=40.3m
62881VDD
62881ISUM+
62881ISUM-
62881VIN
0616 change to 150pF 330p/50V_4 1_6 *680p/50V_6 PC192 PC184 PC82 40.3m/1.6m=25.2A
62881RTN 0.22u/25V_6 PR92 560u/2.5V_6X5.7 560u/2.5V_6X5.7 10u/6.3V_8
GFX_IMON
GFX_IMON <6>
PC87 11K/F_4
2
62881_GND PR89
1000p/50V_4 *19.1K/F_4 PC83
*0.022u/25V_4
1
PC187 PC85
3 VSS_AXG_SENSE 0.15u/10V_4 0.1u/10V_4 3
62881_GND
PR214 VIN
SHORT_PAD_4
PC190 62881_GND
PC186 47n/10V_4
0.22u/25V_6
62881_GND
+5V_S5 0616 change to 2.49k
PR216 PC188
*180p/50V_4
PR224
PC189 10_6 2.49K/F_4
1u/6.3V_4
PR221
*100/F_4
62881_GND
PR94 PC84
2 1 0616 un-mount
82.5/F_4 0.01u/25V_4
Parallel
PR229 10/F_4
PR228 SHORT_PAD_4
VSS_AXG_SENSE <6>
4 4
PR231 10/F_4
PR230 SHORT_PAD_4
VCC_AXG_SENSE <6>

PROJECT : ZR7
1A
1.Level 1 Environment-related Substances Should NEVER be Used. +VGFX_AXG (ISL62881)
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners. Date: Friday, March 05, 2010 Sheet 46 of 50
A B C D E F G H
5 4 3 2 1
+3VPCU 1.76A
+1.8V
PC97
PC212 0.1u/25V_4
10u/10V_8
PU12 HPA00835RTER
16 10 DCR(max)=10mohm
VIN PH
1 11 PL17
VIN PH 1.0uH/11A_7X7X3
D PR113 D
2 VIN PH 12
SHORT_PAD_4
MAINON 15 13 PR254 SHORT_PAD_6
EN BOOT
54418-1.8_VFB 6 14 PC206 0.1u/50V_6 PR263
VSNS PWRGD 51.1/F_4
PC203 7 3
COMP GND
1000p/50V_4
8 RT/CLK GND 4 R1
PAD
PAD
PAD
PAD
PAD
PAD
HWPG_1.8V <37>
9 SS AGND 5 PR253
PR259 PR261 PR262
100K/F_4
15K/F_4 182K/F_4 +3VSUS 100K/F_4 PC208 PC96 PC211
22
21
20
19
18
17
0.1u/25V_4 10u/10V_8 10u/10V_8
PC216
*100P/50V_4 PC213
MAINON 0.01u/25V_4 54418-1.8_VFB
MAINON <37,41,42,43>
PC217
1200p/50V_4 V0=0.8*(R1+R2)/R2
R2 PR260
78.7K/F_4
+3VPCU
C
SW@ C
2A
+1V
PC149
PC148 SW@0.1u/25V_4
SW@10u/10V_8
PU7 SW@HPA00835RTER
16 DCR(max)=10mohm
VIN PH 10
1 11 PL10
VIN PH SW@1.0uH/11A_7X7X3
PR159 2 12
SW@SHORT_PAD_4 VIN PH
15 13 PR157 SW@SHORT_PAD_6
<45> PG_1V_EN EN BOOT
54418-1_VFB 6 14 PC147
VSNS PWRGD SW@0.1u/50V_6 PR173
PC144 7 3 SW@51.1/F_4
COMP GND
SW@1000p/50V_4
8
RT/CLK GND
4 R1
PAD
PAD
PAD
PAD
PAD
PAD
PG_1.5V_EN <43>
9 5 PR158
PR169 PR168 SS AGND PR170
SW@10K/F_4
SW@8.06K/F_4 SW@182K/F_4 +3VSUS SW@20K/F_4
22
21
20
19
18
17
PC145 PC146 PC48

PC51 SW@0.1u/25V_4
SW@10u/10V_8
SW@10u/10V_8
B PC50 B
*SW@100P/50V_4
SW@0.01u/25V_4 54418-1_VFB
PC54
SW@1200p/50V_4 PR162 +1.8V
SW@78.7K/F_4
V0=0.8*(R1+R2)/R2 VIN_SRC +15V
R2
SW@
PR49 PR46
SW@1M/F_6 SW@1M/F_6
1
2
5
6
change p/n 3 PQ6
SW@SWAO6402A
3
3
PR47
4
SW@SHORT_PAD_4
+1.5V_GPU 2 2 +1.8V_GPU
PR48 PQ8 PC46
+3V +5V +1.05V SW@1M/F_6 SW@DMN601K-7 *SW@2.2n/50V_4
VIN_SRC +1.1V_VTT +1.5V +15V PQ7 1.41A
1
7/9 change power enable SW@PDTC143TT
1
PC47
PR187 PR172 PR196
net name to +1.5V_GPU SW@1u/10V_4
Add it for S3 leakage circuit
PR192 22_8 22_8 PR182 PR197 22_8 (ZY9B solution)
<36> MAINON_DIS_G 1M/F_6 22_8 22_8 PR189
1M/F_6
7/23 modify
MAINON_G MAIND
A MAIND <36,39,43> A
3
3
PR186
2 1M/F_6 2
<37,41,42,43> MAINON PC163
2 2
2 2 2 PQ40 *2.2n/50V_4 7/7 modify
1
PQ47 DMN601K-7
1
PR195 DTC144EUA PQ41 PQ45

1
*100K_4 PQ42 PQ43 PQ46 DMN601K-7

1
DMN601K-7
PROJECT : ZR7
1
DMN601K-7 DMN601K-7 DMN601K-7

2

1A
Discharge/1.8V)
5 4 3 2 1
1 2 3 4 5
VIN_SRC
A A
PD9
SW1010CPT
PR241
1M_6
1
PQ65
AO3409
TH_ON 2
3
Thermal protection
3
S5_ON S5_ON 2
<37,39> S5_ON
PQ66
1
B
VL VL DTC144EUA B
SYS_SHDN# <4,39>
PR218 PR242
? 1K_4 200K/F_4 PR244
200K_6
PC200
0.1u/50V_6
3
8
PR148
10K _6_NTC 2.469V 3 +
1 2
NTC 2 - PQ67
PU10A DMN601K-7
4
LM393 PC202
1
0.1u/50V_6
PR238
C 200K/F_4 C
+3VPCU
3
VL
S5_ON 2
PR208
PQ64 100K/F_6
DMN601K-7
PR210
1
10K/F_6
PD8
5
+ NC_TEMP
7 T75
4.95V 6
-
PU10B RB500V-40
LM393
For EC control thermal protection (output 3.3V)
PR213
1M/F_6
D D

PROJECT : ZR7
1A
Thermal Protection
1 2 3 4 5
5 4 3 2 1
300 mil ISL62882 1800 mil 1800 mil CPU

VCC_CORE
PU7 U3031
U38 U3035 U50 CN27 U6 U22 U33 CN1 CN2 CN34 CN36 CN30 CN15
40 mil 20 mil 40 mil 40 mil 20 mil 20 mil 20 mil 30 mil 20 mil 80 mil 80 mil 80 mil 20 mil
200 mil CN19 CN20 CN10 CN43 CN12 CN16 CN41 U2
200 mil AO6402A +5V
20 mil 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil
D +5VPCU PQ35 D
520 mil
280 mil AO4496 280 mil CN9

+5V_TMA
400 mil ISL6237 PQ82 280 mil
PU4
40 mil AO6402A 40 mil U3035 PU7 PU8 PU9 PU10 PU6 PU11
+5V_S5
PQ38 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil 20 mil
200 mil
R330 R3691 U45 ESD1 U23 CN15 CN14
AC System +5VPCU
Charger 20 mil 10 mil 20 mil 30 mil 20 mil 20 mil 20 mil
ISL6251A VIN
CN39 CN6 U4 U19 U14 CN5 R428
DC
PU2 20 mil 10 mil 70 mil 10 mil 70 mil 130 mil 20 mil
40 mil D30 MR1 CN14 U16 U8 R429 PU12 R164 R586 R437 L22 U9 PU2
+3VPCU
C
20 mil 15 mil 20 mil 30 mil 20 mil 20 mil 20 mil 15 mil 20 mil 10 mil 10 mil 20 mil 10 mil C
+3VPCU 250 mil AO4496 250 mil L26 U15 R3343 R649 R462 L3035 R184 R3587 R167 R192 R195 U3010 CN27
PQ25 +3V 20 mil 10 mil 20 mil 20 mil 30 mil 15 mil 30 mil 15 mil 10 mil 30 mil 30 mil 10 mil 80 mil
U5 Q6 U33 U27 U18 U44 R655 R619 R710 L57 CN11 R496 R499
R327 CN12 CN18 U29 U13 CN5 R158 R36 R11 R29 CN3 R3289 R3292
150 mil AO6402A 150 mil 30 mil G973 40 mil U3031 R3301 R3268 L25 R711 L28 R3291
PQ7 +3V_S5 PU11 +1.8V 30 mil 15 mil 15 mil 15 mil 40 mil 25 mil 20 mil
120 mil R654 Q22 CN17 R198 U21 U3017 U29 R17 U3044 U11 R151
20 mil 120 mil 30 mil 20 mil 15 mil 20 mil 30 mil 20 mil 20 mil 15 mil 30 mil
B B
20 mil G909 20 mil R3234 R34

+1.5V_S5
PU12 15 mil 15 mil
R3340 R448 R165 L3055 R3570 R3056 R180 R3304 L3046 L3048 R186 R454 R455
200 mil UP6111A 400 mil 20 mil 80 mil 20 mil 15 mil 150 mil 15 mil 15 mil 15 mil 15 mil 15 mil 40 mil 50 mil 50 mil
PU10 +1.05V
L3047 R185 R3644 L3058 R195
15 mil 30 mil 60 mil 15 mil 30 mil
250 mil UP6111A 600 mil
PU9 +VTT Q39 U3031 R3243 R195
10 mil 600 mil 15 mil 15 mil
80 mil JDIM3001 JDIM3002
+SMDDR_VTERM 40 mil 40 mil
200 mil TPS51116 20 mil R3326

+SMDDR_VREF 20 mil
PU6
A
600 mil 300 mil AO4496 300 mil R3302 CN17 CN9 U18 R69 R668 U29 R676 A
+1.5VSUS +1.5V
PQ23 15 mil 30 mil 180 mil 20 mil 30 mil 30 mil 60 mil 30 mil
400 mil
JDIM3001 JDIM3002 U3031
100 mil 100 mil 350 mil
200 mil ISL62881 400 mil
+VAXG U3031
PU8 Quanta Computer Inc.
350 mil
PROJECT : ZR7B
1A
POWER MANAGEMENT
5 4 3 2 1
5 4 3 2 1
MODEL
ZR7
Model REV CHANGE LIST FRO M To
X 1A
10/6 1. Change Hole13,14,15,16,18,19,20,21,27 for layout requirement__P35
1A X 1A
2. Rename__All
ZR7B MB 3. Unstuff R203, R171__P27
X 1A
10/12 1. PQ6 and +1V power system add SW@ for power design change__P47 1A B 2A
2. Swap VCORE1.2ID1 to pin AL13__P17 1A B 2A
3. Change PR5, PR123, PR127, PR129 for power design change__P44 1A B 2A
4. Unstuff PC68 for power design change__P43 1A B 2A
5. Change Net name RST_GATE#_R to RST_GATE#__P36 1A B 2A
6. Change U37 to 2M size__P9 1A B 2A
7. Change PU7,PU12 for power design change__P47 1A B 2A
1A B 2A
10/19 1. Change U36 P/N for PCH version update__P8~P13
2A 1A B 2A
2. Del R358 for ODD power control__P29
1A B 2A
3. Unstuff R588,R268, Stuff R587,R273 for Speaker issue__P12, P30
1A B 2A
4. Power design change
1A B 2A
* PC223 change to use CC71004MZ01
1A B 2A
* PC201 change to use CC73301MZ04
* PC194 change to use CC73301MZ04 1A B 2A
* PL11,PL12 change to use CV+18V0MZ04 1A B 2A
* PC136, PC104, PC172, PC173, PC174,PC72 change to use CH6102K9A19 1A B 2A
* PC68 change to use CH33306K915
1A B 2A
* PR127 change to use CS34422FB00
1A B 2A
* PR129 change to use CS34992FB01 1A B 2A
* PR5 change to use CS42202FB10 1A B 2A
* PC121 change to use CH61004M291 1A B 2A
* PC21 change to use CH61004M291
1A B 2A
* PL7 change to use CV+18V0MZ04
1A B 2A
* PC25,PC134,PC30 change to use CH733RY8802
* PC118,PC119,PC127 change to use CH6102K9A19 1A B 2A
* PC10,PC114 change to use CH61004M291 1A B 2A
* PC211,PC212, PC96,PC148,PC146,PC48 change to use CH6102K9A19
1A B 2A
10/28 1. R380,R376 PH with +3VPCU__P37
1A B 2A
2. Mark +1V power system with sw@__P47
1A B 2A
3. Mark +1.8V_GPU power system with sw@__P47
1A B 2A
4. Change Net RF_LED_R and RF_LED# for BT and WLAN LED control__P37
1A B 2A
5. Change CN4 P/N and footprint to 8pin for cost down__P24
D
1A B 2A D
6. Add R607, R608 for SW/B signal__P33
1A B 2A
7. SMT product issues_All
1A B 2A
* CN12,CN21 change footprint__P28
1A B 2A
* PL10,PL17 change footprint__P47
1A B 2A
* PU8 change footprint__P40
1A B 2A
1A B 2A
1A B 2A
* Q36,Q40,Q42 change P/N__P31
1A B 2A
* U34 change footprint__P27
1A B 2A
9. Add R609 for vender suggest__P3
1A B 2A
10. Add R610,R611,Q45,Q46, del R444, R443 for HDMI test__P25
1A B 2A
11. Add R291,R315 for Acer requirement__P31
1A B 2A
12. PC25, PC30, PC134 change value to 330u/2V_P44
1A B 2A
11/12 1. Change bead from CX08T121000 to CX5AG121001 for vender cost down requirement__All
1A B 2A
2. Change Bead from CX05T121000 to CX5AG121001 for vender cost down requirement__All
1A B 2A
3. CN8 change P/N and footprint for ME design change__P34
1A B 2A
4. Add Q45, Q46, R610, R611, del R443, R444 for HDMI issue__P34
1A B 2A
5. Change PJ1 for ME design change__P38
1A B 2A
6. Change HOLE18, 23, 6, 9, 27, 22, 17 and add HOLE30, 31 for machenical change_P35
1A B 2A
7. Add R444, R443 1.5K for HDMI test__P25
1A B 2A
8. Stuff L32, L35, L36, L38, Unstuff R230, R229, R321, R324, R316, R314, R306, R297 for EMI requirement __P34
1A B 2A
9. Change R494, R520 from 0ohm to bead for EMI requirement __P34
1A B 2A
10. Change R419 from 680ohm to 51ohm for ATI design change __P18
1A B 2A
11/17 1. Remove 3G@, Add MP@ for separate different parts between Madison and Park__All
1A B 2A
2. Remove Power Short Pad__All
1A B 2A
3. Add PC232 for power design change__P38
1A B 2A
4. Add Q47,R642 ,R542 for WiFi LED__P33
1A B 2A
5. Change U16 P/N for update LAN chip version__P33
1A B 2A
6. Change PJ1, CN8, CN4, BT1, CN14 for ODD, RTC, Battery connector change__All
1A B 2A
11/18 1. Swap L38 for layout requirement__P34
3A 1A B 2A
2. Change CN9 P/N and footprint for ME issue__P32
1A B 2A
3. Change HOLE18, 23, 6, 9, 27, 22, 17 for layout requirement_P35
4. Power design change
B 2A C 3A
* PR128, PR102, PR101, PR158, PR110, PR111, PR151, PL8, PL9, PR117, PL13, PR82 change P/N for power design change_All
B 2A C 3A
* Del PC68 for power design change_All
B 2A C 3A
* Add PC190 for power design change_All
B 2A C 3A
B 2A C 3A
12/9 1. Change PR17, PR18, PC232 for Power design change__P38
B 2A C 3A
2. Del Q36, R455 and R441, Q33 change mark__P25
B 2A C 3A
3. R22,R23,R25,R27,R47,R65 change mark to MP@__P18
B 2A C 3A
4. Change R92, C565 location for ATI design change__P18
B 2A C 3A
5. Reserve R639 and add HDMI_HPD_PCH# for EC requirement__P9,P25
B 2A C 3A
B 2A C 3A
12/18 1. Add R455,R612 PCH strap pin __P9
B 2A C 3A
2. Del 0ohm_0402: R10,R11,R15,R14,R83,R402,R388,R90,R91,R107,R144,
B 2A C 3A
R190,R199,R198,R220,R231,R248,R256,R273,R363,
R369,R393,R394,R387,R437,R438,R400,R401,R501, B 2A C 3A
R503,R526,R532,R548,R550,R552,R553,R554,R555, R556,R590,R606__All B 2A C 3A
3. Del 0ohm_0603:
B 2A C 3A
R493,R122,R139,R148,R173,R174,R175,R176,R218,
R219,R226,R228,R255,R232,R234,R235,R236,R237, B 2A C 3A
R244,R264,R267,R284,R307,R545,R558,R581,R587__All B 2A C 3A
4. U16 change footprint for PM requirement__P26
B 2A C 3A
5. Del R268,R588 for Audio I/O power level__P31
B 2A C 3A
6. Add R590 for LAN design change__P26
B 2A C 3A
7. Add R643 for W/L LED design change__P33
B 2A C 3A
8. SMTPE requirement
B 2A C 3A
*JSIM1 change footprint
B 2A C 3A
*PU3 change footprint
B 2A C 3A
*PR130 change footprint
B 2A C 3A
12/22 1. Cahnge Hole18, Hole23 for layout modify__P35 B 2A C 3A
B 2A C 3A
12/24 1. R455 & R612 reconnect_P9
B 2A C 3A
2. R552/R553/R554/R555/R556 change back to 0 ohm for black screen issue verify_P28
B 2A C 3A
3. CN9 footprint change footprint_P32
B 2A C 3A
4. Update VRAM table and add VRAM@ mark_P23
B 2A C 3A
5. EMI solution
B 2A C 3A
* R90 & R91 change to unstuff , L13 stuff._P24
B 2A C 3A
* Add R614 on LVDS_BRIGHT_P24
B 2A C 3A
* Adding C813 for VIN
B 2A C 3A
* Adding C814,C815,C816,C817,C818,C819,C820,C821 for VIN_SRC
B 2A C 3A
* Adding C822 for CSOP_1,PC102 change to stuff
B 2A C 3A
* Adding C823,C824,C825,C826,C827 for VIN_SRC
B 2A C 3A
* Add C828 to +3V
B 2A C 3A
* Change R614 to bead_P24
B 2A C 3A
6. Add F1 & F2 for safety.
B 2A C 3A
7. Add JP4 and delete JP5 for for change VGPU_IO source
B 2A C 3A
8. Change PR55 to 2.7K for Power change design_P40
B 2A C 3A
9. Add 3G@ for 3G function_All
B 2A C 3A
C C
12/31 1. U28 change to 512K, U37 change to 4M for BIOS design change_P9,P37
4A
2. Change R328,R329,R330,R331,R334,R335 value for LED Brightness fine turn_P33
3. Stuff PR274,unstuff PR136, PR275 for change VGPU_IO source_P45
1/5 1. Reserve Board_ID PAD and unstuff R629,R630,R631,R632,R633,R634 _P10

2. Remove R417,R413,Q30,Q31 for costdown_P23,P37
3. Add trace VGA_THERM#_P23,P37
4. NONE
5. D10, F1 replace location_P24
6. Stuff R99, Change Q6<P/N modify> location for dGPU_SELECT_R control design change_P24
2010/01/11 1. unstuff R486
2. R244 change from shortpad to RC0603 and unstuff.
3. C482 change from cap to 0 ohm resistor.
2010/01/18 1. delete PAD of U11/U12/U14

2.
PR1 3. PD# PU change from +3V to +5VA & R599 change to 1K ohm resistor.
SHORT0603
2010/01/19 1. PQ7 changes to BA001430Z49
PR44 2. PR1
SHORT0603 SHORT0603 3. remove shortpad R139/R148/R144
PR36 4. R152/R154/R259 change to SHORTPAD
PR44
SHORT0402 SHORT0603 5. R78 connect from +3V to +3V_D and R75 change to Unstuff.
6. F1/F2 update P/N.
PR72 PR36
SHORT0603 SHORT0402
PR62 PR72
SHORT0402 SHORT0603
2010/01/20 1. Unstuff R552/R553/R554/R555/R556
PR81 PR62 2. L23/L24/L25/R221/R249/R260/R305/R241/R242/R29/R32/R482/R544/ change to SHORTPAD
SHORT0603 SHORT0402 3. BOM for Board-ID,check again.
PR68 PR81 2010/01/21 1. add C829/EC1/EC2

SHORT0402 SHORT0603 2. Delete U30/C189
3. Delete D21/D22 , ADD Q36/Q39
PR115 PR68 4. Change PR21 to CS-2203J913
SHORT0603 SHORT0402 5. Change PC18 to CH22206K917
6. Unstuff<C815/C816/C817/C818/C820/C821/C823/C824/C825/C826/C827>
PR99 PR115
SHORT0402 SHORT0603 2010/01/22 1. R49/R101 change to SHORTPAD
2. Delete C829
PR154 PR99 3. C816/C818/C819/C820 change net and stuff.
SHORT0603 SHORT0402 4. Q36/Q39 should be always @ NOT SW@
PR105 2010/02/03 1. C777/PC190/PC1 update P/N & description.

PR154
SHORT0402 2. PR222 Value change back to 0_4
SHORT0603
2010/02/04 1. PR222 change to SHORTPAD
PR156 PR105 2. delete Q36/Q39 , add D21/D22, and reserve PAD of R615
SHORT0603 SHORT0402
PR107 2010/03/05 1. Delete PD2

PR156
SHORT0402 2. PR101 & PR102 change P/N.
SHORT0603
PR206 PR107
SHORT0603 SHORT0402
PR108 PR206
SHORT0402 SHORT0603
PR240 PR108
SHORT0603 SHORT0402
PR113 PR240
SHORT0402 SHORT0603
PR245 PR113
SHORT0603 SHORT0402
PR161 PR245
SHORT0402 SHORT0603
PR250 PR161
SHORT0603 SHORT0402
PR167 PR250
SHORT0402 SHORT0603
PR254 PR167
SHORT0603 SHORT0402
PR176 PR254
SHORT0402 SHORT0603
PR257 PR176
SHORT0603 SHORT0402
PR179 PR257
SHORT0402 SHORT0603
PR266 PR179
SHORT0603 SHORT0402
B PR185 PR266 B
SHORT0402 SHORT0603
PR270 PR185
SHORT0603 SHORT0402
PR198 PR270
SHORT0402 SHORT0603
PR60 PR198
SHORT0805 SHORT0402
PR214 PR60
SHORT0402 SHORT0805
PR120 PR214
SHORT0402 SHORT0402
PR222 PR120
SHORT0402 SHORT0402
PR199 PR222
SHORT0603 SHORT0402
PR227 PR199
SHORT0402 SHORT0603
PR200 PR227
SHORT0603 SHORT0402
PR228 PR200
SHORT0402 SHORT0603
PR228
SHORT0402
PR230 PR157
SHORT0402 SHORT0603
PR230
SHORT0402
PR239 PR159
SHORT0402 SHORT0402
PR239
SHORT0402
PR248 PR47
SHORT0402 SHORT0402
PR248
DOC NO.
PROJECT MODEL : ZR7B APPROVED BY: DATE: 2009/12/24
PROJECT : ZR7 SHORT0402
1A
Change list2 PR249 PART NUMBER: DRAWING BY: REVISON: C3A
SHORT0402
PR249
SHORT0402
PR251
SHORT0402
PR251
SHORT0402
PR252
SHORT0402
PR252
SHORT0402
A A
5 4 3 2 1

Acer Aspire Timelinex 5820tg Quanta zr7b Rev 1a SCH PDF

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Acer Aspire Timelinex 5820tg Quanta zr7b Rev 1a SCH PDF

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5 4 3 2 1

Azalia SPI SPI ROM

Int. MIC ALC271X-GRR NPCE781 X'TAL RT8206B RT8207A TPS54418RTE x2

ISL62882 MAX8792ETD+T Discharger

SW@ for Switchable Graphic only SKU

MP@ for Madison & Park different parts

GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

Thermal Follow Chart

B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B

+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC

+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS

+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V

+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0

+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0

+VGFX_AXG variation Internal GPU POWER GFX_ON S0

+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0

+1.05V +1.05V PCH CORE POWER MAINON S0

+VCC_CORE variation CPU CORE POWER VRON S0

LCDVCC +3.3V LCD POWER LVDS_VDDEN S0

+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable

+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable

+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable

+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable

+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable

+1V +1V DP/PEG POWER PG_1V_EN Discrete enable

Quanta Computer Inc.

Quanta Computer Inc.

AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

Processor Compensation Signals

JTAG & BPM

Processor pull-up JTAG MAPPING

XDP_TMS R192 *51_4 0_4

Scan Chain STUFF -> R469, R491, R507

R189 (Default) NO STUFF -> R489, R490

Quanta Computer Inc.

AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3) U33D

<15> M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 <15>

DDR SYSTEM MEMORY - B

M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ40 AK3 AR5 M_B_DQS#6

Channel A DQ[15,32,48,54], DM[5] Channel B DQ[16,18,36,42,56,57,60,61,62]

Quanta Computer Inc.

CPU Core Power U33F

VTT Rail Values are AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

1.1V RAIL POWER

C339 330u/2V_7343 AC32 +1.1V_VTT AJ16 Y1

CPU CORE SUPPLY

PEG & DMI

VCC62 VTT1_52 VTT1_68

VCC88 VCC_SENSE VCCSENSE <40>

AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

CFG7 R172 *3.01K/F_4

Quanta Computer Inc.

Size Document Number Rev

Date: Friday, March 05, 2010 Sheet 7 of 50

IBEX PEAK-M (DMI,FDI,GPIO)

Digital Display Interface

<37> ICH_RSMRST# C16 H7 SUSC# <37> BC46

PM_RI# F14 F6 PM_SLP_LAN# TP29

PCH Pull-high/low +3V_S5