COMPARISON OF SPLITTING AND LUT APPROACH FOR AES

DECRYPTION IMPLEMENTATION
PUNEETH S B
M.Tech in Digital Electronics,Department of ECE, Don Bosco Institute of Technology,
Bangalore, India.
puneeth003@gmail.com

TEJASWINI M L
AssistantProfessor, Department of ECE, Don Bosco Institute of Technology, Bangalore, India.
mltejaswini238@gmail.com

KALASHREE S
M.Tech in Digital Electronics,Department of ECE, Don Bosco Institute of Technology,
Bangalore, India.
kalasris6@gmail.com

GAURAVI SHETTY
M.Tech in Digital Electronics,Department of ECE, Don Bosco Institute of Technology,
Bangalore, India.
gauravishetty@gmail.com

ABSTRACT:Advanced Encryption Standard (AES), which was developed by FIPS. It is

abbreviated as advanced encryption system for saving digital data, which is a serious problem.
Hence there is a requirement of high speed coding and decoding of the data which need to
protected from the access of the unauthorised person. AES can be used in PDAs and Debit and
Credit cards with magnetic tape, which provide security for the details, these operations has to
performed at high speed and low on-chip area, to meet these constraints AES decryption
algorithms have been designed and synthesised for the two methods which are LUT And Splitting
method.

INTRODUCTION

From J. Daemen and V. Rijmen,1999 Cryptography involves two parts Encryption and
Decryption. Encryption operation is performed on the data which need to be avoided being
accessed to unauthorised person. This will be done using particular key which masks the original
data.Decryption, it is for decoding the data which will beencrypted using certain cryptographic
rules, for which the key used for encryption is necessary. After designing an algorithm for the
operation of Encryption and Decryption in Verilog language using Xilinx tool. The code written
has to be optimised for which the work has to done on reducing the area and delay of the hardware
implementation. This is done by using a compatible FPGA kit. AES has four basic steps operation:
Sub bytes, Shift row, Mix columns and Add round key. These four steps make one round of the
AES. The number of rounds gives the key size. All four layers has there inverse operations. This
inverse operation has the multiplier part, where the optimisation or faster multiplier need to
replaced, so that the decryption becomes faster and time required for waiting until data to be
decrypted will be reduced. Animplementation of the decryption unit of AES, in inverse mix
columns the multiplication can be done in many ways. Multiplication can be performed by adding
same number for the pre-mentioned number of times where those two are the number of which
product need to be found. FromAdam Bernet, 2003 Other method is LUT which is similar to the
tables book, from which the answer will be taken and that particular row and column will be
identified and value will be accessed from the table. From Hua Li and ZacFriggstad,
2005Splitting method, this is done by splitting the numbers to the nearest round figure, so that the
multiplication operation will be performed by using partial products, sum of these partial products
will give the required to result. These two methods have their own advantage and disadvantage
which need to verified and based on the best result it can be used.

Multiplication involved in mixed columns and inverse mix columns is based on Galois field
multiplication,here a particular number will be used with which the encoded data will be xored.
This xor operation need to be performed based on the number of bits, it has to be seen that MSB
bit of the encoded data should be xored with MSB bit of the number. The full explanation of
Galois field multiplier, whose scope is beyond this paper. It is multiplication of power 2.

LUT
Look up table, it is kind of multiplication used in AES. There is a table which stores the value of
the declared values for unique of combination of numbers which is not repeated. Original table is
in hexadecimal whose values do not repeat and the values are of 8bit. This table helps in reducing
multiplication operation every time, which consumes much of the time. Here the LUT values are
given manually instead of using code book, which generates its own values. The product of
multiplication is given by the L lookup table and adding the results of multiplicands and finding
the E lookup table value for product.

For example if BF*9 has to be performed, then BF will be seen in L table, whose value
is9D(hexadecimal). For 09 it is C7. 9D and C7 has to be added whose sum is 169, since the sum is
greater than FF then, the sum has to be subtracted from FF, which gives 65, E table value of 65 is
30.
If Input=4F BF 5C 41
Output[0]=(4F*E)XOR(BF*B)XOR(5C*D)XOR(41*9)
=E(L(4F)+L(E)) XOR E(L(BF)+L(B)) XOR E(L(5C)+L(D)) XOR E(L(41)+L(9))
=E(38+DF) XOR E(9D+68) XOR E(22+EE) XOR E(8F+C7)
=E(117) XOR E(105) XOR E(110) XOR E(156)
=E(18) XOR E(6) XOR E(11) XOR E(57)
=F7 XOR 55 XOR E1 XOR 7F
=3C
After the Ltable operation, the results are added, if the sum is greater than FF then modulo of FF
will be performed. This modulo value will replace the sum. If the sum is not greater then the
operation continues.Either in Encryption or in decryption the key must be expanded, which will be
used in Add Round key function. Each time add round key is used, the results will be XORed.
During the AES performance Add round will be called for each time and one extra time during the
beginning of AES

SPLITTING METHOD

Splitting method is a basic mathematical technique to find the product of big numbers which will
take little more time than usual ones. The numbers will be split in such a way that it will be for

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easy for obtaining products and after the multiplication of all combinations each will result in
partial products, these partial products will be added to give final answer.

Example: 24*45, it can be split into 20+4 and 40+5. Now, all the combinations of multiplication
will be performed i.e. 20*40,4*40,20*5,4*5, all the products need to be added up to get the
product.

Even in this method, Galois field multiplication will be performed coming to data which is in form
of bits, for example if 11001011 then it is given as x7+x6+x3+x+1. Addition of two elements in
GF is done by XORing. Multiplication of two such elements is done by multiplying one term to all
the terms of the second polynomial, like this all terms need to be multiplied. When the power is
more than 7, it has to be reduced to the modulo of x8+x4+x3+x+1. This is done by xi-8, I is the
degree of polynomial that has to be reduced.
For example: (x5+x3)*(x6+x2)=x11+x9+x7+x5.
x11+x9+x7+x5
+ x11+x7+x6+x4+x3
x9 +x6+x5 +x4+x3
+ x9+x5 +x4+x2+x
x6+x3+x2+x
For the inverse operation in matrix multiplication, we take E,B,D,9, in splitting method these
numbers will be split to:
E=2+C;
B=3+8;
D=1+C;
9=1+8;
Since the multiplication is distributive over addition, the single matrix which will be taken by
E,B,D,9 and next three rows will be rotate right of previous row. This will be split into the above
given numbers and two matrices will be formed.

RESULTS

The code written in Verilog is simulated for Spartan 3E. The results obtained are as follows. The
number of slices consumed is around 426% and number of 4input LUT is 849%. It is over
mapped to the Spartan 3E due to its large area.

Similarly, for the splitting method, when it is simulated for Spartan 3E, the number of 4 input LUT
consumed during the execution is around 5% and number of slices consumed is around 6%.
Number of bonded IOBs is 96%. The synthesized report gives information regarding
consumption of LUT and IOBs.

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 Figure 1.Synthesis report of LUT

Figure 2.Synthesis report of Splitting Method

The area and time consumption for this particular design can be calculated using tools like
Synopsis or Cadence.

FUTURE SCOPE AND CONCLUSION

These two methods are using more numbergates and delay hence for the fast computation
of AES it requires another algorithm. This can be performed by replacing the above
methods by Vedic maths in multiplication which is mostly used in the Galois Field
Multiplier and Mixed column operations. This data is obtained from Hua Li and
ZacFriggstad, 2005,Adam Bernard, 2003.

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REFERENCES

J. Daemen and V. Rijmen(1999), AES Proposal: Rijndael, AES Algorithm Submission.

Advanced Encryption System (AES)(2001).
Hua Li and Zac Friggstad, Department of Mathematics, University of Lethbridge. An efficient
architecture for the AES Mix columns operation. IEEE 2005.
ABI Software development written by Adam Bernet, 2003.
Huddar, S.R.; Rupanagudi, S.R.; Kalpana, M.; Mohan, S., "Novel high speed vedic mathematics
multiplier using compressors," Automation, Computing, Communication, Control and
Compressed Sensing (iMac4s), 2013 International Multi-Conference on , vol., no., pp.465,469,
22-23 March 2013
Sushma R. Huddar, Sudhir Rao Rupanagudi, Venkatesh Janardhan, Surabhi Mohan, and S.
Sandya, "Area and Speed Efficient Arithmetic Logic Unit Design Using Ancient Vedic
Mathematics on FPGA," in Advances in Computing, Communication, and Control, pp. 475-
483, Springer, Berlin Heidelberg, 2013.
Ashwini M. Deshpande, Mangesh S. deshpande and Devendra N. Kayatanavar, FPGA
Implementation of AES Enryption and Decrytion,International Conference On Control,
Automation, Communication And Energy Conservation -2009.
Dr.R.V.Kshirsagar, M.V.Vyawahare, FPGA Implementation of High speed VLSI Architectures
for AES Algorithm, 2012 Fifth International Conference on Emerging Trends in Engineering
and Technology.
AES page available via http://www.nist.gov/CryptoToolkit

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