CEN433
King Saud University
Dr. Mohammed Amer Arafah
1
Address Decoding
MS (9 bits) LS (11 bits)
n Memory devices interfaced are usually Memory
of smaller storage capacity than the BA0-19 19 11 10 0 chip
full address space of the processor
A10-A0
n For example, the 2716 is 2 K x 8
memory device has 11 (= 1 + 10) 9 Selector 11 Address
bits bits
address inputs (A0-A10).
9 to 1
n When interfaced to a microprocessor CS/
Decoder
with 20 address signals there is a
mismatch.
n The extra 9 address pins (A11-A19)
are decoded using a decoder such FFFFFH High
that they select the memory device for 511 Memory
a unique position in the memory map (ROM)
of the processor. MS (9 bits) LS (11 bits) 510
Memory locations:FF800H-FFFFFH
BA19 1 2 1 U1
n Selector address: 20 15 = 5 bits 2
3
4
74LS04
n If we want the memory locations to U2B 5
8 CS/
5 6
00010000000000000000 = 10000H BA17
74LS04
n End address BA16
BA15 5 6
n Selector 5 bits: 00010 (Remain
fixed) 74LS04
Memory locations:F0000H-FFFFFH
32 K x 8 32 K x 8 32 K x 8
In Byte operation,
28F400 DQ15 is an input
Flash accepting A0
Memory address bit.
512K x 8
(In the Byte In the word mode:
Mode) 256 K x 16
80000H
7FFFFH
Address:
Start: 10000000000000000000
Enable Power down mode End: 11111111111111111111 00000H
i.e. 80000H to FFFFFH
Programming supply voltage Flash occupies the top
Half of the memory map
Additional control s for Flash memory.
Used for programming (erasing)
. .
. .
. .
00005 00004
00003 00002
00001 00000
Note: A1
not A0 32K x 8 32K x 8
Write Write
Enable Enable
for low Common CE for both banks
for high
bank Active Low (one decoder)
bank
00000 00000
8K 8
BA1-13
RAM BD0-7
03FFF
RAML1CS/
04000
8K 8 MEMR/
32K 8 RAM LWR/
07FFF
RAM BA1-15
BD8-15
08000
RAMHCS/ BA1-13
BD0-7
16K 8 MEMR/
RAML2CS/
RAM HWR/
MEMR/
LWR/
0FFFF 0FFFF
BA1-14 BD0-7
RAML3CS/
RAMHCS / MEMR/
LWR/
BA14 RAML1 CS /
A
BA15 B RAML2 CS /
G RAML3 CS /
74LS139
CEN433 - King Saud University 37 Mohammed Amer Arafah