VII Latin American Symposium on Circuits and Systems (LASCAS) 2016
0.3 V Supply, 17 ppm/oC 3-Transistor Picowatt
Voltage Reference
Arthur Campos de Oliveira , Jhon Gomez Caicedo , Hamilton Duarte Klimach and Sergio Bampi
Microelectronics Graduate Program, Federal University of Rio Grande do Sul
Porto Alegre, RS, Brazil
oliveira.arthurc@gmail.com, jhalexgomez@hotmail.com, hamilton.klimach@ufrgs.br, bampi@inf.ufrgs.br
AbstractIn this work a novel resistorless MOSFET 3-
transistor voltage reference that operates in the picowatt range
and occupies very small area is proposed. The circuit is based on
a self-cascode structure that is biased in subthreshold condition
using the leakage current provided by a reverse biased MOSFET
diode. Its electrical behavior is analytically described and a
design methodology is presented to allow the transistors sizing
for optimal temperature compensation. Simulation results for
a standard 130 nm CMOS process are presented to validated
the proposed circuit topology. A reference voltage of 85 mV is
obtained with a temperature coefficient (TC) of 17.4 ppm/o C
and consuming only 7 pW under 0.3 V of power supply at
room temperature. Monte Carlo analysis shows that the reference
voltage /< 3.3% and that 90% of the samples present TC<50
ppm/o C without trimming.
KeywordsVoltage reference, subthreshold, ultra-low power,
ultra-low voltage, picowatt.
I. I NTRODUCTION
Basically the generation of a voltage reference is performed
through the sum of two voltages with different tempera-
ture characteristics, being one complementary, and the other
proportional to the absolute temperature (CTAT and PTAT,
respectively), resulting a temperature independent voltage.
The most common used strategy is the so called bandgap
voltage reference (BGR), where the junction diode (or bipolar
junction transistor) CTAT behavior is counterbalanced by a
PTAT source, resulting the silicon bandgap voltage as the
reference output.
The first practical BGR circuit was proposed by Widlar
in 1971 [1]. Since then several methods were proposed to
improve the design of voltage references through the years
[1][8]. Although presenting adequate performance for many
applications, typical BGRs require power supply voltages over
1.5 V and sub-BGRs over 0.9 V, which might not meet the
low voltage constraints for low power applications [6].
The transistor subthreshold operation has been widely ex-
ploited in order to achieve both low power consumption and
low supply voltage [2][9]. In this case, the most common
approach to generate a PTAT voltage is through the difference
of the gate-source voltages of two transistors operating in the
subthreshold region [9].
In recent works, this approach is also used to perform
the difference between two threshold voltages (VT ) of dif-
The authors are grateful to CNPq, CAPES and IC-BRAZIL program for
financial support and PDK licensing.
ISBN 978-1-4673-7835-2/16/$31.002016 IEEE 263
ferent types of transistors [3], [7] to generate a supply and
temperature independent voltage reference. However, the use
of transistors with distinct VT s increase the impact of the
fabrication variability on the performance of the circuit. In
[8] the dependence of VT with respect to the channel length
(L) is exploited in order to obtain different VT . But due its
small output voltage and topology limitation, its performance
is degraded.
In this work, we propose a novel 3-Transistor (3T) volt-
age reference based on the self-cascode (SC) structure. The
generation of a temperature-compensated voltage reference
is performed by means of two different threshold voltages
of two MOS transistors of the same type. The two distinct
threshold voltages are obtained through the exploration of the
dependence of VT with respect to L. The proposed topology
is capable of operate at the minimum supply voltage of 0.3 V
while consuming only 7 pW under room temperature.
This paper is organized as follows: section II presents the
proposed 3T voltage reference circuit. The design method-
ology and considerations about the circuit are presented in
section III. Section IV presents the simulated results for the
proposed concept and the comparison of our circuit with
recently published low-power/voltage works. Finally, section
V presents the conclusion.
II. C IRCUIT D ESCRIPTION
The schematic of the proposed 3T voltage reference is
shown in Fig. 1. In this circuit, all transistors are operating in
weak inversion and the bias current is provided by a reverse
biased diode composed by M3 . M1 and M2 form the SC
structure which is used to perform the difference between
their gate-source voltages. Since M1 and M2 are the same
type of transistors, their different VT are achieved through the
VT dependence with respect to L. Therefore, a supply and
temperature independent voltage reference can be obtained by
adjusting the aspect ratio of M1 and M2 in order to compensate
the temperature variation of their threshold difference.
To design the proposed circuit a continuous MOSFET
model that is valid from weak to strong inversion conditions
and from the triode to the saturation regimes is used. Accord-
ing with the Unified Current Control Model (UICM) [10], the
drain current can be described as the difference between a
forward (IF ) and a reverse (IR ) current components
ID = IF IR = IS (if ir ) = ISQ S(if ir ) (1)
IEEE Catalog Number CFP16LAS-ART
 VII Latin American Symposium on Circuits and Systems (LASCAS) 2016

VDD
VT 1 VT 2
  
IS2
VREF = t ln 1 + exp (7)
M3 IS1 nt
 
VT 1 VT 2
Defining = IIS2
S1
exp n t
, if  1, VREF can be
approximated as
M2
VT 1 VT 2
 
ISQ2 S2
VREF VREF = + t ln (8)
n ISQ1 S1
M1 The threshold voltage has a linear dependence with respect
to temperature [11]:

Fig. 1. Schematic of the proposed voltage reference circuit. VT (T ) = VT (T0 ) T (T T0 ) (9)

where VT (T0 ) is the threshold voltage at room temperature
where S = W/L, being L the length and W the width and T is the first derivative of the threshold voltage with
of the channel of the transistor, if and ir are the forward respect to temperature, where T is a positive number (T >
and reverse normalized currents or inversion coefficients, and 0). Replacing (9) in (8) leads to
2
ISQ = Cox 0
n 2t is the sheet normalization current, which
VT 1 (T0 ) VT 2 (T0 ) (T 2 T 1 )(T T0 )
is a process related parameter, where n represents the almost- VREF = +
constant subthreshold slope factor, Cox
0
is the gate capacitance n
  n (10)
per unit area, and t = kT /q is the thermal voltage. The kT ISQ2 S2
+ ln
relationship between the inversion coefficients and the terminal q ISQ1 S1
voltages is given by [10] By setting VREF /T = 0, the optimal value for the ratio
S2 /S1 can be obtained
VG VT nVS(D) q q 
q T 1 T 2
  
= 1 + if (r) 2 + ln 1 + if (r) 1 S2 ISQ1
nt = exp (11)
(2) S1 ISQ2 k n
where VG , VS and VD are the gate, source and drain Replacing (11) in (10) the temperature compensated voltage
voltages, referenced to the bulk terminal, and VT is the reference is obtained as
threshold voltage.
To prevent the adequate operation of the SC we must keep VT 1 (T0 ) VT 2 (T0 ) (T 1 T 2 )T0
transistors operating in the subthreshold region. Also, we can VREF = + (12)
n n
suppose that M2 works in saturation while M1 is in triode.
According to (1), the drain currents of M1 and M2 can be Assuming that all bulk-source voltages are zero and T 1
described as function of the forward and reverse coefficient T 2 , a simplified expression of VREF can be obtained
levels, then
VREF = VT 1 (T0 ) VT 2 (T0 ) = VT (13)
ID1 = IF 1 IR1 = IS1 (if 1 ir1 ) (3) Through (13), the proposed voltage reference provides the
difference of the threshold voltages of the transistors that
compose the self-cascode structure, in this case M1 and M2 .
ID2 = IF 2 = IS2 if 2 (4) It is important to note that (13) holds only for  1, which
can be adjusted through the W and L of both transistors, and
From (1)-(3) leads to the drain current of M1
zero bulk-source voltages.
VG1 VT 1 III. D ESIGN M ETHODOLOGY
  
ID1 = 2eIS1 exp
nt In order to obtain distinct VT , or more precisely VT 1 >
 (5)
VG1 VT 1 nVREF VT 2 , the channel length (L) of the transistors that compose

exp
nt the SC must be different. Fig. 2 shows the variation of the
VT with respect to L for different values of W for a low-
and the drain current of M2
power transistor of a standard 130 nm CMOS process. VT is

VG2 VT 2 nVREF
 extracted as presented by [12]. As it is shown, VT decreases
ID2 = 2eIS2 exp (6) as L increases, and VT depends only of L for larger values
nt
of W. The type of transistor used is defined by the maximum
Since the current that flows through the drain of M1 and variation of VT with respect to L in order to achieve a wider
M2 is the same, we have ID1 = ID2 which leads to range for the voltage reference. The L of both transistors (M1

ISBN 978-1-4673-7835-2/16/$31.002016 IEEE 264 IEEE Catalog Number CFP16LAS-ART

 VII Latin American Symposium on Circuits and Systems (LASCAS) 2016

620
W = 1 m
reference voltage is very small, these TC values represent a
600 W = 50 m
W = 100 m
total variation of only 0.18 mV and 0.68 mV respectively over
580 the temperature range. The line sensitivity (LS) obtained for
VT (mV)

560 VDD ranging from 0.3 V to 1.2 V is 0.417 %/V at 27 o C, as

540 shown in Fig. 4(b).
520

500
100 101 102
85.8 VDD = 0.3 V 80
Channel Length (m) VDD = 0.5 V
85.3
VDD = 0.7 V
85.6 VDD = 1.2 V 85.25
60

VREF (mV)

VREF (mV)

VREF (mV)
Fig. 2. Threshold voltage vs L and W. 85.2
85.15
85.4
40 85.1
85.05
85.2
and M2 ) are defined by the required voltage reference given 20
85
0.3 0.525 0.75
VDD (V)
0.975 1.2

by (13). 85

If we consider that the transistor is saturated for VDS > 0 20 40 60 80 100 120
0
0 0.2 0.4 0.6 0.8 1 1.2
Temperature (oC) VDD (V)
3 4t , the minimum acceptable voltage will be VDDmin =
8t + VREF . Therefore, M3 is sized to keep M2 and itself (a) Temperature dependence (b) Line sensitivity
saturated over all temperature range at minimum VDD . In 0
order to have a minimum size for M3 , and consequently 2 VDD = 0.3 V
VDD = 0.5 V
5

a lower current consumption, M2 must have a long L to 1.5

VDD = 0.7 V
VDD = 1.2 V
10

Power (nW)

PSRR (dB)
guarantee a VDS > 4t at minimum VDD . As shown before, 15

(13) holds only if  1, therefore the selected W1 have 1 20

25
to be small, leaving only W2 as a variable to perform the 0.5 30
temperature compensation. Since M1 can be in triode, the 35
voltage reference can range from sub-kT/q to hundreds of mV. 0
40 0
0 20 40 60 80 100 120 10 101 102 103 104 105 106 107
To find the optimal ratio between M1 and M2 Fig. 3 Temperature (oC) Frequency (Hz)
shows the TC versus S2 /S1 . The curve is obtained with (c) Power consumption (d) Power Supply Rejection-Ratio
W1 /L1 =2 m/1 m, W3 /L3 =100 m/2 m, L2 =50 m and
varying W2 . The circuit could be more carefully designed Fig. 4. Simulated performance of the proposed voltage reference.
for area minimization. The S2 /S1 ratio predicted by (11) for
the optimal TC is 0.9 (W2 =90 m), which matches with the The power consumption temperature dependence is reported
simulated ratio. With the given dimension the values of the by Fig. 4(c). At VDD = 0.3 V, for 27 o C and 120 o C
threshold voltages of M1 and M2 are VT 1 =589.3 mV and it consumes 7 pW and 420 pW, respectively. The power
VT 2 =503.9 mV, respectively, resulting in a voltage reference consumption reaches a maximum of 2 nW at VDD = 1.2 V
of 85 mV. The required supply voltage is VDDmin = 285 mV. and 120 o C. Since the proposed voltage reference is target for
Therefore, it can be approximated as VDDmin = 300 mV. low-voltage applications, it its expected for it to be used in
the pW consumption range. As the circuit is biased with the
900
leakage current, it discards the need of a startup circuit.
The power supply rejection ratio (PSRR) is reported by Fig.
TC (ppm/oC)

600 Predicted 4(d) and show -38 dB at 10 Hz and -18 dB at 100 Hz.
300
The sensitivity of the proposed voltage reference to process
Simulated
variability is evaluated through Monte Carlo (MC) simulation.
0
0.5 0.8 1.1 1.4 1.7 2 The obtained results for VDD = 0.3 V are shown by Fig. 5.
S2/S1 VREF and TC are shown considering both average process (PC)
and process and mismatch (PC+MM) variations, with 100 runs
Fig. 3. TC vs the ratio S2 /S1 and the optimal choice for minimum TC.
each. VREF over average process variation is reported by Fig.
5(a), yielding / = 2%, while the PC+MM combination
IV. S IMULATION R ESULTS presents a spread of / = 3.24%. The simulated TC for
As this work presents a proof of concept, the results both PC and PC+MM variations resulted 90% and 87% of the
presented here are for schematics simulation only and using samples below < 50 ppm/o C, as depicted in Figures 5(b) and
low-power transistors of IBM 130 nm process. 5(d).
Fig. 4(a) presents the temperature dependence of the circuit The comparison of our circuit with recently published low
and its dependence with the supply voltage. The typical voltage and low power voltage references is reported in Table
reference voltage VREF obtained is around 85 mV at room I. The proposed voltage reference presents the lowest power
temperature. The minimum obtained TC in the 0 o C to 120 consumption over all other references considering, when is the
o
C range is 17.4 ppm/o C at 0.3 V, reaching a maximum of case, their post-trimming results [4], [7]. Our topology also
67.1 ppm/o C at 1.2 V. But keep in mind that since the average presents one of the best trade-offs among supply voltage, TC

ISBN 978-1-4673-7835-2/16/$31.002016 IEEE 265 IEEE Catalog Number CFP16LAS-ART

 VII Latin American Symposium on Circuits and Systems (LASCAS) 2016

TABLE I
C OMPARISON BETWEEN OUR WORK AND RECENT LOW- VOLTAGE / LOW- POWER VOLTAGE REFERENCES .

(+ ) experimental; ( ) simulation [4]a,+ [5] [6]+ [7]a,+ [8]+ This Work Unit
Technology 0.18 0.18 0.18 0.13 0.18 0.13 m
Temp. Range -40-125 0-125 0-125 -20-80 0-120 0-120 oC

Supply Voltage 0.45-1.8 0.85-1.8 0.45-2 0.5-3 0.15-1.8 0.3-1.2 V

Power@room temp. 32,000 4,860 3,150 29.5 26.1 7 pW
VREF 118.46 479 263.5 176 17.69 85 mV
TC 63.6 8.79 142 29 1462.4 17.4 ppm/o C
LS 0.44 0.2112 0.44 0.036 2.03 0.417 %/V
PSRR@100 Hz -44.2 -48 -45 -51 -64 -18 dB
a After trimming

30 40 At 0.3 V the circuit consumes only 7 pW while presenting

25
= 85 mV
= 1.76 mV
35 a TC of 17.4 ppm/o C from 0 to 120 o C. Monte Carlo
simulation shown a / = 3.25% spread for VREF and TC
Process Samples

Process Samples

30
20
< 50 ppm/o C for 87% of the samples, when considering both
25
15 20

10
15 average process and mismatch variations. Due its robustness
5
10
and simplicity, the voltage reference can range from sub-kT/q
5

0 0
to hundreds of mV and also can be optimized for a lower
78 80 82 84 86 88 90 92 94 0 20 40 60 80 100 120
VREF (mV) TC (ppm/oC) power consumption and wider temperature range.
(a) (b)
30 40
R EFERENCES
25 = 85 mV 35 [1] R. Widlar, New developments in ic voltage regulators, IEEE Journal
PC+MM Samples

PC+MM Samples

= 2.76 mV 30 of Solid-State Circuits, vol. 6, no. 1, pp. 27, Feb 1971.

20
25 [2] Y. Osaki, T. Hirose, N. Kuroki, and M. Numa, 1.2-v supply, 100-nw,
15 20 1.09-v bandgap and 0.7-v supply, 52.5-nw, 0.55-v subbandgap reference
10
15 circuits for nanowatt cmos lsis, IEEE Journal of Solid-State Circuits,
10 vol. 48, no. 6, pp. 15301538, June 2013.
5
5 [3] W. Yan, W. Li, and R. Liu, Nanopower cmos sub-bandgap reference
0
78 80 82 84 86 88 90 92 94
0
0 20 40 60 80 100 120 with 11 ppm/ o c temperature coefficient, Electronics Letters, vol. 45,
VREF (mV) TC (ppm/oC) no. 12, pp. 627629, June 2009.
[4] Y. Wang, Z. Zhu, J. Yao, and Y. Yang, A 0.45-v, 14.6-nw cmos
(c) (d) subthreshold voltage reference with no resistors and no bjts, IEEE
Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 7,
Fig. 5. Variability results for VREF and TC. pp. 621625, July 2015.
[5] O. Mattia, H. Klimach, and S. Bampi, 0.9 v, 5 nw, 9 ppm/o c resistorless
sub-bandgap voltage reference in 0.18 m cmos, in 2014 IEEE 5th
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The literature lacks in experimental results for fabrication 2014, pp. 14.
[6] L. Magnelli, F. Crupi, P. Corsonello, C. Pace, and G. Iannaccone, A
variability of weak inversion voltage references with substan- 2.6 nw, 0.45 v temperature-compensated subthreshold cmos voltage
tial samples [2], [5]. For this reason variability comparison reference, IEEE Journal of Solid-State Circuits, vol. 46, no. 2, pp. 465
may not be reliable. 474, Feb 2011.
[7] M. Seok, G. Kim, D. Blaauw, and D. Sylvester, A portable 2-transistor
V. C ONCLUSION picowatt temperature-compensated voltage reference operating at 0.5 v,
IEEE Journal of Solid-State Circuits, vol. 47, no. 10, pp. 25342545,
This paper presented a novel resistorless MOSFET 3T Oct 2012.
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indicate a reference voltage around 85 mV from 0.3 to 1.2 V.

ISBN 978-1-4673-7835-2/16/$31.002016 IEEE 266 IEEE Catalog Number CFP16LAS-ART