2 Text Books:
1. Rabaey J. M., Chandrakasan Anantha, Nikolic Borivoje, Digital Integrated Circuits : A Design Perspective,
PHI Learning Private Limited, 2nd Edition.
4. Gregorian R., Temes G.C.,Analog Mos integrated circuits for signal processing, Wiley interscience publication.
5. Sze S.M.,VLSI Technology, Second edition, McGraw Hill International Edition.
6. Randall A Geiger, Phillips E. allen, Noel R Strader, VLSI Design techniques for analog and digital circuits,
McGraw Hill International Edition 1990.
10. Johns. David A. and Martin K, Analog Integrated Circuit Design, John Wily & Sons Inc. 2002.
5 Course Plan:
Sr. Topic Learning Objective No.of
No. Lectures
1. Introduction to VLSI Design Methodo- Introduction to the semiconductor industry 2
gies
2. Scaling Technology Generation transition and its effects on 2
performance
3. CMOS Technology, Design Rules, MOS Introduction to layouts and industry design flow for 3
Capacitances analog and digital integrated circuits
4. Advanced Current Sources & sinks; Building temperature independent voltage and cur- 6
Current Reference circuit, Operational rent references, Basic building block for most analog
amplifiers Architectures,feedback subsystems
5. Noise Quantification of various types of noise in analog cir- 8
cuits
6. MOS inverter- Static and switch- Basic building block for most digital sub-systems and 4
ing characteristics,Combinational MOS Speed of digital systems Study and design of various
logic circuits static logic CMOS logic gate families
7. Synchronous system and Sequential cir- Synchronous design, timing metrics,Design of flip- 5
cuits design flops
8. Memory Circuits Design Design of SRAM, DRAM, decoders, sense amplifiers 5
9. Design verification & test Verification of functionality,manufacturing defects 4
6 Evaluation Scheme:
EC No. Components Duration Marks Date & Time Remarks
14.09.2014
1 Test-I 1 Hour 40 Closed Book
08.30-09.30 AM
19.10.2014
2 Test-II 1 Hour 40 Closed Book
08.30-09.30 AM
3 Assignments/Surprise Quiz/Online Test 40 Throughout Semester Open Book
7 Assignment/s:
Regular system design Assignments covering use of Cadence tools for Simulation of VLSI Circuits will be given.
9 Make-up Policy:
Make up for any component will be given only in genuine cases. In all cases prior intimation must be given to IC.
10 Notices:
All notices related to the course will be put on moodle page of course. Also students are requested to check their mails
on institute Email ID regularly.
Instruction Incharge
EEE F313/INSTR F313