VLSI vlsi@pantechmail.

com

TESTING METHODOLOGY | ARCHITECTURE DESIGN | TANNER | SYSTEM

GENERATOR | LOW POWER VLSI | MEMEORY DESIGN | IMAGE PROCESSING |
EMBEDDED APPLICATION

Project
Project Titles Application Technology
Code
Cellular Automata based Built-In-Self Test Implementation for
PS VLSI 901 NoC
Star Topology NoC
An Approach to LFSR-Based X-Masking for Built-In Self-Test
PS VLSI 902 BIST

Testing Methodology
New Approaches for Power Binning of High Performance Processor
PS VLSI 903
Microprocessors design
Test Point Insertion in Hybrid Test Compression / LBIST

2017
PS VLSI 904 BIST
Architectures
Star-EDT: Deterministic On-Chip Scheme Using Compressed
PS VLSI 905 automotive
Test Patterns
A Built-In-Self-Test Scheme for Online Evaluation of Physical
PS VLSI 906 IOT
Unclonable Functions and True Random Number Generators
SR-TPG: A Low Transition Test Pattern Generatorfor Test-
PS VLSI 907 BIST
per-Clock and Test-per-Scan BIST
A Fully Integrated Discrete-Time Superheterodyne Receiver signal
PS VLSI 908
processing
Grid Synchronization of Wind Based Microgrid

Xilinx System generator | Code

PS VLSI 909 communication
FPGA Based Higher Order FIR Filter Using XILINX System
PS VLSI 910 FIR
Generator

Generation
FPGA implementation of hardware efficient adaptive filter signal
PS VLSI 911
robust to impulsive noise processing

2017
Efficient Implementation of Empirical Mode Decomposition in signal
PS VLSI 912
FPGA Using Xilinx System Generator processing
A Code Partitioning Tool for Simulink Models to Implement Quantum
PS VLSI 913
on FPGA-based Network-on-Chip Architecture Computing
Rapid Heterogeneous Prototyping from Simulink
PS VLSI 914 NoC
Real-Time Image Segmentation using a Spiking Neuromorphic
PS VLSI 915
Processor
High-Performance Ternary Adder Using CNTFET signal
PS VLSI 916
processing
Power Carbon
Tanner | Low

Nano Tube

Ultra Low Voltage I-V RFID Tag Implement in A igzo TFT Technology Communicatio
PS VLSI 917
on Plastic n
2017

An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips

PS VLSI 918 Communication
A low power input amplifier for bio-signal acquisition in 28 nm Bio medical
PS VLSI 919
FDSOI technology

1
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2017-18 Pantech ProEd Private Ltd
 VLSI vlsi@pantechmail.com

TESTING METHODOLOGY | ARCHITECTURE DESIGN | TANNER | SYSTEM

GENERATOR | LOW POWER VLSI | MEMEORY DESIGN | IMAGE PROCESSING |
EMBEDDED APPLICATION

Electrical performance of carbon-based power distribution Power

PS VLSI 920 networks with thermal effects High-Density 4T SRAM Bit cell in 14- Management
nm 3-D Cool Cube Technology Exploiting Assist Techniques Memory Design
GAAFET versus Pragmatic Fin FET at the 5nm Si-Based CMOS Power
PS VLSI 921

Carbon Nano
Tanner | Low
Technology Node Management

Power

Tube
2017
Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Signal
PS VLSI 922
Circuits Processing
Ultra-Efficient Fuzzy Min/Max Circuits Based on Carbon Nanotube Power
PS VLSI 923
FETs Management
Implementation of a Motion Estimation Hardware Accelerator on
PS VLSI 924

2017 SPARATAN 6 | Real Time Video

SoC
Zynq SoC

Processing | Night Vision | Vertex

Design and test of smart IP-camera within reconfigurable
PS VLSI 925 Surveillance
platform
Human Silhouette Extraction on FPGAs for Infrared Night Vision
PS VLSI 926 Security
Military Surveillance
The Simulation and Implementation of Radar Signal Surveillance
PS VLSI 927

FPGA
Processing based on Space Domain
Accelerating Eulerian Video Magnification Using FPGA
PS VLSI 928 RADAR
Real-time Video Enhancement on FPGA by Context-based Fusion
PS VLSI 929 Security
Technique
FPGA Implementation of High Frame Rate and Ultra-Low Delay
PS VLSI 930 Optical Vision
Tracking with Local-Search Based Block Matching
FPGA based Tactile Sensor Suite Electronics for Real Time
PS VLSI 931 Tracking
Embedded Processing
A resource-efficient multi-camera GigE vision IP core for embedded Embedded
PS VLSI 932

2017 Embedded
vision processing platforms vision
Dataflow object detection system for FPGA-based smart camera computer
PS VLSI 933

Vision
visions
A Low Complexity Pedestrian Detection Framework for Smart Surveillance
PS VLSI 934
Video Surveillance Systems Systems
FPGA-based circular hough transform with graph clustering for
PS VLSI 935 Tracking
vision-based multi-robot tracking
An FPGA prototype of dual link algorithm for MIMO interference
PS VLSI 936 communications
network
Virtual
reality
2017

Exploring timing side-channel attacks on path-ORAMs

PS VLSI 937 encryption
RISC-V based sound classifier intended for acoustic surveillance in
PS VLSI 938 surveillance
protected natural environments

2
www.pantechsolutions.net | www.pantechproed.com | whats App : 98409 74407
2017-18 Pantech ProEd Private Ltd
 VLSI vlsi@pantechmail.com

TESTING METHODOLOGY | ARCHITECTURE DESIGN | TANNER | SYSTEM

GENERATOR | LOW POWER VLSI | MEMEORY DESIGN | IMAGE PROCESSING |
EMBEDDED APPLICATION

Artificial Neural Network model design and topology analysis for

PS VLSI 939 communications
FPGA implementation of Lorenz chaotic generator
Optimal Rate-Diverse Wireless Network Coding
PS VLSI 940 communications
Accelerating Decision Tree Based Traffic Classification on FPGA and
PS VLSI 941 Traffic

Virtual
Reality
Multicore Platforms

2017
Creating immersive and aesthetic auditory spaces in virtual reality
PS VLSI 942 virtual reality
Decision Tree and Random Forest Implementations for Fast
PS VLSI 943 IOT
Filtering of Sensor Data

2017
IOT
A Review of FPGA implementation of Internet of Things Virtual
PS VLSI 944
Machines
A Parallel Hybrid Heuristic Based on Karps Partitioning for PTSP on shopping
PS VLSI 945
Multi-core Processors Protocol
Design of Low Power Memory Cell Using D Flip-Flop Under
PS VLSI 946 Photo Voltaic
Adiabatic Reduction Technique
Design Methodology for Voltage-Scaled Clock Distribution Photo Voltaic
PS VLSI 947
Networks
Full-Swing Local Bit line SRAM Architecture Based on the 22-nm Fin Processors
PS VLSI 948

Cadence | Memory Design

FET Technology for Low-Voltage Operation Design
Cyclic Combinational Gate Diffusion Input(CCGDI) Technique- A
PS VLSI 949 Memory Cell
New Approach of Low Power Digital Combinational Circuit Design

2016-17
Self-gated resonant-clocked flip-flop optimized for power efficiency Photovoltaic
PS VLSI 950
and signal integrity
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Power
PS VLSI 951
Threshold Logic Flip-Flops Management
Dual Use of Power Lines for Design-for-TestabilityA CMOS
PS VLSI 952 DFT
Receiver Design
Sub threshold Level Shifter with Self Controlled Current Limiter by
PS VLSI 953 CPU Design
Detecting Output Error
Design of a Low Power 4x4 Multiplier Based on Five Transistor (5-T)
ALU Design
PS VLSI 954 Half Adder, Eight Transistor (8-T) Full Adder & Two Transistor (2-T)
AND Gate
Implementation of Low Power Flip Flop Design in Nanometer Power
PS VLSI 955 Regime Management

Analysis of ternary multiplier using booth encoding technique Photovoltaic

PS VLSI 956
2016-17

Archite
VIVAD

Design
cture

system
O|

Multiplier-less pipeline architecture for lifting-based two- Signal

PS VLSI 957
dimensional discrete wavelet transform Processing

3
www.pantechsolutions.net | www.pantechproed.com | whats App : 98409 74407
2017-18 Pantech ProEd Private Ltd
 VLSI vlsi@pantechmail.com

TESTING METHODOLOGY | ARCHITECTURE DESIGN | TANNER | SYSTEM

GENERATOR | LOW POWER VLSI | MEMEORY DESIGN | IMAGE PROCESSING |
EMBEDDED APPLICATION

A New Gate for Low Cost Design of All-optical Reversible Logic

PS VLSI 958 Radar
Circuit
Fully Reused VLSI Architecture of FM0/Manchester Encoding Using Quantum
PS VLSI 959
SOLS Technique for DSRC Applications Computing
High-Speed and Energy-Efficient Carry Skip Adder Operating Under
PS VLSI 960 CPU Design
a Wide Range of Supply Voltage Levels
Low-Cost High-Performance VLSI Architecture for Montgomery Signal
PS VLSI 961

2016-17 VIVADO
Modular Multiplication Processing

| Architecture
A Low-Power Architecture for the Design of a One-Dimensional Edge Preserving
PS VLSI 962

Design
Median Filter
On the Analysis of Reversible Booths Multiplier Telecommunicat
PS VLSI 963
ion
Parity Preserving Adder/ Subtractor using a Novel Reversible Gate Quantum
PS VLSI 964
Computing
Comparisons of Robert, Prewitt, Sobel operator based edge
PS VLSI 965 Defense
detection methods for real time uses on FPGA
Reversible Image Data Hiding with Contrast Enhancement
PS VLSI 966 Machine Vision
Image segmentation framework based on multiple feature
PS VLSI 967

Image Processing | Spartan 3 EDK

Defense
spaces
Reconfigurable Architecture of Adaptive Median Filter An FPGA
PS VLSI 968 Computer Vision
Based Approach for Impulse Noise Suppression
A CDF based Lifting scheme for the satellite image compression
PS VLSI 969 Computer Vision

2016 17
Hardware Implementation of Digital Watermarking System for Real Broadcast
PS VLSI 970
Time Captured Image Transmitting Monitoring
Real-Time Image Segmentation using a Spiking Neuromorphic
PS VLSI 971 Satellite imagery
Processor
Spartan 6 FPGA Implementation Of 2d-Discrete Wavelet signal
PS VLSI 972
Transform In Verilog HDL processing
Research and implementation of color image processing system design
PS VLSI 973
pipeline based on FPGA
Hardware Implementation of a Brain Inspired Filter for Image human vision
PS VLSI 974
Processing
High-Throughput Ring-LWE Crypto processors
PS VLSI 975 Security

4
www.pantechsolutions.net | www.pantechproed.com | whats App : 98409 74407
2017-18 Pantech ProEd Private Ltd