Dept of EEE VFSTR University

UNIT- 4
TRANSISTOR BIASING
DC load line, AC load line and selection of operating point, need for biasing,
various biasing techniques: fixed bias, collector to base bias and self bias with
stability factors. Various compensation circuits, thermal runaway and thermal
stability.
OBJECTIVES
To familiarize the students about the different load line and the need for
biasing.
To familiarize the students about the different biasing techniques.
OUTCOMES
After the completion of the unit the students will be able to
Bias a given transistor.
Connect the compensation circuit.
TEXTBOOKS
1. J.Millman and CC Halkias, Electronic Devices and Circuits, 2nd ed.,
Tata McGraw-Hill, , 2007.
2. S.Salivahanan, Electronic Devices and Circuits , 5th ed.,Tata McGraw-
Hill, 2010.
REFERENCES
1. R.L.Boylestad and Lovis Nashelsky, Electronic Devices and Circuits
Theory, 10th ed., Pearson Education, 2010.
2. N.N.Bhargava, Basic Electronics and Linear Circuits, 1st ed.,Tata
McGraw-Hill, 2009.

Transistor Biasing Page 1 K Rachananjali

Dept of EEE VFSTR University

Introduction:-

This chapter introduces methods for establishing the quiescent operating point of a
transistor amplifier in the active region of the characteristics. Due to changes in
temperature T, the operating point shifts to a new value because the transistor
parameters (, ICO , VBE ) are functions of T. The stability of different biasing
circuits is compared by establishing certain criterion. Compensation techniques are
also presented for quiescent-point stabilization.

DC load line (or) Static load line: -

Consider a common-emitter circuit as shown below, which has capacitors with

negligible reactance at the lowest frequency of operation.

VCC

RB RC
IC
+
IB
+ +
VBE - RL Output
Signal
Signal, v0
Input, vi
IE
- -

The ratings maximum collector dissipation PC(max), maximum collector voltage

VC(max), maximum collector current IC(max) and maximum emitter-to-base
voltage VEB(max) will limit the range of useful operation in the active region even
though RC, RL, RB and VCC can be chosen freely.

Let us suppose that RC is selected so that the dc line is drawn as shown in

figure by approximately locating the co-ordinates on the both axes.

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mA

IC IC(max )
VC
RC
DC load line

IC Q1

vCE (max )
volt
VC VCC VCE
From the output circuit of fig1, using KVL

VCC = ICRC + VCE

VCE = VCC ICRC --------------> (1)

For dc load line, RL = so the effective load RL = R C

To get the required co-ordinates on both axes, put IC = 0 in

eq (1), we get

VCE = VCC---------------> (2)

Put VCE = 0 in eq (1), we get

V CC
IC = ---------------> (3)
RC

V CC
So the coordinates are (VCC, 0) and 0,
RC

Since the values of VCC and RC are known the line is drawn by joining
these two coordinates as shown in fig 2.

AC load line (or) Dynamic load line: -

If the load RL , the load line we drawn is known as AC load line or Dynamic
load line. The effective load RL at the collector is RC in parallel with RL.

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i.e., L =RC || RL
R
The AC load line must be drawn through operating point Q1 as indicated in DC
load line and must have a slope corresponding to RL =RC || RL.

The figure below shows common-emitter collector characteristics, AC and DC

lines of a typical transistor.

IC , mA

IC(max )
IB = 140A

120 A PC(max )
vcc
100 A 80 A
RC
60 A

40 A

20 A

In the above fig, the input may swing a maximum of approximately 40A around
Q1 and if a larger input swing is available, the transistor output may get
deteriorated due to cut-off during a part of the input cycle. So another operating
point Q2 is selected on the DC load line where it meets higher current in the
collector characteristics (here it is 60A). So point Q2 is now operating point for
the AC load line where it passes through, with a slope corresponding to
RL =RC || RL.

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Selection of the operating point: -

In general, a transistor functions linearly when it is constrained to operate in its

active region. The basic application of a transistor when operating in its active
region is amplification. With same waveform as that applied at the input, if the
output signal is not a faithful reproduction of the input signal, for example if it is
clipped on one side, there should be one factor to be examined. This is popularly
known as operating point or Q-point.

To establish an operating point, it is necessary to provide appropriate direct

potentials (using VCC), currents (using RC, RL etc) using external sources. Once the
operating point or Q-point is selected the output should have the same waveform as
that of input and if any change occurs, the operating point should be relocated by
the correct use of external sources.

Need for Biasing: -

To operate the transistor in the active region, the supply voltages and resistances
should establish a set of DC voltages VCEQ and DC currents ICQ to produce
distortion free output in the amplifier circuits. These voltages and currents are
called quiescent (no - i/p) values which determine the operating point or Q-point
for the transistor.

The process of selecting proper supply voltages and resistors for obtaining the
desired Q-point is called Biasing. Biasing circuits are used to get proper and
desired operating point.

When transistor is used as an amplifier, establishment of operating point in the

active region is necessary and is achieved by biasing.

Often Q-point is established near the center of active region of transistor

characteristic to allow similar signal swings in positive and negative directions.

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Biasing Circuits: -

There are basically 3 biasing circuits with which the required operating
point can be achieved.

(i) Fixed Bias Circuit: -

The circuit diagram of the fixed bias circuit is as shown below.

VCC

IC RC
Rb
+

+ +
IB
vBE Output
Signal - RL
Signal, v0
Input, vi
IE
-
_

In the circuit, a high resistance Rb is connected between VCC and base of the
transistor. Since base is made positive w.r.t emitter, transistors base-emitter
junction is forward-biased and by proper selection of Rb the required zero signal or
quiescent base current and in turn collector current flow in the circuit.

Analysis: -

Writing KVL to the base-emitter circuit loop

We get -VCC +IBRb +VBE=0

=>VCC = VBE + IBRb

V CC V BE
=>IB =
Rb

We know that

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IC=IB +ICEO

As ICEO is very small, IC IB

V CC V BE
IC=
Rb

Here , VCC, VBE are constants for a transistor.

IC depends up on R b .

To get constant IC in active region, suitable values of R b are

chosen.
V CC V BE V CC
Rb = or Rb
IC IC

as VBE << VCC

Similarly,

Writing KVL to the collector-emitter circuit, we get

-VCC+ ICRC+VCE= 0

=> VCE = VCC ICRC

Stability Factor S: -

The stability factor S is defined as the ratio of change of

collector current IC with respect to the reverse saturation current ICO,
keeping and VBE constant.
I C I C
i.e. S= V BE ,=constant
I CO I CO

We know that, collector current of CE configuration is given by

IC= IB +ICEO

IC= IB +(1+ )ICO------------->(1)

Differentiating eq(1) w.r.t IC, keeping constant.

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I B I CO
1= + (1+ )
I C I C

I CO I B
=> (1+ ) = 1
I C I C

I C (1+ )
=> = I
I CO 1 B
I C

(1+ )
S = I ----------------> (2)
1 B
I C

For fixed bias circuit,

V CC V BE
IB=
Rb

I B
=> =0
I C

eq(2) becomes,
1+
S= = 1+
10

If =150, then S=151 which means that IC is dependent on ICO by 151

times and in turn on temperature. So any small variations in temperature or I CO, IC
changes abruptly and stability decreases. So fixed bias circuit has high S and
poor stability.

Stability Factor : - The stability factor S is defined by the variation of IC

with VBE and is given by
I C
S = ICO ,=constant
V BE

For fixed-bias circuit, We have IC= IB + (1+ )ICO

V CC V BE
IB=
Rb

V CC V BE
+ (1+ )ICO ----------------->(3)
Rb

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Differentiating (3) w.r.t IC, we get

V BE
( keeping and ICO constant)
I C

I C
S = =
V BE Rb

By choosing Rb w.r.t , S can be made considerably small.

Stability Factor : -

It is defined by the variation of IC w.r.t and is given by

I C
S = ICO ,V BE =constant

For fixed-bias circuit, we have IC= IB + (1+ )ICO

Differentiating above equation w.r.t we get

I C
= IB + ICO

I C IC
=> S = = IB + ICO IB =

(ii) Collector to base bias (or) Biasing with feedback resistor: -

An improvement in stability is obtained by modifying the connection R b in the

fixed-bias circuit as shown in figure below.

IB + IC

Re
Rb
C
IB +
IC
B IB vCE
+
+
_
vi vBE
_ _ E

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In this circuit, the biasing resistor (R b ) is connected between collector and base of
the transistors.

Analysis: -

Writing KVL to the base-emitter circuit

VCC (IB+IC) R C IB R b VBE=0

=>VCC = IB (R b +RC) + ICRC + VBE

V CC V BE I C R C
=>IB = -------------> (1)
R C +R b

Similarly, writing KVL to the collector-emitter circuit,

VCC + (IB+IC) RC + VCE=0

=>VCE=VCC (IB+IC) RL------------> (2)

Stability factor S: -

We know that,
1+
S= I
1 B
I C

From Eq.(1)
I B R C
=
I C R C +R b

1+ 1+
S= R C = RC
1 1+
R C +R b R C +R b

The stability factor S is smaller than 1+, so an improvement in stability is

obtained as compared to fixed bias circuit. Also S can be made smaller by
making R b small or RC large.

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Stability Factor : -

We know that
I C
S = ,ICO =constant
V BE

We have from eq (1)

V CC V BE I C R C
IB =
R C +R b

But IC = IB
V CC V BE I C R C
IC =
R C +R b

Differentiating above equation w.r.t IC, we get

V BE RC
1= (By keeping , ICO constants)
R C +R b I C R C +R b

RC V BE
=>1+ =
R C +R b R C +R b I C

V BE R C +R b +R C
=
I C R C +R b R C +R b

I C
=
V BE R b +(1+)R C

I C
S = =
V BE 1+ R C +R b

As the denominator is always greater than numerator, S will always be

smaller and there will be a great improvement in the stability factor S with
changes in VBE.

Stability Factor S: -

In the above analysis, we have

(V CC V BE I C R C )
IC =
R b +R C

Differentiating the above equation w.r.t , we get

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I C V CC V BE RC I C
= IC +
R b +R C R b +R C

I C R C V CC V BE I C R C
=> 1+ =
R b +R C R b +R C

I C
=> R b + R C + R C = VCC VBE IC R C

I C V CC V BE I C R C
S= =
R b +(1+)R C

For this circuit, S will also be smaller compared to fixed-bias circuit.

(iii.) Self-bias (or) Emitter bias (or) Voltage divider bias: -

If the load resistance RC is very small like in a transformer-coupled

circuit, then there is no improvement in stabilization in the collector-to-base bias
circuit over the fixed-bias circuit.

The circuit diagram of voltage divides bias circuit is shown below.

+VCC

IC

R1 IC RC RC
C C
Rb +
+ B _ VCC
IB
I
B
B
E
E +
vi R2 _ VTh RE
RE
I
IE IB + IC
N
- N

The resistor R1, R2 and RE are used to provide the required bias. The resistors R1
and R2 act as a particular divider network giving a fixed voltage at the bias.

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If the current IC increases due to change in temperature (or) change in , the emitter
current IE also increases and hence the voltage drop across RE increases, reducing
the voltage difference between base and emitter (VBE).Due to reduction in VBE,
base current IB and hence collector current IC also reduce. Therefore, negative
feedback exists in the emitter bias circuit.

Analysis: -

From the Thevenins equivalent circuit

R2
vTh = vCC ----------------> (1)
R 1 +R 2

And
R1R2
R b = R Th = R1||R2 = -------------------> (2)
R 1 +R 2

Also applying KVL to the base-emitter circuit

VTh = IB +R Th +vBE + (IB+IC) RE --------------------> (3)

Similarly

VCE = VCC - IC (RC+RE) ( IC>>IB)

V CC V CE
=>IC= ------------------------> (4)
R C +R E

Stability Factor S: -

We know that
1+
S= I
1 B
I C

Differentiating eq (3) w.r.t IC, considering VBE as constant we get

I B I B
0= R Th + RE + RE
I C I Z

I B R E
=
I C R E +R Th

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1+ 1+
S= R E
= RE
1 1+
R E +R Th R E +R Th

R
1+ R E +R Th 1+ Th
RE
= = 1+ R
R Th + 1+ R E 1++ RTh
E

R Th
If <<1 then above equation reduces to
RE

1
S=(1 + ) =1
1+

Stability factor S for voltage divides or self-bias is less as compared to

other biasing circuits as mentioned.

Stability factor S: -
I C
S is given by S= ICO ,=constant
V BE

From eq(3)
VTh = IB + R Th + VBE + (IB + IC)RE

=>VBE = VTh (RE +R Th ) IB- REIC

We know that

IC = IB + (1+ ) ICO
I (1+ )I CO
IB= C

I C (1+ )I CO
VBE= VTh (RE +R Th ) REIC

R E +R Th I C R E +R Th (1+ )I CO
= VTh + REIC

1+ R E + R Th I C R E +R Th (1+ )I CO
= VTh + ------------------> (5)

Differentiating the above eq w.r.t VBE keeping ICO, constant

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R Th +(1+ )R E I C
1=0 +0
V BE

I C
=
V BE R Th +(1+ )R E

S =
R Th +(1+ )R E

Stability Factor S: -
I C
S is given by S= ICO ,V BE =constant

We have from eq (5)

R Th +(1+ )R E I C R E +R Th (1+ )
VBE = VTh + ICO

R Th +(1+ )R E I C
=VTh + V1

V Th +V 1 V BE R E +R Th (1+ )
=>IC= -------------> (6) where V1= ICO
R Th +(1+ )R E

Differentiating IC w.r.t , considering V1 as independent of

We get
I C R Th +R E 1+ V Th +V 1 V BE [V Th +V 1 V BE ]R E
=
R Th +R E 1+ 2

=
S. V Th +V 1 V BE
1+ (R Th +R E 1+ )
[ S=
1+ (R Th +R E )
R Th +R E 1+
]

Multiplying numerator and denominator by , we get

I C (V Th +V 1 V BE ) I C .S
= =
1+ R Th +R E 1+ 1+

(V Th +V 1 V BE )
IC= from eq(6)
R Th +R E 1+

I C I C .S 1+
S = = where S= RE
1+ 1+
R Th +R E

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From above equations, it is evident that all the values of S, S and S are kept
as low as possible by its self-biasing circuit.

Bias Compensation Techniques: -

The parameters that vary often due to changes in temperature and other
circuit conditions are ICO, VBE and which in turn vary the operating point of the
transistor circuit and to provide stability, we need biasing circuits.

Stabilization techniques refer to the use of resistive biasing circuits

which permit IB to vary so as to keep IC relatively constant.

On the other hand, compensation techniques refer to the use of

temperature sensitive devices such as diodes, transistors, thermistors, sensistors etc
to compensate for the variation in currents. For excellent bias and thermal
stabilization, both stabilization as well as compensation technique are utilized.

They are

1.) Diode compensation for instability due to VBE change.

2.) Diode compensation for instability due to ICO change.
3.) Thermistor compensation.
4.) Sensistor compensation.

(1.) Diode compensation for instability due to VBE change: -

The circuit below shows self bias stabilization technique with a diode
compensation for VBE.

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+VCC

RL
R1 R 2
R Th =
R1 + R 2 C
+
IB VBE _

VTh RE

D RD
VD
VDD

The diode D used in the circuit must be of same material and type as the transistor.
Hence the voltage VD across the diode has the same temperature coefficient
(-2.5mV/) as VBE of the transistor. The diode D is forward biased by the source
VDD and resistor RD.

Writing KVL to the base circuit, we get

VTh IB R Th VBEIERE+VD = 0

VTh VBE + VD = IB R Th + RE(IC+IB) --------------------> (1)

But IC = IB + (1+)ICO-----------------------> (2)

From (1)

VTh VBE+ VD = REIC + (R Th +RE) IB

Substituting the value of IB from equation (2)

I C (1+)I CO
VTh VBE+VD = REIC+ (R Th +RE)

=> [VTh VBE+VD] = REIC+IC (R Th +RE) (1+)ICO(R Th +RE)

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=> [VTh VBE+VD] + (1+)ICO (R Th +RE) = IC[R Th +(1+)RE]

V Th V BE +V D + 1+ I CO R Th +R E
=> IC= ----------------------------> (3)
R Th +(1+)R E

From eq (3) it is clear that, as VBEVD remains constant the current IC remains
constant inspite of VBE variations.

(2.) Diode compensation for instability due to ICO variation: -

The circuit shows transistor amplifier circuit with diode D used for compensation
of variation in ICO. The diode D and the transistor are of same type and same
material. In this circuit diode is kept in reverse biased condition.

The reverse saturation current IO of the diode will increase with temperature at the
same rate as that of transistor collector saturation current ICO.

vcc

RC IC
I R1 C
IB
B

E
vBE
Io

From figure,
V CC V BE V CC
I= =constant
R1 R1

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The diode D is reverse biased by VBE. So the current through D is the reverse
saturation current IO.

Now base current IB = IIO

But IC = IB + (1+)ICO

=>IC = (IIO)+(1+)ICO

If >>1, IC IIO+ICO

IC I + [ICOIO]

From above equation IC is dependent only upon I . Since IO and ICO are almost
constants and hence cancelled. Thus variations ICO is compensated by diode current
IO.

(3.) Thermistor compensation: -

Instead of using diodes (or) transistors, this method uses

temperature sensitive resistive elements like Thermistor.
Thermistor has negative temperature coefficient i.e. its
resistance decreases exponentially with increasing temperature as shown
in figure.

RT

R T
T

Temp

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R T
Slope of the curve = is the temperature coefficient for thermistor and it is
T
negative. The following circuit shows, compensation circuit using thermistor.
vcc

R1 RC IC

vBE _
RT IE
RE

In the figure, R2 is replaced by thermistor RT in self-bias circuit.

With increase in temperature, RT decreases. So voltage drop across it also
decreases. This voltage drop is nothing but the voltage at the base with respect to
ground. Hence, VBE decreases which reduces IB. So IC will also reduce since
IC= IB + (1+) ICO
Whenever temp increases ICO also increases, but due to Thermistor IB decreases. So
IC is kept constant always.
Another circuit for the same compensation technique using Thermistor is shown
below. vcc

R1 RC RT

R2 RE

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In this circuit, thermistor is connected between emitter and VCC to minimize the
increase in collector current due to change in ICO, VBE or with temperature.
IC increases with temperature and RT decreases. So current flowing through RE
increases and hence voltage drop and it decreases VBE and hence IB and in turn IC.
So compensation is done by using this circuit.

(4.) Sensistor compensation: -

This circuit uses Sensistor which has positive temperature coefficient i.e. its
resistance increases exponentially with increasing temperature.

RT

R T
T

Temp
R T
Slope of the curve = .
T

The circuit using this Sensistor is shown below where R1 is replaced by RT in

self bias mode.
vcc

RT RC

vBE _
R2
RE

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As temperature increases, RT increases which decreases the flow of current through

it hence current through R2 decreases which in turn reduces the voltage drop across
it. As the voltage drop across R2 decreases, hence IB decreases. It means, when ICO
increases with increase in temperature, IB reduces due to voltage drop across R2
and IC is maintained almost constant.

Thermal Runaway: -

We know that

IC= IB + (1+) ICO

In the above equation IB, ICO and increase with raise in temperature, in particular
the reverse saturation current ICO changes greatly with temperature. Actually it
doubles for every 10 rise in temperature.

Usually collector current causes the collector-base junction temperature to rise

which, in turn, increases ICO. This increase in ICO further increases collector current
IC as evident from the above equation. So again temperature increases at the
junction which in turn increases ICO and it continues as a cumulating process and is
referred to as self heating.

The excess heat produced at the collector-base junction may even burn and destroy
the transistor. The saturation is called Thermal Runaway. To keep the
temperature within the limits, the heat generated must be dissipated to the
surroundings. Heat sinks are generally employed to dissipate the additional heat
from the transistor.

Thermal Stability: -

Thermal Runaway leads to destroy the transistor and it is necessary to avoid this.

The required condition to avoid thermal runaway is that the rate at which heat is
released at the collector junction must not exceed the rate at which the heat can be
dissipated. It is given by
P C P D
< -----------------> (1)
T j T j

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Where PC is power generated at collector junction

PD is power dissipated

Tj is junction temperature

The steady state temperature raise at the collector junction is proportional to the
power dissipated at the junction and is given by

T= TjTA = PD ----------------> (2) where = constant of proportionality

And is referred to as Thermal resistance

T j T A
=
PD

Differentiating (2) w.r.t Tj we get

P D P D 1
= 1, = --------------> (3)
T j T j

Substituting (3) in eq (1), we get

P C 1
< -------------------> (4)
T j

This condition must be satisfied to avoid runaway.

For voltage divider bias circuit, +vcc

PC= heat generated at collector-junction

DC power input-power loss as I2R R1 RC IC

Let IC=IE
IB
PC = VCC IC IC2 [RC + RE]

Differnetiating above equation w.r.t IC

R2 RE IE
P C
= VCC 2IC (RC + RE) ----------------> (5)
I C

From equation (4)

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P C I C 1
< -------------------> (6)
I C T j

I C
In the above equation can be written as
T j

I C I CO V BE
=S + S +S ---------------------> (7)
T j T j T j T j

As junction temperature is affected by ICO mostly,

I C I CO
=S (neglecting VBE and variations)
T j T j

As the reverse saturation current for both Silicon and Germanium increases
about 7% per , so we can write
I CO
= 0.07ICO
T j

I C
= S0.07ICO
T j

So, eq (6) becomes

1
[VCC2IC (RC + RE)] S 0.07ICO <

As S, ICO and are always positive the inequality is satisfied when

VCC 2IC (RC + RE) is negative

i.e., VCC < 2IC (RC + RE)

V CC
=> < IC (RC + RE) -----------------> (8)
2

Applying KVL to collector circuit of voltage divider bias circuit

VCE = VCC IC (RC + RE)

V CC
IC (RC + RE) = VCC VCE => VCE <
2

V CC
Thus, if VCE is less than , the stability is ensured.
2

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