Lecture Notes

Power MOSFETs

Outline
Construction of power MOSFETs
Physical operations of MOSFETs
Power MOSFET switching Characteristics
Factors limiting operating specfications of MOSFETs
COOLMOS
PSPICE and other simulation models for MOSFETs

Copyright by John Wiley & Sons 2003

MOSFETs - 1
Multi-cell Vertical Diffused Power MOSFET (VDMOS)

contact to source
source
diffusion
conductor
field
oxide

gate
oxide

gate
width
N+ N+ N+ N+
P P

N-

gate N+
conductor

Copyright by John Wiley & Sons 2003

MOSFETs - 2
 Important Structural Features of VDMOS

source gate conductor

body-source
field oxide
short
gate oxide

N+ N+ N+ N+
P (body) P (body)
N- parasitic i channel
(drift region) BJT
D length
integral
N+ diode

drain

1. Parasitic BJT. Held in cutoff by body-source short

2. Integral anti-parallel diode. Formed from parasitic BJT.
3. Extension of gate metallization over drain drift region. Field plate and accumulation
layer functions.
4. Division of source into many small areas connected electrically in parallel.
Maximizes gate width-to-channel length ratio in order to increase gain.
5. Lightly doped drain drift region. Determines blocking voltage rating.

Copyright by John Wiley & Sons 2003

MOSFETs - 3
 Alternative Power MOSFET Geometries
Source

boddy-source short
Oxide

N+ N+
Gate
P Channel
P conductor
length Trench-gate MOSFET
Parasitic BJT Integral
N- ID
ID diode Newest geometry. Lowest
N+ on-state resistance.

Drain

gate oxide
gate source

N+ N+ P
V-groove MOSFET.
P
First practical power
N MOSFET.
i
N+
D Higher on-state
resistance.
drain

Copyright by John Wiley & Sons 2003

MOSFETs - 4
MOSFET I-V Characteristics and Circuit Symbols
i
D [v - V = v ]
GS GS(th) DS
ohmic
i
VGS5 D
active
VG S 4 actual

VG S 3
linearized

V
GS2

VG S 1

v
V GS
v
V
GS
<V
GS(th) BV
DS GS(th)
DSS

D D

G
G
N-channel P-channel
MOSFET MOSFET
S S

Copyright by John Wiley & Sons 2003

MOSFETs - 5
 The Field Effect - Basis of MOSFET Operation
VGG3
V
GG1 +
+ SiO
SiO 2
2 + + + + + + + + + + +
+ + + + + + + + + + +

+ +
N N
ionized P
depletion layer
acceptors
P boundary inversion layer
ionized with free electrons
N acceptors

VG G 2 N depletion layer boundary

+
SiO
2
+ + + + + + + + + + + Val ue deter mi ned by sever al factor s
1. Type of mater i al used for gate conductor
+ 2. Dopi ng densi ty of body r egi on di r ectl y
N
beneath gate
ionized depletion layer 3. I mpur i ti es/bound char ges i n ox i de
P acceptors boundary eox
free electrons
4. Ox i de capaci tance per uni t ar ea Cox =
N t ox
t ox = ox i de thi ck ness

Thr eshol d Vol tage V GS(th)

V GS wher e str ong i nv er si on l ayer has for med.
Typi cal v al ues 2- 5 v ol ts i n power MOSFETs
Adjust thr eshol d vol tage dur i ng devi ce
fabr i cati on vi a an i on i mpl antati on of
i mpur i ti es i nto body r egi on just beneath
gate ox i de.

Copyright by John Wiley & Sons 2003

MOSFETs - 6
 Drift Velocity Saturation

electron
drift velocity
Mobility also decreases because large
8 x 1 06
values of VGS increase free electron
cm/sec density.

At larger carrier densities, free carriers

collide with each other (carrier-carrier
4 electric
1.5x10 V/cm field scattering) more often than with lattice and
mobility decreases as a result.

In MOSFET channel, J = q n n E
Mobilty decreases, especially via carrier-
= q n v n ; velocity v n = n E
carrier scattering leead to linear transfer
curve in power devices instead of square
Velocity saturation means that the law transfer curve of logic level MOSFETs.
mobility n inversely proportional to
electric field E.
Copyright by John Wiley & Sons 2003
MOSFETs - 7
 Channel-to-Source Voltage Drop

VGS = VGG = Vox + VCS(x) ;

V + VCS(x) = ID1RCS(x)
GG V
+ DD1 I
D1

Vo x(x) Larger x value corresponds be being

closer to the drain and to a smaller
V (x) inversion
+ Vox .
N CS
x depletion

P
Smaller Vox corresponds to a smaller
N channel thickness. Hence reduction in
N+ channel thickness as drain is
approached from the source.

Copyright by John Wiley & Sons 2003

MOSFETs - 8
 Channel Pinch-off at Large Drain Current
Appar ent di l emma of
channel di sappear i ng at
+
V D D 2+ I
D2 dr ai n end for l ar ge I D
avoi ded.
V Vo x(x)
GG
1. Lar ge el ectr i c fi el d at dr ai n
V (x) inversion
+ end or i ented par al l el to
N CS
depletion dr ai n cur r ent fl ow. Ar i ses
x
velocity fr om l ar ge cur r ent fl ow i n
saturation channel constr i cti on at
P region dr ai n.
N
N+ 2. Thi s el ectr i c fi el d tak es
over mai ntenance of
mi ni mum i nver si on l ayer
thi ck ness at dr ai n end.
I D2 > I D1 so V CS2(x ) > V CS1(x ) and thus channel
nar r ower at an gi ven poi nt. Lar ger gate- sour ce bi as
V GG postpones fl atteni ng
Total channel r esi stance fr om dr ai n to sour ce of I D vs V DS unti l l ar ger
i ncr easi ng and cur ve of I D vs V DS for a fi x ed V GS
val ues of dr ai n cur r ent ar e
fl attens out. r eached.
Copyright by John Wiley & Sons 2003
MOSFETs - 9
 MOSFET Switching Models for Buck Converter
V
d D

Io
r
D DS(on)
F

R
G
Cgd
+ G
V
GG
C
gs

S
Buck converter using power MOSFET.
D
MOSFET equivalent circuit valid for
on-state (triode) region operation.
C
gd

G I = f(V )
D GS
C
gs
MOSFET equivalent circuit valid for off-
S state (cutoff) and active region operation.
Copyright by John Wiley & Sons 2003
MOSFETs - 10
MOSFET Capacitances Determining Switching Speed

gate
source

C gs C
gd
C
N+ gd2
N+ P idealization
C
P gd
Cd s

N actual
C gd1
drain-body
N+ depletion layer
v
v = v 200 V DS
GS DS
drain

Gate-source capacitance Cgs approximately

constant and independent of applied voltages.

Gate-drain capacitance Cgd varies with applied

voltage. Variation due to growth of depletion layer
thickness until inversion layer is formed.
Copyright by John Wiley & Sons 2003
MOSFETs - 11
 Internal Capacitances Vs Spec Sheet Capacitances

MOSFET internal capacitances Reverse transfer or feedback capacitance

C gd C
bridge
G D
+V -
C gs Cd s b

S C gd

Bridge balanced (Vb=0) Cbridge = Cgd = C rss

Input capacitance
G D Output capacitance

G D
C iss

S
C oss

S
C iss = C gs + C gd

C oss = C gd + C d s
Copyright by John Wiley & Sons 2003
MOSFETs - 12
 Turn-on Equivalent Circuits for MOSFET Buck Converter
Vi n Vi n
Equi val ent ci r cui t Equivalent cir cuit
dur i ng td(on). dur ing tr i .
D I o
F D I o
F

C
DC C
R C gd1 DC
G R C gd1
G
+
V i
G +
GG C V
gs i
GG G C
gs

Vi n
Equi val ent ci r cui t Equivalent cir cuit
V
dur i ng tfv1. in
dur ing tfv2.
I o I o r
DS(on)
R
G
R Cg d 1
G +
V i C
G gs
+ GG C gd2
V i
GG G

Copyright by John Wiley & Sons 2003

MOSFETs - 13
 MOSFET-based Buck Converter Turn-on Waveforms
V
GG+
t = R (C + C )
G gd1 gs

v (t)
GS
V
G S , Io

t = R (C + C )
G gd2 gs
V
GS(th)

i (t)
G

t
Charge on C
Charge on C + Cg d gd
gs

V in
t
fv2
Free-wheeling diode
assumed to be ideal.
v (t)
DS
i (t)
(no reverse recovery
D
current).
Io

t
t ri V t
d(on) t fv1 DS(on)

Copyright by John Wiley & Sons 2003

MOSFETs - 14
 Turn-on Gate Charge Characteristic
V
Vgs V V d
d1 d2
Vgs,on
I
I V D1
d3 Cgd
V + D1
t g
mo + +
Specified I Vgs C C V
D1 gs ds ds
- -

Q gate g (V - V )
Q Q m gs t
on p
Vgs V + I /gm
Q t D1
(Vt+ID1/gm) T1
V
Qon = ![Cgs(Vgs)!+!Cgd(Vgs)]!Vgs!dVgs
t
t
Vgs,off Vgs,off V
gs,on
Vds,on I
d
! I
Qp = !Cgd(Vds)!Vds dVds D1
t
Vd
V
Vgs,on ds
QT = Qon + Qp + ![Cgs(Vgs)!+!Cgd(Vgs)]!Vgs!dVgs
V
V ds,on
(Vt+ID1/gm) d
t
Copyright by John Wiley & Sons 2003
MOSFETs - 15
Turn-on Waveforms with Non-ideal Free-wheeling Diode

Vi n
Io i D (t)
F
Io + I rr

I rr t
C gd1
I rr R
G
i (t)
D +
t rr V i
Io
GG G Cgs

t t
ri

V Equivalent circuit for

GS,I
V o
GS(th) estimating effect of free-
t wheeling diode reverse
recovery.
Vin
v (t)
DS

t
Copyright by John Wiley & Sons 2003
MOSFETs - 16
 MOSFET-based Buck Converter Turn-off Waveforms

t 2= R (C
G gd2
+ C )
gs
v (t)
GS t1= R (C + C )
G gd1 gs Assume ideal fr ee-
V
GG V V
GS(th)
w heeling diode.
G S , Io

Essentially the
t inver se of the tur n- on
i (t)
G
pr ocess.

t
d(off)
v (t)
DS Model quanitatively
i (t)
D using the same
I o
V
in equivalent cir cuits as
for tur n- on. Simply
use cor r ect dr iving
t voltages and initial
t
rv2
t rv1 t fi conditions

Copyright by John Wiley & Sons 2003

MOSFETs - 17
 dV/dt Limits to Prevent Parasitic BJT Turn-on
gate D
source

Cg d
+ N+ G
N parasitic
BJT
P P
Cg d
N
+
N S
dVDS
drain
Large positive Cgd
dt
could turn on parasitic BJT.
D
L+
Turn-on of T+ and reverse recovery of Df- will
D
F+ dv DS
produce large positive Cgd in bridge circuit.
T+ I o dt

D
L- Parasitic BJT in T- likely to have been in reverse
active mode when Df- was carrying current. Thus
DF - stored charge already in base which will increase
T-
dv DS
likeyhood of BJT turn-on when positive Cgd is
dt
generated.
Copyright by John Wiley & Sons 2003
MOSFETs - 18
 Maximum Gate-Source Voltage
V GS(max) = maxi mum per mi ssi bl e gate-
sour ce vol tage.

I f V GS >V GS(max) r uptur e of gate oxi de by

l ar ge el ectr i c fi el ds possi bl e.

EBD(oxi de) 5- 10 mi l l i on V/cm

Gate oxi de ty pi cal l y 1000 anstr oms thi ck
V GS(max) < [5x106] [10- 5] = 50 V
Ty pi cal V GS(max) 20 - 30 V

Stati c char ge on gate conductor can r uptur e

gate oxi de
Handl e MOSFETs w i th car e (gr ound
y our sel f befor e handl i ng devi ce)
Pl ace anti - par al l el connected Zener di odes
betw een gate and sour ce as a pr otecti ve
measur e

Copyright by John Wiley & Sons 2003

MOSFETs - 19
 MOSFET Breakdown Voltage
depletion layer boundary depletion layer boundary
without field plate with field plate action
action of gate electrode of gate electrode

+ +
N N N
P P

+
N

BVDSS = drain-source breakdown

2. Appropriate length of drain drift region
voltage with VGS = 0

Caused by avalanche breakdown of

3. Field plate action of gate conductor
drain-body junction overlap of drain region

Achieve large values by 4. Prevent turn-on of parasitic BJT with

body-source short (otherwise BVDSS
1. Avoidance of drain-source reach-
through by heavy doping of body = BVCEO instead of BVCBO)
and light doping of drain drift region

Copyright by John Wiley & Sons 2003

MOSFETs - 20
 MOSFET On-state Losses
gate
source
accumulation
channel layer
resistance resistance
+
N N+
P
P
I drift region
source region D resistance
N
resistance

drain region
resistance
+
N

drain

On-state power dissipation Pon = rDS(on) dominated by drain drift resistance

for BVDSS > few 100 V
Io2 rDS(on)
Vd BVDSS2
rDS(on) = 3x10-7
!ID A
Large VGS minimizes accumulation
rDS(on) increases as temperature increases.
layer resistance and channel
Due to decrease in carrier mobility with
resistance increasing temperature.

Copyright by John Wiley & Sons 2003

MOSFETs - 21
 Paralleling of MOSFETs

Rd
MOSFETs can be easily
paralleled because of Q
1
positive temperature G
coefficient of rDS(on).

Positive temperature coefficient leads to thermal

stabilization effect.

If rDS(on)1 > rDS(on)2 then more current and thus

higher power dissipation in Q2.

Temperature of Q2 thus increases more than

temperature of Q1 and rDS(on) values become
equalized.
Copyright by John Wiley & Sons 2003
MOSFETs - 22
 MOSFET Safe Operating Area (SOA)

log ( i )
D

I
DM No distinction betw een
-5
FBSOA and RBSOA. SOA
10 sec
is squar e.
10 - 4 sec
Tj , m a x FB = for w ar d bias.
10
-3
sec
V GS 0.

RB = r ever se bias.
DC
V GS 0.

BV
DSS
No second br eakdow n.

log ( v )
DS

Copyright by John Wiley & Sons 2003

MOSFETs - 23
Structural Comparison: VDMOS Versus COOLMOS
source
gate
cond
uctor

N+ N+ N+ N+
+ +
P P
Conventional
vertically oriented
N-
power MOSFET

N+

drain

source
gate
cond
uctor

COOLMOS structure
N+ N+ N+ N+
P P (composite buffer structure,
b b
W super-junction MOSFET,
P N P super multi-resurf
MOSFET)
b b b
Vertical P and N regions of
width b doped at same
N+ density (Na = Nd)
drain
Copyright by John Wiley & Sons 2003
MOSFETs - 24
 COOLMOS Operation in Blocking State
source
gate
cond COOLMOS structure partially
uctor
depleted.
N+ N+ N+ N+
P P
b b Arrows indicate direction of
depletion layer growth as device
N -
P
turns off.
V1
P
+ Note n-type drift region and
N+
adjacent p-type stripes deplete
drain uniformly along entire vertical
length.

source
gate
cond
COOLMOS structure at edge
uctor of full depletion with applied
N+ N+ N+ N+ voltage Vc. Depletion layer
P P
b b
N reaches to middle of vertical P
and N regions at b/2.
Ec Ec -
P P
Vc Using step junction formalism,
+ Vc = (q b2 Nd)/(4 e) = b Ec,max/2
N+
Keep Ec,max EBD/2. Thus
drain Nd ( e EBD)/(q b)

Copyright by John Wiley & Sons 2003

MOSFETs - 25
 COOLMOS Operation in Blocking State (cont.)
source
gate
cond
uctor

N+ N+ N+ N+
P P P
b N b
Ev Ev
Ev
P -
P
V
Ec Ec
+

N+

drain
V > Vc

For applied voltages V > Vc, vertically oriented electric field Ev begins to grow in depletion region.

Ev spatially uniform since space charge compensated for by Ec. Ev V/W for V >> Vc.

Doping level Nd in n-type drift region can be much greater than in drift region of conventional
VDMOS drift region of similar BVBD capability.

At breakdown Ev = EBD 300 kV/cm ; V = BVBD = EBDW

Copyright by John Wiley & Sons 2003
MOSFETs - 26
 COOLMOS Operation in ON-State

source
gate
cond
uctor
On-state specific resistance ARon [-cm2]
N+ N+ Ro n N+ N+
P P much less than comparable VDMOS
b b because of higher drift region doping.

P P -
V1 COOLMOS conduction losses much
N
less than comparable VDMOS.
+

N+

drain
ID R
L

Ron A = W/(q nNd) ; Recall that Nd = (e EBD)/(q b)

Breakdown voltage requirements set W = BVBD/ EBD.

Substituting for W and Nd yields Ron A = (b BVBD)/(e n EBD2)

Copyright by John Wiley & Sons 2003

MOSFETs - 27
 Ron A Comparison: VDMOS versus COOLMOS

COOLMOS at BVBD = 1000 V. Assume b 10 m. Use EBD = 300 kV/cm.

Ron A = (10-3 cm) (1000 V)/[ (9x10-14 F/cm)(12)(1500 cm2 -V-sec)(300 kV/cm)2]
Ron A = 0.014 -cm . Corresponds to Nd = 4x1015 cm-3

Typical VDMOS, Ron A = 3x10-7 (BVBD)2

Ron A = 3x10-7 (1000)2 = 0.3 -cm ; Corresponding Nd= 1014 cm3

Ratio COOLMOS to VDMOS specific resistance = 0.007/0.3 = 0.023 or approximately 1/40

At BVBD = 600 V, ratio = 1/26.
Experimentally at BVBD = 600 V, ratio is 1/5.

For more complete analysis see: Antonio G.M. Strollo and Ettore Napoli, Optimal ON-Resistance
Versus Breakdown Voltage Tradeoff in Superjunction Power Device: A Novel Analytical Model, IEEE
Trans. On Electron Devices,Vol. 48, No. 9, pp 2161-2167, (Sept., 2001)

Copyright by John Wiley & Sons 2003

MOSFETs - 28
 COOLMOS Switching Behavior
MOSFET witching waveforms for clamped inductive load.
Larger blocking voltages Vds > depletion
voltage Vc, COOLMOS has smaller Cgs, Cgd,
and Cds than comparable (same Ron and
BVDSS) VDMOS.

Small blocking voltages Vds < depletion

v (t)
voltage Vc, COOLMOS has larger Cgs, Cgd,
GS V GS,Io
and Cds than comparable (same Ron and
V BVDSS) VDMOS.
GS(th)

t
Effect on COOLMOS switching times
relative to VDMOS switching times.
v (t) V
DS V Turn-on delay time - shorter
DS(on)
d
Current rise time - shorter
Voltage fall time1 - shorter
t
td ( o n ) t r i t fv1 t t rv1 tfi Voltage fall time2 - longer
fv2 t d(off)
Turn-off delay time - longer
i (t) t rv2 Voltage rise time1 - longer
D Io
Voltage rise time2 - shorter
t Current fall time - shorter
Copyright by John Wiley & Sons 2003
MOSFETs - 29
 PSPICE Built-in MOSFET Model

Circuit components

Drain

RD RG, RDS, RS, RB, and RD = parasitic

Cgb
ohmic resistances
Cbd

Cgs Cgd, and Cgb = constant voltage-

Cgd independent capacitors

RG RB
RDS Idrain Cbs and Cbd = nonlinear voltage-
Gate Bulk dependent capacitors (depletion layer
capacitances)
Cgs Cbs

Idrain = f(Vgs, Vds) accounts for dc

RS characteristics of MOSFET
Source

Model developed for lateral (signal level)

MOSFETs
Copyright by John Wiley & Sons 2003
MOSFETs - 30
 Lateral (Signal level) MOSFET

Body-source short Cgs G Cgd

Body-source short keeps Cbs constant.
S D

N+ N+
C bg
Body-source short puts Cbd between drain and
source.
P
C bs C bd
Variations in drain-source voltage relatively
Drain-body small, so changes in Cbd also relatively small.
Source-body B
depletion layer
depletion layer

Capacitances relatively independent of terminal

Cgs, Cbg, Cgd due to electrostatic
voltages
capacitance of gate oxide. Independent
of applied voltage
Consequently PSPICE MOSFET model has
voltage-independent capacitances.
Cbs and Cbd due to depletion layers.
Capacitance varies with junction voltage.
Copyright by John Wiley & Sons 2003
MOSFETs - 31
 Vertical Power MOSFET

Body-
source source gate
short
Cg s
Cbg

N+
Cg d N+
Cbs P
P
Cb d N
N+

drain
drain-body depletion layer
Drain-drift region and large drain-source
voltage variations cause large variations in MOSFET circuit simulation
drain-body depletion layer thickness models must take this variation
into account.
Large changes in Cgd with changes in drain-source
voltage. 10 to 100:1 changes in Cgd measured in high
voltage MOSFETs.

Moderate changes in Cgb and Cbs.

Copyright by John Wiley & Sons 2003
MOSFETs - 32
 Inadequacies of PSPICE MOSFET Model
4
MTP3055E
C gd V = 0
GS Cgs and Cgd in PSPICE model are
[nF] constant independent of terminal voltages
2 SPICE model

In vertical power MOSFETs, Cgd varies

Motorola subcircuit model substantially with terminal voltages.

0
0V
10V V 20V 30V
DS

60V
MTP3055E V
DS
Comparison of transient response of drain-
40V
source voltage using PSPICE model and
Motorola an improved subcircuit model. Both
SPICE
20V subcircuit model models used in same step-down converter
model circuit.
0V
0s 100ns 200ns 300ns
Time

Copyright by John Wiley & Sons 2003

MOSFETs - 33
 Example of an Improved MOSFET Model
Developed by Motorola for their TMOS line of
power MOSFETs

Drain M1 uses built-in PSPICE models to describe

dc MOSFET characteristics. Space charge
LDRAIN capacitances of intrinsic model set to zero.
DGD
CGDMAX
Space charge capacitance of DGD models
RDRAIN1 voltage-dependent gate-drain capacitance.
RGDMAX CGDMAX insures that gate-drain capacitance
RDRAIN2
does not get unrealistically large at very low
LGATE RGATE DBODY
drain voltages.
M1 DBODY models built-in anti-parallel diode
Gate CGS inherent in the MOSFET structure.
RDBODY
RSOURCE CGS models gate-source capacitance of
MOSFET. Voltage dependence of this
LSOURCE capacitance ignored in this model.
Resistances and inductances model parasitic
Source components due to packaging.
Many other models described in literature. Too
numerous to list here.
Copyright by John Wiley & Sons 2003
MOSFETs - 34
 Another Improved MOSFET Simulation Model
Drain
M2 and M3 are SPICE level 2
L
D
MOSFETs used along with Voffset to
model voltage dependent behavior of
R Cgd.
d

M2 M3
JFET Q1 and Rd account for voltage drop
Dsub
V offset Q
1
in N- drain drift region
+
-

Gate M1
Dsub is built-in SPICE diode model used
LG R
G to account for parasitic anti-parallel diode
in MOSFET structure.
RS

LS
Source
LG, RG, LS RS, LD, RD - parasitic
inductances and resistances
M1= intrinsic SPICE level 2 MOSFET with no
parasitic resistances or capacitances.
Copyright by John Wiley & Sons 2003
Reference - "An Accurate Model for
Power DMOSFETs Including Inter-
electrode Capacitances", Robert Scott,
Gerhard A. Frantz, and Jennifer L.
Johnson, IEEE Trans. on Power
Electronics, Vol. 6, No. 2, pp. 192-198,
(April, 1991)
MOSFETs - 35