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Interactive Transformerless Photovoltaic Power Plant

Sumit K. Chattopadhyayl Student Member iEEE, Chandan Chakrabort/ Senior Member iEEE and

Bikash C Pae Senior Member iEEE,

1 &2Department of Electrical Engineering, Indian Institute of Technology Kharagpur, 721302, INDIA

3 Department of Electrical and Electronic Engineering, Imperial College London, UK

lemail: sumitkc1981@gmail.com 2email: chakraborty@ieee.org 3email: b.pal@imperial.ac.uk

Abstract: Hybrid multilevel inverter topology is proposed for at higher frequency. This is one of the key factors to make

high power transformer less grid interactive photovoltaic power photovoltaic converters different from general purpose

plant. Cascaded H-Bridge & Neutral Point Clamp topologies are inverters. Photovoltaic converters are typically having

hybridized to form this topology. Trinary asymmetric ratio of dc isolation voltage of 1000Y. The DC bus voltage is usually

bus voltage is adapted for increasing the number of levels. Only

kept within 800Y in order to avoid insulation failure. So, for

three basic switching stages (two single phase H bridge cell and

higher power rating of the inverter (above 80kW), the

an NPC structure with common source for all phases) are used in

photovoltaic array current has to be high (above 100A). In

each phase to obtain 53 levels in line to line voltage using trinary

voltage rato. NPC structure with a common DC bus for all

order to satisfy IEEE 519 harmonic standard [10], high

phases is connected to main photovoltaic (PV) array. This is kept frequency switching cannot be avoided in this topologies: This

at highest voltage to optimize the DC bus capacitor rating, and to causes higher switching losses, higher electromagnetic

reduce dc bus voltage ripple to increase MPPT efficiency. Third interference (EMI), increased cost of switch with high device

harmonic voltage is injected in order to increase the number of stresses and expensive gate drivers. Also costly, heavy and

voltage levels further, and to increase the DC bus utilization. bulky thermal management system is required owing to heavy

Increasing the number of voltage levels gives more flexibility to

switching losses.

reduce Total Harmonic Distortion (THD) of the system and in

turn reduction in cost and size of the power filter. Switching loss So, increasing the efficiency of solar cell will not be enough to

is optimized by operating the inverter at fundamental frequency.

build highly efficient photovoltaic power generation system.

Nearest voltage level control modulation technique is adapted.

The power conditioning unit should also be efficient and

The converter is simulated in MATLAB/Simulink. The results

reliable (many times photovoltaic power plants operate at

are validated through prototype experimentation in the

laboratory.

lower efficiency because of inverter failure). The maximum

power point tracking (MPPT) efficiency should also be very

Index Terms: Asymmetric hybrid multilevel inverter, grid high.

connected photovoltaic system, third harmonic injection, nearest

voltage level control, MPPT This paper analyses the practical challenges to enhance the

performance of MPPT and the efficiency of the power

I. INTRODUCTION conditioning unit. A hybrid multilevel inverter topology is

proposed. Control and sizing aspects to maximize the

The global capacity of photovoltaic power generation is

efficiency and optimize the cost of the inverter is discussed.

rapidly increasing [1] [2]. In last two decades, the research

As it is well known that, the cost of the power conditioner unit

and development for increasing the efficiency of photovoltaic

is typically about 9% of the total establishment cost of a large

power generation and reducing the cost/kW of energy is also

photovoltaic power generation system, cost optimization of

becoming a demanding subject of research.

the converter is necessary.

Presently almost all photovoltaic converters in the market [3]

The paper is organized as follows: Section I has explained the

[9] are operating above 5kHz frequency. The PY modules are

importance, motivation and challenges of developing efficient

having high terminal-to-body stray capacitance (typically few

and cost optimized power converter for grid connected

hundreds of nano Farad per kW). This requires some

photovoltaic systems. Section II proposes a suitable topology

topological modification to avoid line to earth leakage current

of multilevel inverter, its switching technique and a method to ripple, and increases the requirement of DC bus capacitors.

increase the line to line voltage and number of levels in line to With a lower DC bus capacitance the voltage ripple will be

line voltage. In Section III, the power distribution ratio/sizing higher: results lower MPPT efficiency. One end of the CHB

of PV array is discussed. Section IV deals with simulation. can be connected with NPC structure, which can be connected

Whereas, the experimental results are presented in Section V. to a common dc source for all phases. If this NPC structure is

Section VI concludes the work. kept at highest voltage, most of the power will be delivered by

the DC bus connected to this structure, which will have

II. TOPOLOGY, MODULAnON AND CONTROL minimum DC bus voltage ripple. This will increase the MPPT

efficiency.

A. Selection o/Topology

was not practical when the capacity of photovoltaic power J

plant was not high enough [11]. Presently there are hundreds

CellI

V

J

of multi mega watt photovoltaic power plants are operating in

the globe, which requires large size photovoltaic inverter.

Multilevel inverter can be a good choice for photovoltaic

CHB

application, because of its high power quality, low EMI

problem and low switching frequency [12].

Cell 2

multilevel inverter in grid connected photovoltaic system. In

order to improve power quality and reduce EMI problems, it is J

required to increase the number of levels. The number of

switches becomes too high with higher number of voltage CHB

increases the number of gate drivers and higher conduction

loss of devices. All above factor will have negative impact on J Ql

cost, reliability (reliability is inversely proportional to number 9V

J Q4

The asymmetric structure of multilevel inverter can increase Cell 3

switches. Trinary asymmetry can give highest number of

voltage levels for a given number of stages. In trinary

asymmetry, the ratio of voltage level is: 1: 3: ... : 3". In [13],

it is shown that, in trinary asymmetry, most of the power

(nearly 80% when the modulation index is close to unity) is

delivered from the highest voltage cell. The highest voltage

cell operates at fundamental frequency of the inverter output Fig. 1. Circuit diagram of one phase

voltage. This enables the use of GTO or Thyristor as a

switching device: Results in reduction of conduction loss, and The complete circuit diagram of one phase is shown in Fig. 1.

reduction in device and driver cost. Handling most of the Where, the highest voltage cells for all three phases are

power in fundamental frequency switching also reduces connected to a common DC source, owing to the NPC

switching loss, even if the loss per switching of Thyristor is structure. It can be noted that, in trinary voltage ratio, if

much higher than that of IGBT. There are three basic number of cells are more than three, there will be negligible

topologies of multilevel inverter: Cascaded H-Bridge (CHB), power from the lowest voltage cell, and will unnecessarily

Neutral point clamped (NPC) and Flying capacitor (FC). Out increase the conduction and switching losses, without

of which asymmetric structure is convenient to achieve in significant increase in power quality. This structure will be

CHB structure only. But in CHB, it is required to keep isolated beneficial to use in case of three phase power generation only.

DC bus for every H-Bridge. This increases the DC bus voltage For single phase system, this topology will not give any extra

5075

advantage compare to CHB MLI, this will only add two more The requirement of computational resource is negligible,

diodes to the circuit compare to CHB MLI. compare to SVM technique.

B. Selection ofModulation Technique The third harmonic injected phase voltages (Red and Yellow

colored) and corresponding line to line voltage (Green

Nearest voltage level control modulation technique is selected colored) is shown in Fig. 2. The peak magnitude of line to line

as a method of generating the switching pulses. In this voltage is just double of peak magnitude of phase voltage.

technique, the output voltage level should be nearest to the

reference voltage. In nearest voltage level control, the number 400

I

300

avoid large THD. In this design, the number of voltage levels

in line to neutral is 27. Nearest voltage level control gives

excellent dynamic performance [15], which is required for

Q,j

grid synchronization and highly efficient MPPT. Also the ell

simple algorithm helps to realize robust control with less -.

....

0

complexity. This modulation technique is easier to implement >-

when the input reference will be taken from the real world.

The real world signal may not be of fixed frequency and fixed ,, ,,

-300

voltage.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _. ---------------- _ . -- ----- -------

-400 L-__----,--:'-c:

- :--__--:-"-.,,-__

--- --,---,'=-__----:-'

0,04 0 ,045 0.05 0.055 0.06

C. Third Harmonic injection

Time in Second

Third harmonic voltage is injected in phase voltage in order to Fig. 2. Simulated 53 level line to line voltage and

have further increase in number of levels in line to line corresponding 27 level phase voltages

voltage. The expression of third harmonic injected modulating

wave is given by III. POWER DISTRIBUTION RATIO AND MPPT

V(t) VMx{1.15sin(wt)+O.19sin(3wt)}

= (1) In order to achieve MPPT of every module connected to the

proposed inverter, the number of modules to be connected to

Third harmonic part of the modulating wave gets cancelled out various DC busses of the inverter will be determined by the

in line to line voltage. As a result, the expression for power distribution ratio of the inverter and power rating of the

modulating wave of line to line voltage becomes inverter.

(2) :Refel'ence :

pII\..- ::-.- i-----------

. . ........ .

Where, VM is the voltage obtained by summing up the voltages 150 - -- - -- -- --- -- ; ------- -------j.--------- -

I. ,, '

:.....- : .. :

of all the cells of a phase. Output phase voltage of a trinary ... illjtcttd l'erel'ence

100 - -- - - -- :- -/'> --- ----------'--------t ----:-

t

2x (9+3+1) +1=27 levels per phase and nearest integer of : ,. .-...

9V(18 volt)

3V(36 volt)

2x-Y3x(9+3+1)+1;:::;45 levels in line to line voltage. From 50 --A--

,

-------,,----- : -------

!, .

equation 2, it can be seen that, If third harmonic is injected,

I [Jui

.: LJ

the same topology can give 2x2x (9+3+1) +1=53 levels in line

't+'--- -c

: :

O

to line voltage. The space vector modulation (SVM) could V(12voll)

also give same number of voltage levels in line to line voltage. -50

0.02 0.021 0.022 0.023 0.024 0.025

But, SVPWM involves significantly higher complex algorithm

Time in second -------:::o

for so many voltage levels; involves significantly high

computational resource for real time system. Since third Fig. 3. Reference phase voltage, corresponding third

harmonic is injected with nearest voltage level control, it harmonic injected reference voltage in digitized form

requires only comparators to generate the desired waveforms. and cell voltages for a quarter cycle

5076

Power distribution ratio is independent of power factor [16]. IV. MODELING AND SIMULA nON

Hence, if it is possible to find the power distribution ratio of

switching cells of various voltage levels at unity power factor, Two arm IGBT-Diode based cells are used as basic switching

it will be possible to find the power distribution ratio of cells to form H-bridge as shown in Fig. 4. And two single arm

switching cells of various voltage levels at other power factors IGBT-Diode based cells are connected in series with clamping

as well. Power distribution ratio will have quarter wave diodes to form NPC structure as shown in Fig. 5. Based on the

symmetry in unity power factor. In Fig. 3, the reference phase combination of these two basic switching cells, the topology is

voltage, corresponding third harmonic injected reference formed as shown in Fig. 1. A switching table is formed to

voltage in digitized form and corresponding cell voltages operate the inverter in various voltage levels as shown in

shown for a quarter cycle. The angles 91 to 915 can be found Table-I. Minimum voltage of 12V is taken as dc bus voltage

out by putting the magnitudes of voltages during those instants for lowest voltage CHB, consequently 36V is the dc bus

in to equation 1. If it is assumed that the phase current of the voltage for medium voltage CHB cell and 108V is the dc bus

inverter is ]ph(t)=]Mxsin(wt), then the power delivered by voltage for NPC structure with respect to neutral point. Grid is

highest voltage cell (9V in this case) in a quarter cycle at simulated with three phase ac source. Line impedance is

modulation index of 1 will be: simulated with R-L series branch. Neutral point of the grid is

kept isolated from the neutral point of the inverter for blocking

(3) the third harmonic current component. The fundamental

component of the modulating wave leads the grid voltage in

Similarly the power delivered by medium voltage cell (3V in order to supply active power to the grid. The phase angle of

this case) will be: the reference wave of the inverter is controlled for controlling

power flow.

OS . Os . 90 .

P3V= V IM{ Jr02 sme de - Jros sme de + JrOll sme de}

+

(4)

..------F=--A

will be: t---B

Py

02 .

VIM { Jr01 sme de - r03 os

J 2 sine de + J sine de-

J Q4

0 04

r0 6 . r Os . 09 . Oll

Jo sme de + J

s 07

sme de - Jros sme de + JrOlO sine de-

2 . 90

r01 013

J

Oll

sme de + Jr014 sine de - J01S sine de} (5)

Fig. 4. Basic Switching Cell of CHB

approximately: Ql

Q4

phases) for both medium and lowest voltage stages. So, the

Q2

power distribution ratio for each medium voltage H-bridge as

a percent of output power will be 7.5% and power distribution

ratio for lowest voltage H-bridges as a percent of output power Q3

will be 0.833% approximately.

busses must follow this power distribution ratio to achieve Fig. 5. Basic switching cell of NPC structure

MPPT of each PV module.

5077

firing time of two inverter cells during voltage level transition.

The duration is typically within the range of 10 !l sec. The LiR

CellI (V) Cell2 (3V) Cell3 (9V) time constant of the load was kept about 400 !l sec; which can

CHB CHB NPC be about 1000 !l sec for grid tied inverter, as the inverter will

QQQ Q Q Q Q Q Q Q Q

Level 1 2 3 4 1 2 4 1 2 3 4

I(-I3V) 0 1 1 0 0 1 1 0 0 1 1 0 Tek J'L II Trig'd M Pos: 8.440ms CH2

2(-I2V) 1 0 1 0 0 1 1 0 0 1 1 0 +

Couplig

3(-l1V) 1 0 0 1 0 1 1 0 0 1 1 0 lmJ

4(-IOV) 0 1 1 0 1 0 1 0 0 1 1 0 BW Limit

mi

5(-9V) 1 0 1 0 1 0 1 0 0 1 1 0 200MHz

6(-8V) 1 0 0 1 1 0 1 0 0 1 1 0 Volts/Div

7(-7V) 0 1 1 0 1 0 0 1 0 1 1 0 EmlI

8(-6V) 1 0 1 0 1 0 0 1 0 1 1 0 Probe

10X

9(-5V) 1 0 0 1 1 0 0 1 0 1 1 0 Voltage

IO(-4V) 0 1 1 0 0 1 1 0 1 0 1 0 Ivert

11(-3V) 1 0 1 0 0 1 1 0 1 0 1 0 WiI

CH2+50.0V M 2.50ms CH3 .I -72.0V

I2(-2V) 1 0 0 1 0 1 1 0 1 0 1 0 CH3+50.0V 3-Apr-1213:16 150.107Hz

I3(-V) 0 1 1 0 1 0 1 0 1 0 1 0

14(0) 1 0 1 0 1 0 1 0 1 0 1 0 Fig. 5. 53 Level line to line voltage and corresponding 27 level

I5(V) 1 0 0 1 1 0 1 0 1 0 1 0 phase voltage

I6(2V) 0 1 1 0 1 0 0 1 1 0 1 0

Tek J'L ii Trig'd M Pos: 8.680ms CH1

17(3) 1 0 1 0 1 0 0 1 1 0 1 0 +

Couplig

18(4) 1 0 0 1 1 0 0 1 1 0 1 0 I!I!l

BW Limit

19(5) 0 1 1 0 0 1 1 0 1 0 0 1

mi

20(6) 1 0 1 0 0 1 1 0 1 0 0 1 200MHz

21(7) 1 0 0 1 0 1 1 0 1 0 0 1 Volts/Oiv

m

22(8) 0 1 1 0 1 0 1 0 1 0 0 1 Probe

23(9) 1 0 1 0 1 0 1 0 1 0 0 1 100X

Voltage

24(10) 1 0 0 1 1 0 1 0 1 0 0 1 Invert

25(11) 0 1 1 0 1 0 0 1 1 0 0 1 mi

CH1 67.0V M 2.50ms CH1 .I 75.4V

26(12) 1 0 1 0 1 0 0 1 1 0 0 1 CH4+5.00A 6-Apr-12 03:17 57.1837Hz

27(13) 1 0 0 1 1 0 0 1 1 0 0 1

Table-I: The sWltchmg table of proposed hybnd MLI Fig. 6. Line to line voltage and corresponding line current

+

Pos: 635,OHz MATH

Operation

=- IW

The simulated results are verified through laboratory prototype o

....

rFl

1104

.

and found as per expectation. dSPACE is used to Source

.

m

develop the controller of the prototype. Semikron make trench :s

gate IGBT is used to develop the inverter stacks. Semikron

0..'

make SKHI 22AR gate drivers are used to drive the IGBTs.

: M>

Presently DC busses are fed from DC source. A photovoltaic o

,...; .

Window

'-' IDi1IiI!J

emulator is under development. MPPT efficiency will be

. J

FFT

W

verified through PV emulator. om

_

CH410,OdB

__ LL J L L _ L ____________L_________J__

125Hz (2.50kS/s) Hanning

The line voltage and corresponding voltage of one of the

6- Apr-12 02: 53 50,0358Hz

.=:

phase is shown in Fig. 5. This matches with the simulated

line voltage and phase voltage waveform as observed in

Frequency in Hz (125 Hz per division)

Fig. 2. Occasional glitches are observed in line and phase

Fig. 7. FFT of line current

voltage in Fig. 5. and in Fig. 6. These are due to mismatch of

5078

modulation technique improves the dynamic performance and

reduces the computational burden significantly as compare to

space vector modulation.

ACKNOWLEDGEMENT

Dept. of Science and Technology (DST), Govt. of India,

through the project "Stability and Performance of

Photovoltaics" with joint collaboration of DST, India and

Research Council (RC), UK.

REFERENCES

[I] http://www.thinkglobalgreen.orgjSOLAR.html

http://www.pvresources.com/en/top50pv.php

US 2005/0286281 A I, 29 December 2005.

DE1022006010694 A II, 20 September 2007.

Number W02008015298, 2 July 2007

"Transformerless Inverter for Single-Phase Photovoltaic

Systems," Power Electronics, IEEE Transactions on , vo1.22, no.2,

pp.693-697, March 2007.

Fig. 8. Hardware setup E.; , "A New High-Efficiency Single-Phase Transformerless PV

Inverter Topology," Industrial Electronics, IEEE Transactions on,

vo1.58, no.I, pp.184-191, Jan. 2011.

be coupled to the grid with an inductor with very small

[9] Knaup, P., International Patent Application, Publication Number

resistance. The line current is shown in Fig. 6. The glitches WO 2007

observed in the line and phase voltages are having negligible [10] IEEE Recommended Practices and Requirements for Harmonic

Control in Electrical Power Systems," IEEE Std 519-1992, vol.,

no., pp.O_I, 1993

Fig. 7. The third harmonic component is 37db below the

[II] S.Kouro, M.Malinowski, K.Gopakumar, J. Pou, L. G.Franquelo,

fundamental: l.41% of fundamental, the seventh harmonic is B.W u, J. Rodriguez, M. A. Perez, J. l. Leon, , "Recent Advances

and Industrial Applications of Multilevel Converters," IEEE

nearly 40db below fundamental: 1% of fundamental. The

Transactions on Industrial Electronics" vo1.57, no.8, pp.2553-

THD is noted l.83%. The individual harmonic components 2580, Aug. 2010.

and THD are much below the harmonic limit specified in [12] S.Kouro, J.Rebolledo, J.Rodriguez, "Reduced Switching-

Frequency-Modulation Algorithm for High-Power Multilevel

IEEE 519 standard [10]. The overall view of the hardware Inverters," IEEE Transactions on Industrial Electronics" vol. 54,

setup is shown in Fig. 8. no.5, pp.2894-2901,Oct. 2007.

Multilevel Inverter for Traction Drives Using Only One DC

Supply," IEEE Transactions on Vehicular Technology" vol.59,

"Multilevel Voltage-Source-Converter Topologies for Industrial

Trinary asymmetric NPC-CHB hybrid topology can be a

Medium-Voltage Drives," IEEE Transactions on Industrial

prospective multilevel inverter topology for large and medium Electronics" vol.54, no.6, pp.2930-2945, Dec. 2007

size grid connected transformerless photovoltaic inverter. This [15] J. Dixon, J.Pereda, C. Castillo, and S. Bosch, "Asymmetrical

Multilevel Inverter for Traction Drives Using Only One DC

inverter will have higher efficiency owing to low frequency Supply," IEEE Transactions on Vehicular Technology" vol.59,

switching of power cells. Excellent power quality and low no.8, pp.3 736-3 743, Oct. 20 I0

[16] Perez, M.; Rodriguez, J.; Pontt, J.; Kouro, S.;, "Power Distribution

EMI are achieved due to large number of levels. Large number

in Hybrid Multi-cell Converter with Nearest Level

of voltage level also allows to use nearest voltage level control Modulation," Industrial Electronics, 2007. ISlE 2007. IEEE

with third harmonic injection as a modulation technique for International Symposium on, vol., no., pp.736-741, 4-7 June 2007

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