Rolling- digit Display

The output of each random number generator is a 4-bit binary number representing one of the binary
numbers representing one of the binary code values (1-F). Each digit will be displayed on a standard
seven-segment LED display. Therefore, a BCD-to-7-segment code converter will be inserted between
each number generator and display digit, as illustrated in fig.13.4.

A search of the TLL Data Book shows the functions 7446, 7447, 7448 and 7449 BCD-to-seven-segment
converters. The 7446 and 7447 drive display with active-low inputs(common-anode VLEDs ) and the
7448 and 7449 drive displays with active-low input (common cathode VLEDs). Let us select common-
cathode.

We shall select the 7448, resulting in the circuit of fig. 13.7. It should be noted that current-limiting
resistor may be needed between the 7448 outputs and the display inputs, depending on the input
current requirements of the display.

PAYOFF DISPLAY

The payoff display is identical to the rolling-digit display. A three- digit BCD number generated by the
payoff generator will be converted and displayed on three seven-segment LDs using a copy of the circuit
shown in fig.13.7.

Wager-Display

The payoff display is identical to the rolling-digit display. A three-digit BCD number generated by the
payoff generator will be converted and displayed on three seven-segment LEDs using a copy of the
circuit shown in fig.13.7.

Wager-Placement Switches

The wager must be made prior to pressing the play button. Transitions on the wager-placement
switches do not initiate any actions. There, simple nondebounced DIP switches can be used. A 2-bit
register will latch the positions of these switches at the time the play button is depressed to prevent the
wager from being changed once the game has begun. The circuit is shown in fig.13.8.
PAYOFF GENERATOR

If a winning combination is detected, the number of points won is a function of whether two or three of
the displayed digits match and the matching digit value.

In addition, the number of points is multiplied by a factor of 1 to 4, depending on the wager that was
placed on the wager switches.

There are six inputs to the winnings computation circuit:

1. A 3-bit number (1 to 7) corresponding to the matching digit, or all zeros if there were no
matching digits.
2. One bit One bit indicating whether there were two or three matching digits, assuming there was
at least one match.
3. A 2-bit number corresponding to the wager that was placed.

Since the number of points is a three digit decimal number, the winnings computation circuit will
have 12 output lines corresponding to three BCD digits.

To realize this circuit, a 64x12 PROM device could be used, that is, a PROM with 6 inputs. However,
64X12 is not a standard commercially available configuration; therefore, we will use two PROMs, an
82LS129A (256X4) to drive the hundreds digit and an 82LS135 (256X8) to drive the tens and units
digits. The complete payoff generator circuit is given in fig. 13.10, which shows the assignment of
signals to the 8-bit PROM address inputs and the PROM outputs.