H

0.5 Amp Output Current IGBT

Gate Drive Optocoupler

Technical Data

HCPL-3150

Features Applications ideally suited for driving power

0.5 A Minimum Peak Output Isolated IGBT/MOSFET IGBTs and MOSFETs used in
Current Gate Drive motor control inverter applica-
15 kV/s Minimum Common AC and Brushless DC Motor tions. The high operating voltage
Mode Rejection (CMR) at Drives range of the output stage pro-
VCM = 1500 V Industrial Inverters vides the drive voltages required
1.0 V Maximum Low Level by gate controlled devices. The
Switch Mode Power
Output Voltage (VOL) voltage and current supplied by
Supplies (SMPS)
Eliminates Need for this optocoupler makes it ideally
Negative Gate Drive suited for directly driving IGBTs
Description with ratings up to 1200 V/50 A.
ICC = 5 mA Maximum Supply The HCPL-3150 consists of a For IGBTs with higher ratings,
Current GaAsP LED optically coupled to the HCPL-3120 can be used to
Under Voltage Lock-Out an integrated circuit with a power drive a discrete power stage
Protection (UVLO) with output stage. This optocoupler is which drives the IGBT gate.
Hysteresis
Wide Operating VCC Range: Functional Diagram
15 to 30 Volts
N/C 1 8 VCC
500 ns Maximum Switching
Speeds
ANODE 2 7 VO
Industrial Temperature
Range: CATHODE 3 6 VO
-40C to 100C
Safety and Regulatory N/C 4
SHIELD
5 VEE
Approval:
UL Recognized Truth Table
2500 Vrms for 1 min. per VCC - VEE VCC - VEE
UL1577 Positive Going Negative-Going
VDE 0884 Approved with LED (i.e., Turn-On) (i.e., Turn-Off) VO
VIORM = 630 Vpeak
OFF 0 - 30 V 0 - 30 V LOW
(Option 060 only)
ON 0 - 11 V 0 - 9.5 V LOW
CSA Approved
ON 11 - 13.5 V 9.5 - 12 V TRANSITION
ON 13.5 - 30 V 12 - 30 V HIGH

A 0.1 F bypass capacitor must be connected between pins 5 and 8.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.

5965-4780E 1-197
Ordering Information
Specify Part Number followed by Option Number (if desired)
Example
HCPL-3150#XXX
No Option = Standard DIP package, 50 per tube.
060 = VDE 0884 VIORM = 630 Vpeak Option, 50 per tube.
300 = Gull Wing Surface Mount Option, 50 per tube.
500 = Tape and Reel Packaging Option, 1000 per reel.

Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor.

Package Outline Drawings

Standard DIP Package
9.40 (0.370)
9.90 (0.390)

8 7 6 5
OPTION CODE* 0.20 (0.008)
6.10 (0.240) 0.33 (0.013)
HP 3150 Z DATE CODE
6.60 (0.260)
YYWW 7.36 (0.290)
7.88 (0.310) 5 TYP.

PIN ONE 1 2 3 4

1.78 (0.070) MAX.

1.19 (0.047) MAX.

4.70 (0.185) MAX.

PIN DIAGRAM
PIN ONE
0.51 (0.020) MIN. 1 VDD1 VDD2 8
2.92 (0.115) MIN.
DIMENSIONS 2IN MILLIMETERS 7 (INCHES).
VIN+ VOUT+ AND

0.76 (0.030) 0.65 (0.025) MAX.

1.40 (0.055) 3 VIN
* MARKING CODE VOUT
LETTER 6
FOR OPTION NUMBERS.
2.28 (0.090) "V" = OPTION 060.
2.80 (0.110) 4 GND1
OPTION NUMBERS 300 AND 5005NOT MARKED.
GND2

Gull-Wing Surface-Mount Option 300 PAD LOCATION (FOR REFERENCE ONLY)

9.65 0.25 1.016 (0.040)
(0.380 0.010) 1.194 (0.047)

8 7 6 5
4.826 TYP.
(0.190)
HP 3150 Z
6.350 0.25
YYWW (0.250 0.010) 9.398 (0.370)
9.906 (0.390)

1 2 3 4
MOLDED

0.381 (0.015)
1.194 (0.047) 0.635 (0.025)
1.778 (0.070)

1.780 9.65 0.25

(0.070) (0.380 0.010)
1.19 MAX.
(0.047) 7.62 0.25
MAX. (0.300 0.010)
0.20 (0.008)
4.19 MAX. 0.33 (0.013)
(0.165)

1.080 0.320 0.635 0.25

(0.043 0.013) (0.025 0.010)
0.635 0.130
2.540 (0.025 0.005) 12 NOM.
(0.100)
BSC

DIMENSIONS IN MILLIMETERS (INCHES).

TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01
xx.xxx = 0.005
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)

1-198
Reflow Temperature Profile Regulatory Information
260 The HCPL-3150 has been
240
T = 145C, 1C/SEC
approved by the following
220 organizations:
T = 115C, 0.3C/SEC
200
TEMPERATURE C

180
160 UL
140 Recognized under UL 1577,
120
100
Component Recognition
80 Program, File E55361.
T = 100C, 1.5C/SEC
60
40 CSA
20
0
Approved under CSA Component
0 1 2 3 4 5 6 7 8 9 10 11 12 Acceptance Notice #5, File CA
TIME MINUTES 88324.
MAXIMUM SOLDER REFLOW THERMAL PROFILE
(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
VDE (Option 060 only)
Approved under VDE 0884/06.92
with VIORM = 630 Vpeak.

VDE 0884 Insulation Characteristics (Option 060 Only)

Description Symbol Characteristic Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage 300 Vrms I-IV
for rated mains voltage 600 Vrms I-III
Climatic Classification 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 630 Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, VPR 1181 Vpeak
Partial discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, VPR 945 Vpeak
Partial discharge < 5 pC
Highest Allowable Overvoltage* VIOTM 6000 Vpeak
(Transient Overvoltage tini = 10 sec)
Safety-Limiting Values Maximum Values Allowed in the Event
of a Failure, Also See Figure 37, Thermal Derating Curve.
Case Temperature TS 175 C
Input Current IS, INPUT 230 mA
Output Power PS, OUTPUT 600 mW
Insulation Resistance at TS, VIO = 500 V RS 109

*Refer to the front of the optocoupler section of the current Catalog, under Product Safety Regulations section, (VDE 0884) for a
detailed description of Method a and Method b partial discharge test profiles.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.

1-199
Insulation and Safety Related Specifications
Parameter Symbol Value Units Conditions
Minimum External Air Gap L(101) 7.1 mm Measured from input terminals to output
(External Clearance) terminals, shortest distance through air.
Minimum External Tracking L(102) 7.4 mm Measured from input terminals to output
(External Creepage) terminals, shortest distance path along body.
Minimum Internal Plastic Gap 0.08 mm Through insulation distance conductor to
(Internal Clearance) conductor.
Tracking Resistance CTI 200 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance wtih CECC 00802.

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Note
Storage Temperature TS -55 125 C
Operating Temperature TA -40 100 C
Average Input Current IF(AVG) 25 mA 1
Peak Transient Input Current IF(TRAN) 1.0 A
(<1 s pulse width, 300 pps)
Reverse Input Voltage VR 5 Volts
High Peak Output Current IOH(PEAK) 0.6 A 2
Low Peak Output Current IOL(PEAK) 0.6 A 2
Supply Voltage (VCC - VEE) 0 35 Volts
Output Voltage VO(PEAK) 0 VCC Volts
Output Power Dissipation PO 250 mW 3
Total Power Dissipation PT 295 mW 4
Lead Solder Temperature 260C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile See Package Outline Drawings Section

Recommended Operating Conditions

Parameter Symbol Min. Max. Units
Power Supply Voltage (VCC - VEE) 15 30 Volts
Input Current (ON) IF(ON) 7 16 mA
Input Voltage (OFF) VF(OFF) -3.0 0.8 V
Operating Temperature TA -40 100 C

1-200
Electrical Specifications (DC)
Over recommended operating conditions (TA = -40 to 100C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V,
VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
High Level IOH 0.1 0.4 A VO = (VCC - 4 V) 2, 3, 5
Output Current 0.5 VO = (VCC - 15 V) 17 2
Low Level IOL 0.1 0.6 A VO = (VEE + 2.5 V) 5, 6 5
Output Current 0.5 VO = (VEE + 15 V) 18 2
High Level Output VOH (VCC - 4) (VCC - 3) V IO = -100 mA 1, 3 6, 7
Voltage 19
Low Level Output VOL 0.4 1.0 V IO = 100 mA 4, 6
Voltage 20
High Level ICCH 2.5 5.0 mA Output Open, 7, 8
Supply Current IF = 7 to 16 mA
Low Level ICCL 2.7 5.0 mA Output Open,
Supply Current VF = -3.0 to +0.8 V
Threshold Input IFLH 2.2 5.0 mA IO = 0 mA, 9, 15,
Current Low to High VO > 5 V 21
Threshold Input VFHL 0.8 V
Voltage High to Low
Input Forward Voltage VF 1.2 1.5 1.8 V IF = 10 mA 16
Temperature VF /TA -1.6 mV/C IF = 10 mA
Coefficient of
Forward Voltage
Input Reverse BVR 5 V IR = 10 A
Breakdown Voltage
Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V
UVLO Threshold VUVLO+ 11.0 12.3 13.5 V VO > 5 V, 22,
VUVLO- 9.5 10.7 12.0 IF = 10 mA 36
UVLO Hysteresis UVLOHYS 1.6 V
*All typical values at TA = 25C and VCC - VEE = 30 V, unless otherwise noted.

1-201
Switching Specifications (AC)
Over recommended operating conditions (TA = -40 to 100C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V,
VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Propagation Delay tPLH 0.10 0.30 0.50 s Rg = 47 , 10, 11, 14
Time to High Cg = 3 nF, 12, 13
Output Level f = 10 kHz, 14, 23
Duty Cycle = 50%
Propagation Delay tPHL 0.10 0.27 0.50 s
Time to Low
Output Level
Pulse Width PWD 0.3 s 15
Distortion
Propagation Delay PDD -0.35 0.35 s 34,35 10
Difference Between (tPHL - tPLH)
Any Two Parts
Rise Time tr 0.1 s 23
Fall Time tf 0.1 s
UVLO Turn On tUVLO ON 0.8 s VO > 5 V, 22
Delay IF = 10 mA
UVLO Turn Off tUVLO OFF 0.6 s VO < 5 V,
Delay IF = 10 mA
Output High Level |CMH| 15 30 kV/s TA = 25C, 24 11, 12
Common Mode IF = 10 to 16 mA,
Transient VCM = 1500 V,
Immunity VCC = 30 V
Output Low Level |CML| 15 30 kV/s TA = 25C, 11, 13
Common Mode VCM = 1500 V,
Transient VF = 0 V,
Immunity VCC = 30 V

Package Characteristics
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Input-Output VISO 2500 Vrms RH < 50%, 8, 9
Momentary t = 1 min.,
Withstand Voltage** TA = 25C
Resistance RI-O 1012 VI-O = 500 VDC 9
(Input - Output)
Capacitance CI-O 0.6 pF f = 1 MHz
(Input - Output)
LED-to-Case LC 391 C/W Thermocouple 28
Thermal Resistance located at center
LED-to-Detector LD 439 C/W underside of
Thermal Resistance package
Detector-to-Case DC 119 C/W
Thermal Resistance
*All typical values at TA = 25C and VCC - VEE = 30 V, unless otherwise noted.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or HP Application Note
1074 entitled Optocoupler Input-Output Endurance Voltage.
1-202
Notes: loads VOH will approach VCC as IOH under the same test condition.
1. Derate linearly above 70C free-air approaches zero amps. 11. Pins 1 and 4 need to be connected to
temperature at a rate of 0.3 mA/C. 7. Maximum pulse width = 1 ms, LED common.
2. Maximum pulse width = 10 s, maximum duty cycle = 20%. 12. Common mode transient immunity in
maximum duty cycle = 0.2%. This 8. In accordance with UL1577, each the high state is the maximum
value is intended to allow for optocoupler is proof tested by tolerable |dVCM /dt| of the common
component tolerances for designs applying an insulation test voltage mode pulse, VCM, to assure that the
with IO peak minimum = 0.5 A. See 3000 Vrms for 1 second (leakage output will remain in the high state
Applications section for additional detection current limit, II-O 5 A). (i.e., VO > 15.0 V).
details on limiting IOH peak. This test is performed before the 13. Common mode transient immunity in
3. Derate linearly above 70C free-air 100% production test for partial a low state is the maximum tolerable
temperature at a rate of 4.8 mW/C. discharge (method b) shown in the |dVCM/dt| of the common mode
4. Derate linearly above 70C free-air VDE 0884 Insulation Characteristics pulse, VCM, to assure that the output
temperature at a rate of 5.4 mW/C. Table, if applicable. will remain in a low state (i.e.,
The maximum LED junction tempera- 9. Device considered a two-terminal VO < 1.0 V).
ture should not exceed 125C. device: pins 1, 2, 3, and 4 shorted 14. This load condition approximates the
5. Maximum pulse width = 50 s, together and pins 5, 6, 7, and 8 gate load of a 1200 V/25 A IGBT.
maximum duty cycle = 0.5%. shorted together. 15. Pulse Width Distortion (PWD) is
6. In this test VOH is measured with a dc 10. The difference between tPHL and tPLH defined as |tPHL-tPLH| for any given
load current. When driving capacitive between any two HCPL-3150 parts device.
(VOH - VCC ) HIGH OUTPUT VOLTAGE DROP V

(VOH - VCC ) OUTPUT HIGH VOLTAGE DROP V

0 0.50 -1
IF = 7 to 16 mA IF = 7 to 16 mA
IOH OUTPUT HIGH CURRENT A

IOUT = -100 mA VOUT = VCC - 4 V 100 C

VCC = 15 to 30 V 0.45 VCC = 15 to 30 V -2 25 C
-1 VEE = 0 V VEE = 0 V -40 C

0.40 -3
-2

0.35 -4

-3 IF = 7 to 16 mA
0.30 -5 VCC = 15 to 30 V
VEE = 0 V

-4 0.25 -6
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 0 0.2 0.4 0.6 0.8 1.0
TA TEMPERATURE C TA TEMPERATURE C IOH OUTPUT HIGH CURRENT A

Figure 1. VOH vs. Temperature. Figure 2. IOH vs. Temperature. Figure 3. VOH vs. IOH.

1.0 1.0 5
VF(OFF) = -3.0 to 0.8 V
VOL OUTPUT LOW VOLTAGE V

IOL OUTPUT LOW CURRENT A

VOL OUTPUT LOW VOLTAGE V

VF(OFF) = -3.0 to 0.8 V

IOUT = 100 mA VCC = 15 to 30 V
0.8 VCC = 15 to 30 V 0.8 4 VEE = 0 V
VEE = 0 V

0.6 0.6 3

0.4 0.4 2
VF(OFF) = -3.0 to 0.8 V
VOUT = 2.5 V
0.2 0.2 1 100 C
VCC = 15 to 30 V
VEE = 0 V 25 C
-40 C
0 0 0
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 0 0.2 0.4 0.6 0.8 1.0
TA TEMPERATURE C TA TEMPERATURE C IOL OUTPUT LOW CURRENT A

Figure 4. VOL vs. Temperature. Figure 5. IOL vs. Temperature. Figure 6. VOL vs. IOL.

1-203
 IFLH LOW TO HIGH CURRENT THRESHOLD mA
3.5 3.5 5
ICCH ICCH VCC = 15 TO 30 V
ICC SUPPLY CURRENT mA

ICC SUPPLY CURRENT mA

ICCL ICCL VEE = 0 V
4 OUTPUT = OPEN
3.0 3.0

3
2.5 2.5
2
VCC = 30 V IF = 10 mA for ICCH
2.0 VEE = 0 V 2.0 IF = 0 mA for ICCL 1
IF = 10 mA for ICCH TA = 25 C
IF = 0 mA for ICCL VEE = 0 V
1.5 1.5 0
-40 -20 0 20 40 60 80 100 15 20 25 30 -40 -20 0 20 40 60 80 100
TA TEMPERATURE C VCC SUPPLY VOLTAGE V TA TEMPERATURE C

Figure 7. ICC vs. Temperature. Figure 8. ICC vs. VCC. Figure 9. IFLH vs. Temperature.

500 500 500

IF = 10 mA VCC = 30 V, VEE = 0 V IF(ON) = 10 mA
TPLH
Tp PROPAGATION DELAY ns

Tp PROPAGATION DELAY ns

Tp PROPAGATION DELAY ns
TA = 25 C
TPHL Rg = 47 , Cg = 3 nF IF(OFF) = 0 mA
Rg = 47 TA = 25 C VCC = 30 V, VEE = 0 V
400 Cg = 3 nF 400 DUTY CYCLE = 50% 400 Rg = 47 , Cg = 3 nF
DUTY CYCLE = 50% f = 10 kHz DUTY CYCLE = 50%
f = 10 kHz f = 10 kHz

300 300 300

200 200 200

TPLH TPLH
TPHL TPHL
100 100 100
15 20 25 30 6 8 10 12 14 16 -40 -20 0 20 40 60 80 100
VCC SUPPLY VOLTAGE V IF FORWARD LED CURRENT mA TA TEMPERATURE C

Figure 10. Propagation Delay vs. VCC. Figure 11. Propagation Delay vs. IF. Figure 12. Propagation Delay vs.
Temperature.

500 500 30
VCC = 30 V, VEE = 0 V VCC = 30 V, VEE = 0 V
Tp PROPAGATION DELAY ns
Tp PROPAGATION DELAY ns

TA = 25 C TA = 25 C
VO OUTPUT VOLTAGE V

IF = 10 mA IF = 10 mA 25
400 Cg = 3 nF 400 Rg = 47
DUTY CYCLE = 50% DUTY CYCLE = 50% 20
f = 10 kHz f = 10 kHz
300 300 15

10
200 200
TPLH TPLH 5
TPHL TPHL
100 100 0
0 50 100 150 200 0 20 40 60 80 100 0 1 2 3 4 5
Rg SERIES LOAD RESISTANCE Cg LOAD CAPACITANCE nF IF FORWARD LED CURRENT mA

Figure 13. Propagation Delay vs. Rg. Figure 14. Propagation Delay vs. Cg. Figure 15. Transfer Characteristics.

1-204
 1000
TA = 25C
IF FORWARD CURRENT mA

100
IF
1 8
10 +
VF 0.1 F

+ 4V
1.0 2 7
IF = 7 to + VCC = 15
0.1 16 mA to 30 V
3 6
0.01 IOH

0.001 4 5
1.10 1.20 1.30 1.40 1.50 1.60
VF FORWARD VOLTAGE V

Figure 16. Input Current vs. Forward Figure 17. IOH Test Circuit.
Voltage.

1 8 1 8
0.1 F 0.1 F
IOL
VOH
2 7 2 7
+ VCC = 15
to 30 V IF = 7 to + VCC = 15
16 mA to 30 V
3 6 2.5 V + 3 6

100 mA

4 5 4 5

Figure 18. IOL Test Circuit. Figure 19. VOH Test Circuit.

1 8 1 8
0.1 F 0.1 F
100 mA
2 7 2 7
+ VCC = 15 IF + VCC = 15
to 30 V VO > 5 V to 30 V
3 6 3 6
VOL

4 5 4 5

Figure 20. VOL Test Circuit. Figure 21. IFLH Test Circuit.

1 8
0.1 F

2 7

IF = 10 mA + VCC
VO > 5 V
3 6

4 5

Figure 22. UVLO Test Circuit.

1-205
 1 8
0.1 F IF
IF = 7 to 16 mA VCC = 15
+ to 30 V
2 7
500 tr tf
+ VO
10 KHz 90%
50% DUTY 3 6 47
CYCLE 50%
3 nF VOUT 10%
4 5
tPLH tPHL

Figure 23. tPLH, tPHL, tr, and tf Test Circuit and Waveforms.

VCM
V VCM
1 8 =
IF t t
A 0.1 F
0V
2 7
B
+ + t
5V VO

VCC = 30 V
3 6 VOH
VO

SWITCH AT A: IF = 10 mA
4 5
VO VOL

SWITCH AT B: IF = 0 mA
+

VCM = 1500 V

Figure 24. CMR Test Circuit and Waveforms.

Applications Information the IGBT gate is shorted to the
Eliminating Negative IGBT emitter by Rg + 4 . Minimizing
Gate Drive Rg and the lead inductance from
To keep the IGBT firmly off, the the HCPL-3150 to the IGBT gate
HCPL-3150 has a very low and emitter (possibly by
maximum VOL specification of mounting the HCPL-3150 on a
1.0 V. The HCPL-3150 realizes small PC board directly above the
this very low VOL by using a IGBT) can eliminate the need for
DMOS transistor with 4 negative IGBT gate drive in many
(typical) on resistance in its pull applications as shown in Figure
down circuit. When the 25. Care should be taken with
HCPL-3150 is in the low state, such a PC board design to avoid
+5 V HCPL-3150
1 8
VCC = 18 V
270 0.1 F +
2 7
Rg
routing the IGBT collector or
emitter traces close to the HCPL-
3150 input as this can result in
unwanted coupling of transient
signals into the HCPL-3150 and
degrade performance. (If the
IGBT drain must be routed near
the HCPL-3150 input, then the
LED should be reverse-biased
when in the off state, to prevent
the transient signals coupled
from the IGBT drain from turning
on the HCPL-3150.)
+ HVDC

CONTROL Q1 3-PHASE
INPUT 3 6 AC

74XXX
OPEN 4 5
COLLECTOR
Q2 - HVDC

Figure 25. Recommended LED Drive and Application Circuit.

1-206
Selecting the Gate Resistor The VOL value of 2 V in the pre- PT = P E + P O
(Rg) to Minimize IGBT vious equation is a conservative PE = IF VF Duty Cycle
Switching Losses. value of VOL at the peak current PO = PO(BIAS) + PO (SWITCHING)
Step 1: Calculate Rg Minimum of 0.6 A (see Figure 6). At lower = ICC (VCC - VEE)
From the IOL Peak Specifica- Rg values the voltage supplied by + ESW(RG, QG) f
tion. The IGBT and Rg in Figure the HCPL-3150 is not an ideal
26 can be analyzed as a simple voltage step. This results in lower For the circuit in Figure 26 with IF
RC circuit with a voltage supplied peak currents (more margin) (worst case) = 16 mA, Rg =
by the HCPL-3150. than predicted by this analysis. 30.5 , Max Duty Cycle = 80%,
When negative gate drive is not Qg = 500 nC, f = 20 kHz and TA
(VCC VEE - VOL) used VEE in the previous equation max = 90C:
Rg
IOLPEAK is equal to zero volts.
PE = 16 mA 1.8 V 0.8 = 23 mW
(VCC VEE - 1.7 V)
= Step 2: Check the HCPL-3150
IOLPEAK PO = 4.25 mA 20 V
Power Dissipation and
+ 4.0 J 20 kHz
(15 V + 5 V - 1.7 V) Increase Rg if Necessary. The
= 85 mW + 80 mW
= HCPL-3150 total power dissipa-
0.6 A = 165 mW
tion (PT) is equal to the sum of
> 154 mW (PO(MAX) @ 90C
= 30.5 the emitter power (PE) and the
= 250 mW20C 4.8 mW/C)
output power (PO):

+5 V HCPL-3150
1 8
VCC = 15 V + HVDC
270 0.1 F +

2 7
Rg

CONTROL Q1 3-PHASE
3 6 AC
INPUT VEE = -5 V

+
74XXX
OPEN 4 5
COLLECTOR
Q2 - HVDC

Figure 26. HCPL-3150 Typical Application Circuit with Negative IGBT Gate Drive.

PE PO Parameter Description
Parameter Description ICC Supply Current
IF LED Current VCC Positive Supply Voltage
VF LED On Voltage VEE Negative Supply Voltage
Duty Cycle Maximum LED ESW(Rg,Qg) Energy Dissipated in the HCPL-3150 for each
Duty Cycle IGBT Switching Cycle (See Figure 27)
f Switching Frequency

1-207
The value of 4.25 mA for ICC in
the previous equation was
obtained by derating the ICC max
of 5 mA (which occurs at -40C)
to ICC max at 90C (see Figure 7).
Since PO for this case is greater
than PO(MAX), Rg must be
increased to reduce the HCPL-
3150 power dissipation.
PO(SWITCHING MAX)
= PO(MAX) - PO(BIAS)
= 154 mW - 85 mW
= 69 mW
PO(SWITCHINGMAX)
ESW(MAX) = DC shown in Figure 28 gives:
f
69 mW
= = 3.45 J
20 kHz
For Qg = 500 nC, from Figure
27, a value of ESW = 3.45 J
gives a Rg = 41 .
Thermal Model
The steady state thermal model
for the HCPL-3150 is shown in
Figure 28. The thermal resistance
values given in this model can be
used to calculate the tempera-
tures at each node for a given
operating condition. As shown by
the model, all heat generated
flows through CA which raises
the case temperature TC
accordingly. The value of CA
depends on the conditions of the
board design and is, therefore,
determined by the designer. The
value of CA = 83C/W was
obtained from thermal measure-
ments using a 2.5 x 2.5 inch PC
board, with small traces (no
ground plane), a single HCPL-
3150 soldered into the center of
the board and still air. The
absolute maximum power
dissipation derating specifications
assume a CAvalue of 83C/W.
1-208
From the thermal mode in Figure
28 the LED and detector IC
junction temperatures can be
expressed as:
TJE = PE (LC||(LD + DC) + CA)
LC DC
(
+ PD
LC + DC + LD
)
+ CA + TA ever, this shield does not
LC DC
(
TJD = PE
LC + DC + LD
+ CA ) ler pins 5-8 as shown in
+ PD (DC||(LD + LC) + CA) + TA
Inserting the values for LC and
a shielded optocoupler. The main
TJE = PE (230C/W + CA)
LED drive circuit becomes
+ PD (49C/W + CA) + TA
TJD = PE (49C/W + CA)
+ PD (104C/W + CA) + TA
For example, given PE = 45 mW,
PO = 250 mW, TA = 70C and CA
= 83C/W:
TJE = PE 313C/W + PD 132C/W + TA
= 45 mW 313C/W + 250 mW
132C/W + 70C = 117C
TJD = PE 132C/W + PD 187C/W + TA
= 45 mW 132C/W + 250 mW
187C/W + 70C = 123C
TJE and TJD should be limited to
125C based on the board layout
and part placement (CA) specific
to the application.
LED Drive Circuit
Considerations for Ultra
High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC as
shown in Figure 29. The HCPL-
3150 improves CMR performance
by using a detector IC with an
optically transparent Faraday
shield, which diverts the capaci-
tively coupled current away from
the sensitive IC circuitry. How
eliminate the capacitive coupling
between the LED and optocoup-
Figure 30. This capacitive
coupling causes perturbations in
the LED current during common
mode transients and becomes the
major source of CMR failures for
design objective of a high CMR
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 25), can achieve
15 kV/s CMR while minimizing
component complexity.
Techniques to keep the LED in
the proper state are discussed in
the next two sections.
Esw ENERGY PER SWITCHING CYCLE J
7
Qg = 100 nC
6 Qg = 250 nC
5
Qg = 500 nC
VCC = 19 V
4
VEE = -9 V
3
2
1
0
0 20 40 60 80 100
Rg GATE RESISTANCE
Figure 27. Energy Dissipated in the
HCPL-3150 for Each IGBT Switching
Cycle.
 LD = 439C/W
TJE = LED junction temperature
TJE TJD TJD = detector IC junction temperature
LC = 391C/W DC = 119C/W
TC = case temperature measured at the center of the package bottom
TC
LC = LED-to-case thermal resistance
LD = LED-to-detector thermal resistance
CA = 83C/W* DC = detector-to-case thermal resistance
CA = case-to-ambient thermal resistance
TA CA will depend on the board design and the placement of the part.

Figure 28. Thermal Model.

CMR with the LED On
(CMRH)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED cur-
rent of 10 mA provides adequate
margin over the maximum IFLH of
5 mA to achieve 15 kV/s CMR.
CMR with the LED Off
(CMRL)
A high CMR LED drive circuit
must keep the LED off
(VF VF(OFF)) during common
mode transients. For example,
during a -dVCM/dt transient in
Figure 31, the current flowing
through CLEDP also flows through
the RSAT and VSAT of the logic
gate. As long as the low state
voltage developed across the
logic gate is less than VF(OFF), the
LED will remain off and no
common mode failure will occur.
The open collector drive circuit,
shown in Figure 32, cannot keep
the LED off during a +dVCM/dt
transient, since all the current
flowing through CLEDN must be
supplied by the LED, and it is not
recommended for applications
requiring ultra high CMRL
performance. Figure 33 is an
alternative drive circuit which,
like the recommended application
circuit (Figure 25), does achieve
ultra high CMR performance by
shunting the LED in the off state.
Under Voltage Lockout
Feature
The HCPL-3150 contains an
under voltage lockout (UVLO)
feature that is designed to protect
the IGBT under fault conditions
which cause the HCPL-3150
supply voltage (equivalent to the
fully-charged IGBT gate voltage)
to drop below a level necessary to
keep the IGBT in a low resistance
state. When the HCPL-3150
output is in the high state and the
supply voltage drops below the
HCPL-3150 VUVLO- threshold
(9.5 <VUVLO- <12.0), the
optocoupler output will go into
the low state with a typical delay,
UVLO Turn Off Delay, of 0.6 s.
When the HCPL-3150 output is in
the low state and the supply
voltage rises above the HCPL-
3150 VUVLO+ threshold
(11.0 < VUVLO+ < 13.5), the
optocoupler will go into the high
state (assuming LED is ON)
with a typical delay, UVLO TURN
On Delay, of 0.8 s.
IPM Dead Time and
Propagation Delay
Specifications
The HCPL-3150 includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize dead
time in their power inverter
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in Figure
25) are off. Any overlap in Q1
and Q2 conduction will result in
large currents flowing through
the power devices from the high-
to the low-voltage motor rails.
To minimize dead time in a given
design, the turn on of LED2
should be delayed (relative to the

1-209
 1 8 1 CLEDO1 8

CLEDP CLEDP
2 7 2 7

CLEDO2

3 6 3 6
CLEDN CLEDN

4 5 4 5
SHIELD

Figure 29. Optocoupler Input to Output Figure 30. Optocoupler Input to Output
Capacitance Model for Unshielded Optocouplers. Capacitance Model for Shielded Optocouplers.

+5 V 1 8
0.1
CLEDP F +
VCC = 18 V
+ 2 7 1 8
ILEDP
VSAT +5 V
CLEDP
3 6 2 7
CLEDN
Rg

4 5 3 6
SHIELD Q1 CLEDN

ILEDN

* THE ARROWS INDICATE THE DIRECTION 4 5

OF CURRENT FLOW DURING dVCM/dt. SHIELD

+
VCM

Figure 31. Equivalent Circuit for Figure 25 During Figure 32. Not Recommended Open
Common Mode Transient. Collector Drive Circuit.

turn off of LED1) so that under maximum dead time is equivalent

1 8 worst-case conditions, transistor
+5 V Q1 has just turned off when
CLEDP
2 7 transistor Q2 turns on, as shown
in Figure 34. The amount of delay
necessary to achieve this condi-
3 6
CLEDN tions is equal to the maximum
value of the propagation delay
4
SHIELD
5 difference specification, PDDMAX,
which is specified to be 350 ns
over the operating temperature
range of -40C to 100C.
Figure 33. Recommended LED Drive
Circuit for Ultra-High CMR.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but it
does not tell a designer what the
maximum dead time will be. The
to the difference between the
maximum and minimum propaga-
tion delay difference specifica-
tions as shown in Figure 35. The
maximum dead time for the
HCPL-3150 is 700 ns (= 350 ns -
(-350 ns)) over an operating
temperature range of -40C to
100C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal tempera-
tures and test conditions since
the optocouplers under consider-
ation are typically mounted in
close proximity to each other and
are switching identical IGBTs.

1-210
ILED1
14

12

VO OUTPUT VOLTAGE V
VOUT1
Q1 ON (12.3, 10.8)
Q1 OFF 10
(10.7, 9.2)
8
Q2 ON
Q2 OFF 6
VOUT2

4
ILED2
tPHL MAX 2
tPLH MIN (10.7, 0.1) (12.3, 0.1)
0
PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN 0 5 10 15 20
(VCC - VEE ) SUPPLY VOLTAGE V
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 36.Under Voltage Lock Out.

Figure 34. Minimum LED Skew for Zero Dead Time.

OUTPUT POWER PS, INPUT CURRENT IS

800
PS (mW)
700
IS (mA)
ILED1
600

500
VOUT1
Q1 ON 400
Q1 OFF
300

Q2 ON 200
VOUT2 Q2 OFF
100

0
ILED2 0 25 50 75 100 125 150 175 200
tPHL MIN TS CASE TEMPERATURE C
tPHL MAX
tPLH
MIN Figure 37. Thermal Derating Curve,
tPLH MAX Dependence of Safety Limiting Value
(tPHL-tPLH) MAX
with Case Temperature per
= PDD* MAX
VDE 0884.

MAXIMUM DEAD TIME

(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN)
= (tPHL MAX - tPLH MIN) (tPHL MIN - tPLH MAX)
= PDD* MAX PDD* MIN

*PDD = PROPAGATION DELAY DIFFERENCE

NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.

Figure 35. Waveforms for Dead Time.

1-211
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