IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO.
5, MAY 2009
An Optimization-Based Algorithm for Shunt Active
Filter Under Distorted Supply Voltages
Koteswara Rao Uyyuru, Mahesh K. Mishra, Member, IEEE, and Arindam Ghosh, Fellow, IEEE
AbstractIn this paper, an optimization-based control algo-
rithm for the compensation of steady-state load under distorted
supply voltages is presented. For balanced and sinusoidal supply
voltages, load compensation using shunt active filter produces per-
fect harmonic cancellation (PHC) and unity power factor (UPF)
source currents. However, when the supply voltages are distorted,
compensation for PHC will not provide UPF, as the harmonics in
the supply voltages are not utilized for delivering the average power.
In the same way, to achieve UPF source currents, the compensated
source currents should have the same harmonics, unbalance, shape,
and be in phase with the respective supply voltages, thereby vio-
lating the perfect harmonic cancellation objective. Hence, there
should be an optimal operation between these two important com-
pensation characteristics. The optimization-based control algo-
rithm presented in this paper gives the best power factor while
satisfying the constraints such as total harmonic distortion limits
and average power balance of source currents. It is also flexible to
adopt different compensation characteristics based upon the sup-
ply voltage conditions. MATLAB and its optimization toolbox are
used for simulation studies and solving the nonlinear optimization
problem, respectively. The algorithm is validated by using a proto-
type of digital signal processor (TMS320F2812PGFA)-based shunt
active power filter. Detailed experimental results are presented.
Index TermsActive power filter (APF), digital signal processor
(DSP), load compensation, optimization, perfect harmonic cancel-
lation, unity power factor.
I. INTRODUCTION
HE DEMAND from the electricity consumers for good
T quality of power supply is ever increasing due to the pro-
liferation of sensitive loads. This is often a challenging task.
The widespread use of adjustable-speed drives, static power
converters such as single-phase and three-phase rectifiers, and
a large number of power-electronics-based equipments cause
distortion in the source currents. The loads such as induction
furnaces and motors increase the rating of the equipments used
in the power system. Single phasing and unequal distribution
of loads among three phases cause excessive neutral current to
flow in the system [1]. Though conventional load compensation
using passive filters is simple to design and operate, it has draw-
backs like resonance, overloading, and detuning. Moreover, it
is not suitable for fast changing loads. The aforesaid problems
Manuscript received September 1, 2008; revised November 3, 2008. Current
version published April 17, 2009. Recommended for publication by Associate
Editor J. R. Rodriguez.
K. R. Uyyuru and M. K. Mishra are with the Department of Electrical Engi-
neering, Indian Institute of Technology Madras, Chennai 600 036, India (e-mail:
ee06s007@iitm.ac.in; mahesh@ee.iitm.ac.in).
A. Ghosh is with the School of Engineering Systems, Queensland University
of Technology, Brisbane, Qld. 4001, Australia (e-mail: a.ghosh@qut.edu.au).
Digital Object Identifier 10.1109/TPEL.2008.2011908
0885-8993/$25.00 2009 IEEE
1223
are effectively alleviated by using a shunt active power filter
(APF) [2]. The selection of control strategy for the APF plays
an important role to get the desired compensation character-
istics. The two main control strategies for load compensation
are perfect harmonic cancellation (PHC) and unity power fac-
tor (UPF) [3][13]. The PHC strategy results in distortion-free
source currents and it is proved that under this strategy, APF
provides better performance [3]. Implementation of a UPF con-
trol strategy gives minimum rms values of source current for a
given average load power [4]. The main advantage of UPF is
that it can preserve the damping provided by the resistive part
of the compensated load. This damping effect is required in
the case of resonance phenomena, particularly in the voltage-
distorted grids, failing which, severe voltage distortion results
at the point of common coupling (PCC) [8].
Under balanced and sinusoidal supply voltages, both UPF
and PHC strategies result in similar compensation characteris-
tics. But under distorted supply voltages, these two important
attributes of load compensation cannot be achieved simulta-
neously. The control strategy for UPF demands that the com-
pensated source currents have to be of same shape, harmonics,
unbalance, and in phase with the respective phase voltages,
which will not ensure perfect harmonic cancellation. Similarly,
PHC strategy will not allow any harmonic component in the
compensated source currents. It is also possible to compensate
the unbalance and reactive part of the load current under this
strategy. However, UPF cannot be achieved by this strategy, be-
cause the supply voltage harmonics are not utilized to supply
average load power. Most of the existing works on shunt ac-
tive power filters under distorted supply voltages adopts either
one of the two control strategies (PHC or UPF). In order to
utilize the advantages of both the strategies, there should be an
optimal operation between these two important compensation
characteristics.
Through the evaluation of PHC and UPF strategies, an op-
timal and flexible control strategy is proposed in [6]. In this
method, a two-step process is adopted to get the desired source
currents. First, the actual voltages are processed through filters,
whose gains are optimized and tuned to get desired voltages.
These voltages are then multiplied by a constant conductance
to get the reference source currents, thus resulting in the aver-
age power being equal to the load average power. This method
employs pq theory that is quite computation intensive. Also, it
generates some additional harmonics in the extracted reference
currents under distorted supply voltages [14]. It also involves
multiple transformations (abc to and to abc), which
will increase the computational time. G. W. Chang et al. pro-
posed a steady-state optimized load compensation algorithm
1224 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 5, MAY 2009

to meet IEEE-519 harmonic current limits and other alternate
performance indices [15], [16]. However, their research is lim-
ited to simulation studies only.
In [17], a nonlinear optimization technique is employed to
get the optimal performance between total harmonic distortion
(THD) limits and the UPF. The algorithm employs a one-step
process to get the reference source currents. However, in this
control algorithm, the authors assumed that the supply voltages
are balanced, but distorted. As the presence of unbalance in
the supply voltages is a common phenomenon, this algorithm
t +T
cannot be used in such cases.
In this paper, a new load compensation algorithm based on op-
timization and extraction of balanced components using Fourier
transform is proposed. This algorithm works effectively not
only under balanced distorted supply voltages, but also under
unbalanced conditions. The Fourier transform is used to get the
balanced set of voltages from the unbalanced distorted supply
voltages. The desired source currents are computed by multiply-
(3n + 3) radian according to the positive, negative, zero se-
quences, respectively, for a fundamental frequency of ra-
dian [18]. In this case, v + 0
sa (t), v sa (t), and v sa (t) in (2) will
have 3n + 1, 3n + 2 and 3n + 3 harmonics, respectively. How-
ever, for an unbalanced distorted system, v + sa (t), v sa (t), and
0
v sa (t) will contain all the harmonics of the source voltages.
The balanced steady-state voltage harmonic components can
be determined by using the following expressions. For 3n + 1
harmonic order, it is written as follows:
+ 2 1
j ((3n +1) t /2)
V sa (3n +1) = v+sa (t)e dt (3)
T t1
where n = 0, 1, . . . , k. The term t1 is an arbitrary instant and
T is the time period of the cycle. The integration is carried out
using a moving average technique to settle any change in supply
voltages within one cycle, assuming that the source voltages
may contain both even and odd harmonics. From the previous
expression |V + sa (3n +1) | and V sa (3n +1) can be obtained. The
 +

ing the balanced set of voltages with the conductance factors, balanced 3n +2 harmonic voltages are given by
which are obtained from the optimization process. For better dy-
t +T
2 1
namic response, a moving average filter is adopted to calculate V sa (3n +2) = v
sa (t)e
j ((3n +2) t /2)
dt (4)
average load power as well as balanced set of supply voltages. T t1
In the following section, the extraction of balanced set of volt- where n = 0, 1, . . . , k. From the previous expression,
ages from available unbalanced distorted supply voltages using |V
sa(3n +2) | and V sa(3n +2) can be obtained. Similarly, the

Fourier transform is presented. 3n + 3 harmonic voltages are obtained as follows:

t +T
2 1
II. EXTRACTION OF THE BALANCED SET OF VOLTAGES FROM 0
V sa (3n +3) = v 0sa (t)ej ((3n +3) t /2) dt (5)
UNBALANCED DISTORTED SUPPLY VOLTAGES T t1
Let the unbalanced and distorted voltages be represented by where n = 0, 1, . . . , k. From the previous expression,
|V 0sa(3n +3) | and  V 0sa(3n +3) can be calculated.

k

Vm an sin (n t + v an )
Therefore, the balanced quantities in the case of unbalanced
vsa (t) =


and distorted supply voltages are (6)(8), as shown at the bottom
n =1


k of the next page, where n = 0, 1, . . . , k in (6)(8). The three-
vsb (t) = Vm bn sin (n t + v bn ) . (1) phase balanced set of voltages in the case of unbalanced and


n =1
distorted supply voltages can be written as

k


Vm cn sin (n t + v cn )


k
vsc (t) = 
vsa (t)= +
(vsa(3n 0
n =1 +1) (t)+vsa(3n +2) (t)+vsa(3n +3) (t))
n =0
In (1), the subscript s denotes the supply, subscripts a, b, c are
the three phases of the system, m denotes the maximum or peak

k
 + 0
vsb (t)= (vsb(3n +1) (t)+vsb(3n +2) (t)+vsb(3n +3) (t))
value, and n denotes the harmonic number. The maximum har-
n =0
monic number considered in the source voltage is denoted by k.
Let us denote the phase-a instantaneous positive sequence,

k
 + 0
negative sequence, and zero sequence voltages by vsa +
(t), vsa (t), vsc (t)= (vsc(3n +1) (t)+vsb(3n +2) (t)+vsc(3n +3) (t)). (9)
0 n =0
and vsa (t), respectively. These sequence voltages are expressed
using symmetrical component theory as follows: Since all the quantities on the right-hand side of (9) are balanced,
  
0 vsa , vsb and vsc form balanced quantities for the distorted and
v sa (t) 1 1 1 vsa (t)
1 unbalanced supply voltages.
v+sa (t)
= 1 a a2 vsb (t) . (2)
3
vsa (t) 1 a2
a vsc (t) III. OPTIMIZATION TECHNIQUE TO GET THE
Here, a is the complex operator with a value of e j 2 /3
. The CONDUCTANCE FACTORS
sequence components given earlier are denoted by bold-faced In order to get the desired optimal performance between unity
letters as they are complex quantities and function of time. The power factor and THD limits of source currents, an optimization
zero sequence components are not complex quantities; however, technique is employed [17]. This algorithm is applicable only
they are represented by bold-faced letters to maintain uniformity when the supply voltages are balanced and distorted. For the
in equations. In a balanced distorted system, the harmonics of unbalanced and distorted supply voltages, this algorithm gives
order 3n + 1, 3n + 2, 3n + 3 rotate at (3n + 1), (3n + 2), unbalanced compensated source currents. Hence, in order to get
UYYURU et al.: OPTIMIZATION-BASED ALGORITHM FOR SHUNT ACTIVE FILTER UNDER DISTORTED SUPPLY VOLTAGES 1225


balanced compensated source currents, the algorithm is modi- In the previous equation, Vsan is the rms value of the nth -
fied by using the extracted balanced set of voltages (9) instead of 
order balanced harmonic voltage component, Vsa1 is the rms
actual supply voltages. The optimization process for unbalanced 
value of the balanced fundamental voltage, Isan is the rms value
distorted supply voltages of phase-a is given as follows. of the nth -order balanced harmonic current component, ITHD
Let the desired source current for phase-a be given by is the harmonic limit on the source current, and Plavg is the
 k average load power, which is computed by the moving average


 + + technique. It will take a maximum of one cycle if both voltage
isa (t) = k1 (vsa1 )+kn (vsa(3n +1) )
n =1 and current have even harmonics. If the voltage and current
 have only odd harmonics, then half cycle data will be sufficient


k
for computation. The necessary conditions for constrained local
0
+ (vsa(3n +2) (t)+vsa(3n +3) (t))
n =0
minima of L are that the first-order derivatives with respect to
the variables present in the function must be zero. Therefore
(10)
L
where k1 , and kn are conductance factors for the fundamen- = y 1 [2k1 (x (ITHD )2 ) ] = 0 (13)
k1
tal and the harmonics, respectively. By controlling these fac-
tors, the THD content in source current can be controlled. The L
= yn [2kn (x + ) ] = 0 (14)
Lagrangian multiplier technique is used to get the conductance kn
factors for the minimum apparent power by satisfying the men-  
where x = n1 ((Vsan )2 ), yn = (Vsan )2 .
tioned constraints.
 
The general Lagrangian function is formed as follows:
L Plavg
n
 2  2
= (Vsa1 ) k1 + (Vsan ) kn = 0 (15)
L=f +r+s (11) 3 2

L
2
where L is the Lagrangian function, f is the objective func- n
 2  2
tion, and and are the Lagrangian multipliers. The terms r = kn (Vsan ) (ITHD )2 k12 (Vsa1 ) = 0. (16)
2
and s are the equality and inequality constrains, respectively. In
the optimization technique, the objective function is to minimize By solving (13)(16), using the MATLAB optimization tool
the apparent power that will directly influence power factor. The box, k1 , kn , , and are obtained for an optimum power factor
equality constraint in the optimization process is that the desired within acceptable THD limit of source current. The conduc-
source currents should supply the load average power, while the tance factors k1 and kn are responsible for shaping the source
inequality constraint puts a specified limit on the THD. There- currents according to the constraints specified. These values are
fore, the Lagrange function to minimize the apparent power is substituted in (10) to get the desired source current for phase-a.
formulated as Similarly, desired currents for b and c phases can be calculated


n

n with the same conductance factors. Therefore, there is no need
 2  2
L= (Vsan ) (Isan ) to perform optimization for the other two phases. This will re-
1 1 duce computation time of reference currents and ensure that the
  
Plavg

n average source power is equal to the average load power. This
 2  2
+ (Vsa1 ) k1 + (Vsan ) kn is another feature of the proposed algorithm. After getting the
3 2 desired source currents, the compensator currents for the three
 n 

phases are obtained from the following equations:
 2 2  2
+ kn2 (Vsan ) (ITHD ) k12 (Vsa1 ) . (12)
2 i 
f a = ila isa , i 
f b = ilb isb , i 
f c = ilc isc . (17)

sa (3n +1) | sin((3n + 1) (t) + V sa (3n +1) )
+
vsa (3n +1) (t) = 2|V +  +



sa (3n +1) | sin((3n + 1) (t 2/3) + V sa (3n +1) )
+
vsb (3n +1) (t) = 2|V +  +
(6)



sa (3n +1) | sin((3n + 1) (t + 2/3) + V sa (3n +1) )
+
vsc (3n +1) (t) = 2|V +  +

vsa (3n +2) (t) = 2|V 
sa (3n +2) | sin((3n + 2) (t) + V sa (3n +2) )



vsb (3n +2) (t) = 2|V sa (3n +2) | sin((3n + 2) (t 2/3) + V sa (3n +2) )
 (7)


v
sc (3n +2) (t) = 2|V | sin((3n + 2) (t + 2/3) +  V
sa (3n +2) ) sa (3n +2)

sa (3n +3) | sin((3n
0 0 0
vsa (3n +3) (t) = 2|V + 3) (t) +  V sa (3n +3) )


0
vsb (3n +3) (t) = 2|V 0sa (3n +3) | sin((3n + 3) (t 2/3) +  V 0sa (3n +3) ) (8)


0
vsc (t) = 2|V 0
| sin((3n + 3) (t + 2/3) +  V0 )
(3n +3) sa (3n +3) sa (3n +3)
1226
Fig. 1. Flowchart for the extraction of reference compensator currents using
proposed optimization control algorithm.
These compensating currents are then realized by using the
current-controlled voltage source inverter (VSI) with hystere-
sis current control technique. When the load changes from one
level to another, the conductance factors obtained for the previ-
ous load cannot be used. For the new load, again the optimization
process has to be run to get the new conductance factors. Then,
these values can be utilized in the compensation algorithm. As
the optimization process cannot give instantaneous result, it is
possible to shift the compensation from optimization control
algorithm to PHC or UPF operation until the new conductance
factors are known, and hence, there is no interruption in the com-
pensation. The flowchart for the extraction of balanced voltages
and the process of optimization is shown in Fig. 1.
IV. SIMULATION RESULTS WITH IDEAL COMPENSATOR
In this section, detailed simulation studies for a three-phase
four-wire system are presented to explain the PHC and UPF
strategies along with the previously discussed optimized con-
trol algorithm. A schematic of a three-phase, four-wire compen-
sated system is shown in Fig. 2. The three-phase load may be
unbalanced and nonlinear. A shunt APF (or compensator) and
the load are connected at the point called the PCC. For the sake
of illustrating the concept, the compensator is considered to be
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 5, MAY 2009
Fig. 2. Schematic of three-phase, four-wire compensated system.
Fig. 3. (a) Supply voltages for case 1. (b) Supply voltages for case 2. (c) Load
currents for case 1. (d) Load currents for case 2.
ideal and it consists of three ideal current sources that are shown
in Fig. 2.
For the simulation study, two cases of supply voltages
are considered: in case 1, balanced distorted voltages and in
case 2, unbalanced distorted supply voltages. For these two
cases, the supply voltages are expressed in (18) and (19),
respectively.
Case 1: Balanced Distorted Supply Voltages
vsa = 359.25 sin(t) + 64.66 sin(5t) + 35.92 sin(7t)
vsb = 359.25 sin(t 1200 ) + 64.66 sin(5 (t 1200 ))
+ 35.92 sin(7(t 1200 ))
vsc = 359.25 sin(t + 1200 ) + 64.66 sin(5 (t + 1200 ))
+ 35.92 sin(7(t + 1200 )). (18)
Case 2: Unbalanced Distorted Supply Voltages
vsa = 359.25 sin(t) + 64.66 sin(5t) + 35.92 sin(7t)
vsb = 287.4 sin(t 1200 ) + 53.88 sin(5 (t 1200 ))
+ 46.70 sin(7(t 1200 ))
vsc = 431.1 sin(t + 1200 ) + 89.81 sin(5 (t + 1200 ))
+ 89.81 sin(7(t + 1200 )). (19)
UYYURU et al.: OPTIMIZATION-BASED ALGORITHM FOR SHUNT ACTIVE FILTER UNDER DISTORTED SUPPLY VOLTAGES
TABLE I
SUPPLY VOLTAGE, LOAD CURRENT, AND POWER FACTOR DATA
Fig. 4. (a) Source currents for case 1. (b) Source currents for case 2.
The load considered for the simulation consists of an unbalanced
linear load and a three-phase full-bridge diode rectifier, which
draws nonlinear load currents from the supply. The supply volt-
ages and the corresponding load currents are shown in Fig. 3.
Details of these parameters, i.e., rms values, THDs, power factor
are given in Table I. Before describing the optimization control
algorithm, the results of PHC and UPF strategies are presented
using instantaneous symmetrical component theory under both
the cases of supply voltages.
A. PHC Strategy
In this strategy, the fundamental positive sequence voltages
are extracted from the supply. These voltages are then used to
calculate reference source currents by using instantaneous sym-
metrical component theory [9]. The phase-a reference source
current is expressed as follows:
+
vsa1 vsa1
0
i+
sa1 = Plavg .
+2
(vsa1 + vsb1 + vsc1
+2 +2 0 )2 )
3(vsa1
0 shown in Fig. 6.
In the previous equation vsa1 is the zero sequence voltage and
its value is equal to zero as the considered supply voltages in (20)
are fundamental positive sequence (balanced) voltages. Here,
+2 +2 +2
the important aspect is that the term (vsa1 + vsb1 + vsc1 ) is con-
stant at every instant. Hence, reference source currents resemble
the fundamental positive sequence voltages with a scaling factor.
Using this strategy, the compensated source currents become si-
nusoidal and balanced. The compensated source currents for the
two cases are shown in Fig. 4(a) and (b), respectively. Though
source currents for both the cases look similar, their magnitudes
are different, as observed from Tables II and III.
B. UPF Strategy
In this strategy, the denominator of (20) is replaced by a mean
value of sum of squared supply voltages. Also, the compensation
0
for the zero sequence voltages is not provided; therefore, vsa
term is eliminated in the numerator and the denominator. As a
consequence of this, the neutral current after compensation is
1227
no longer zero. The reference source currents are proportional
to the actual supply voltages. For phase-a, the source current is
given as follows:
vsa
isa = 2 2 + v 2  Plavg . (21)
vsa + vsb sc
2
Here, the symbol  represents the running mean of (vsa +
2 2
vsb + vsc ) over a period and its value is constant at every instant.
In the previous expression, Plavg is also constant. Therefore, the
source currents resemble the supply voltages. The compensated
source currents for this strategy are shown in Fig. 5(a) and (b),
respectively. This operation results in UPF. If the mean of the
2 2 2
(vsa + vsb + vsc ) term is not considered, dissimilar harmonics
will be present in voltages and currents, and hence, UPF opera-
tion cannot be achieved.
C. Proposed Optimization Control Algorithm
In the previous two control strategies, one compensates the
current harmonics but does not provide unity power factor and
the other gives unity power factor but without compensation of
current harmonics and unbalance. Thus, these schemes do not
fulfill the aims of compensation and representing two extremes
of compensation characteristics. Hence, the optimization con-
trol strategy is employed to get an optimal performance between
the PHC and UPF strategies. However, the characteristics of
these strategies can be obtained as special cases of the proposed
optimization control algorithm. This is achieved by specifying
desired source current THD limits 0% and the same as voltage
THDs, for the PHC and UPF strategies, respectively. The com-
(20)
pensated source currents for THD limits of 5% and 10% are
V. ANALYSIS OF THE SIMULATION RESULTS
For the simulation studies, the rms, THD values of supply
voltages and load currents, power factor values are given in
Table I. The performances of the PHC, UPF strategies and pro-
posed optimal control algorithm (OCA) are given in Tables II
and III under the two supply voltage conditions (case 1 and
case 2). Here, nonunity power factor and nonperfect harmonic
cancellation are represented by NUPF and NPHC, respectively.
A. PHC Strategy
In this strategy, the source currents obtained are balanced and
the THDs in the source currents are zero as given in Table II. The
compensator rating for this strategy is minimum compared to
the other strategies. However, power factor is not unity, though
the source currents are sinusoidal as the harmonic component in
1228 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 5, MAY 2009

TABLE II
SIMULATION RESULTS OF THE STRATEGIES UNDER BALANCED AND DISTORTED SUPPLY VOLTAGES (CASE 1)

TABLE III
SIMULATION RESULTS OF THE STRATEGIES UNDER UNBALANCED AND DISTORTED SUPPLY VOLTAGES (CASE 2)

Fig. 5. (a) Source currents for case 1 (b) Source currents for case 2.

supply voltages does not contribute to the average load power,

which, in turn, increases the apparent power. The value of the
power factor totally depends upon the supply voltage distortion.
It can be verified from the following derivation:
  Fig. 6. Source currents for (a) 5% THD under case 1, (b) 5% THD under
average load power Plavg
pf = case 2, (c) 10% THD under case 1, and (d) 10% THD under case 2.
Vrm s Irm s
V1 I1 cos 1 + V2 I2 cos 2 + V3 I3 cos 3 + + Vn In cos n
=   . where THDv is the total harmonic distortion of supply voltage
V12 + V22 + V32 + + Vn2 I12 + I22 + I32 + + In2
[19].
(22)

In order to compensate the total reactive power, the phase B. UPF Strategy
displacement between voltage and current at each harmonic Under this strategy, the damping provided by the load can
level must be zero, i.e., 1 = 2 = 3 = = n = 0. For be retained by shaping the source currents similar to the sup-
this strategy, the source current is free from harmonics; hence, ply voltages, which will play an important role in the case of
I2 = I3 = = In = 0. By substituting these values in (22), resonance phenomenon. The harmonic components, which are
the power factor becomes similar in the supply voltages and source currents, contribute
1 to the average load power to make the power factor unity. This
pf =  can be verified from (22). In order to get UPF, the currents
1 + THD2v have to be scaled to the voltages, i.e., In = kVn , where k is the
UYYURU et al.: OPTIMIZATION-BASED ALGORITHM FOR SHUNT ACTIVE FILTER UNDER DISTORTED SUPPLY VOLTAGES
TABLE IV
PARAMETERS FOR THE EXPERIMENTAL STUDY
conductance of the compensated load. Then (pf ), is as shown
at the bottom of this page.
The rms values of the source currents under this strategy
are less, but the compensator rating is high compared to all
other strategies, as given in Table II. The other drawback of this
strategy is that the distortion and unbalance in the currents are
same as in the supply voltages.
C. Optimization Control Algorithm
For the proposed optimization control algorithm, THD limits
of 5% and 10% in the compensated source currents are con-
sidered. First, 5% THD is allowed as per the IEEE-519 Stan-
dard [20]. From the results given in Table II, it can be seen
that the rms values of source currents are in between the UPF
(minimum) and PHC (maximum) strategies by satisfying the
standards of distortion current limit. The compensator rating
and power factor are also optimized between UPF (maximum)
and PHC (minimum) strategies. After that, 10% THD limit is
kept as a constraint to check the performance of the algorithm
and the results are shown in Tables III and IV. Though reduction
in rms values of source currents and increase in power factor
values are favorable for this limit of THD, the distortion in the
source current violates IEEE-519 Standards and the compen-
sator rating is increased.
From the results of the optimization control algorithm, by
considering different distortion limits as constraints, it is learned
that by taking 5% THD limit as constraint in the source, the al-
gorithm gives the balanced source currents with the best power
factor and satisfies the IEEE-519 Standards. Though the advan-
tage of reduction in rms values of source current and improve-
ment in the power factor are marginal in the UPF strategy and the
optimization control algorithm, these methods allow the preser-
vation of resistive part of the compensated load. This resistive
part plays an important role in diminishing the harmonic propa-
gation in the distribution system, which occurs due to harmonic
resonance [21].
V1 (kV1 ) + V2 (kV2 ) + V3 (kV3 ) +
pf =   = 1.
V12 + V22 + V32 + + Vn2 (kV1 )2 + (kV2 )2 + (kV3 )2 +
1229
Fig. 7. Power circuit diagram for experimental studies on a shunt active power
filter prototype model developed in laboratory.
Fig. 8. Block diagram for various blocks used in experimental setup.
VI. EXPERIMENTAL RESULTS
The previously proposed ideas have been verified by conduct-
ing detailed experiments on a shunt active filter prototype model
developed in the laboratory. The power circuit considered for the
experimental analysis is shown in Fig. 7. In order to get the de-
sired supply voltage, a programmable power source-305 AMX is
used. The total load consists of two parts; one is the unbalanced
linear load and another is the 3-phase diode bridge rectifier load
as described in Table IV. The shunt active filter is realized by an
H-bridge VSI. This topology is chosen due to its advantage of
having only one dc storage capacitor and its independent control
of each phase compensator current. This eliminates the problem
of dc voltage unbalance. The Y-connected transformers are used
to prevent the short-circuit of the dc storage capacitor for cer-
tain switching combinations of power switches in the H-bridge
VSI. Here, VSI is chosen instead of the current source inverter,
due to the less complicated circuit and better filtering of load
currents [22]. The various blocks used in the implementation of
the control algorithm are shown in Fig. 8. The supply voltages,
dc bus voltage, load currents, and filter currents are transformed
to 5 V range using the Hall effect voltage and current trans-
ducers. These are further processed through signal conditioning
circuit to convert to 03 V range compatible to 12-bit ADC
+ Vn (kVn )
+ (kVn )2
1230
Fig. 9. (a) Supply voltages for case 1. (b) Load currents for case 1. (c) Supply
voltages for case 2. (d) Load currents for case 2.
Fig. 10. PHC strategy. (a) Source currents for case 1. (b) Compensator currents
for case 1. (c) Source currents for case 2. (d) Compensator currents for case 2.
Fig. 11. UPF strategy source currents for case 1.
channels of DSP-TMS320F2812PGFA. The voltages and cur-
rents are sampled by the digital signal processor (DSP) at the
rate of 460 samples per cycle (at a sampling frequency 23 kHz).
In order to determine the frequency, the zero crossing instants
of the source voltage should be known. Extraction of this zero
crossing instants is not a problem under the stiff voltage source
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 5, MAY 2009
Fig. 12. OCA for 5% THD. (a) Source currents for case. 1 (b) Compensator
currents for case 1. (c) Source currents for case 2. (d) Compensator currents for
case 2.
Fig. 13. OCA for 10% THD. (a) Source currents for case 1. (b) Compensator
currents for case 1. (c) Source currents for case 2. (d) Compensator currents for
case 2.
and this can be implemented in the DSP itself. But in the case of
a nonstiff source, the source voltage contains switching harmon-
ics, and thus, the problem of multiple zero crossings will arise.
Hence, a dedicated synchronizing circuit is used to alleviate this
problem and to synthesize the quantities in the time domain,
synchronous with the phase-a voltage [23]. A dead time of
3.2 s required by the IPM PM50RVA120 is provided by the
blanking circuit to avoid the simultaneous conduction of the
IGBTs in the same leg. In the figure, an optoisolation circuit is
used to isolate the signal level circuit from the power circuit.
A protection circuit is used to prevent any abnormal operation
in terms of overrated voltage and current quantities, by stop-
ping the gate pulses from blanking the circuit. The DSP is pro-
grammed in code composer studio (CCS) on the host computer
for implementing the control strategies.
UYYURU et al.: OPTIMIZATION-BASED ALGORITHM FOR SHUNT ACTIVE FILTER UNDER DISTORTED SUPPLY VOLTAGES
TABLE V
EXPERIMENTAL RESULTS FOR OPTIMIZATION CONTROL ALGORITHM
For the balanced distorted (case 1) supply voltages, 50 V
rms (L-N) and 20% THD are considered for each phase. In
the unbalanced and distorted (case 2) supply voltages, 50 V,
60 V, 40 V rms (L-N) and THDs of 25%, 20%, 15% are taken
for the phases a, b, and c respectively. The parameters of the
unbalanced nonlinear load and compensated system are given
in Table IV. The programmed supply voltages for both the cases
are given in (23) and (24). These are shown in Fig. 9(a) and
(c), respectively. Load currents for both the cases are shown in
Fig. 9(b) and (d).
Case 1: Balanced Distorted Supply Voltages
For balanced distorted supply, following voltages are generated:
vsa = 70 sin(t) + 11 sin(5t) + 8.3 sin(7t)
vsb = 70 sin(t 1200 ) + 11 sin(5t + 1200 )
+ 8.3 sin(7t 1200 )
vsc = 70 sin(t + 1200 ) + 11 sin(5t 1200 )
+ 8.3 sin(7t + 1200 ). (23)
Case 2: Unbalanced Distorted Supply Voltages
The following voltages are considered for this case:
vsa = 68.60 sin(t) + 8.32 sin(5t) + 15.10 sin(7t)
vsb = 83.18 sin(t 1200 ) + 14.97 sin(5t + 1200 )
+ 7.48 sin(7t 1200 )
vsc = 55.92 sin(t + 1200 ) + 7.27 sin(5t 1200 )
+ 4.47 sin(7t + 1200 ). (24)
In order to show the ability of the algorithm in achieving
the desired compensation characteristics, different THD limits
on the compensated source currents were imposed. First, 0%
THD (PHC strategy) is taken and the corresponding results for
both the balanced distorted and unbalanced distorted cases are
shown in the Fig. 10(a)(d). In this strategy, the source currents
are compensated for total harmonics, unbalance, and reactive
power of the load. The UPF strategy source currents for the
balanced distorted case are shown in Fig. 11. From the figure,
it can be observed that the source currents have the same shape
as the supply voltage except for the switching frequency ripple,
which is present due to the hysteresis current control of the
VSI. Figs. 12(a)(d) show the source and compensated currents
for the THD limit of 5%, which is IEEE-519 compliant. This
1231
strategy gives the best compromise between the PHC and UPF
strategies. For illustrating the performance of the optimization
algorithm in compensating the source currents for the given
THD, the results of compensation for 10% THD limit are shown
in Fig. 13(a)(d).
The source current THD limits specified in the algorithm
are met with little deviation, owing to the switching frequency
ripples caused by the current modulation technique. However,
this effect can further be reduced by the use of an LCL
filter [24]. The experimental results of the optimization control
algorithm for two cases of supply voltages are given in Table V.
It can be observed from the table that the source current rms
values are less and power factor is more for THD limits close to
the supply voltage THDs.
VII. CONCLUSION
It has been shown that under distorted supply voltages any
effort to increase the power factor results in increased THD of
source currents and total compensation for current harmonics
does not provide the unity power factor. In this paper, an op-
timization control algorithm is proposed to get a compromise
between achieving unity power factor and THD current limits
with compensation of reactive power and unbalance. This con-
trol algorithm can be used under both balanced and unbalanced
distorted supply voltages. The compensation characteristics of
three control strategies, i.e., PHC, UPF, and optimization-based
algorithm are compared. Experimental verification was carried
out on a reduced-scale prototype of DSP-TMS320F2812PGFA-
based shunt APF. From the results, it is clear that the proposed
optimization control algorithm renders the best possible com-
promise between the power factor and the harmonic distortion
along with preserving the resistive part of the compensated load.
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Koteswara Rao Uyyuru received the B.Tech. de-
gree from Jawaharlal Nehru Technological Univer-
sity, Hyderabad, India, in 2003. He is currently work-
ing toward the Ph.D. degree in the Department of
Electrical Engineering, Indian Institute of Technol-
ogy (IIT) Madras, Chennai, India.
From 2003 to 2004, he was a Lecturer in Sri.
Adsumilli Aswardha Narayana Murthy (AANM)
and Sri. Valluripalli Venkata Rama Seshadri Rao
(VVRSR) Polytechnic, Gudlavalleru, India. From
2004 to 2005, he was an Assistant Engineer in the
Southern Power Distribution Company, Andhra Pradesh Ltd., Tirupathi, India.
His current research interests include power quality, power electronic devices,
and power electronics applications in power systems.
Mahesh K. Mishra (S00M02) received the
B.Tech. degree from the College of Technology,
Pantnagar, India, in 1991, the M.E. degree from the
University of Roorkee, Roorkee, India, in 1993, and
the Ph.D. degree in electrical engineering from the
Indian Institute of Technology, Kanpur, India, in
2002.
He has teaching and research experience of 17
years. For about ten years, he was in the Electrical
Engineering Department, Visvesvaraya National In-
stitute of Technology, Nagpur, India. He is currently
an Assistant Professor in the Department of Electrical Engineering, Indian In-
stitute of Technology Madras, Chennai, India. His current research interests
include power distribution systems, power electronics, and control systems.
Dr. Mahesh is a Life Member of the Indian Society of Technical Education
(ISTE).
Arindam Ghosh (S80M83SM93F06) received the Ph.D. degree in elec-
trical engineering from the University of Calgary, Calgary, AB, Canada, in 1983.
He is currently a Professor of power systems at Queensland University of
Technology, Brisbane, Qld., Australia. From 1985 to 2006, he was with the
Department of Electrical Engineering, Indian Institute of Technology (IIT),
Kanpur, India. He held visiting positions with Nanyang Technological Univer-
sity, Singapore, the University of Queensland, Brisbane, and Queensland Uni-
versity of Technology. His current research interests include control of power
systems and power-electronic devices.