MODELING OF HVDC-MMC TRANSMISSION SYSTEM

FOR ELECTROMAGNETIC TRANSIENTS

June 21st 2013
Hani SAAD
Ph.D. student

Director: Prof. J. Mahseredjian, cole Polytechnique de Montral, Canada

Co-director: Prof. X. Guillaud, cole Centrale de Lille, France

Industrial partner : RTE-France

Co-directors of project: S. Nguefeu and S. Dennetire
 2

Plan:
1. Introduction
2. MMC topology overview
3. MMC models
4. Control system
5. HVDC-MMC model in EMTP-RV
 3

1. Introduction

VSC based HVDC transmission system is expanding rapidly.

The recent Modular Multilevel Converter (MMC) topology offers significant
benefit compared to previous VSC technologies

Advantages of Modular Multilevel Converter (MMC):

Low frequency modulation
Lower transient peak voltages on IGBT, which will lead to a lower losses
Very low THD, hence no need for High-pass filters or very small size
Modular structure, scalable to different power and voltage levels
 4

2. MMC topology overview

Idc At normal operation, S1 and S2 are
Arm
iua iub iuc complementary
SM SM-1 SM-1 SM-1 The sub-module consist of two states:
vup _a
Su->on and Sl->off
SM-2 SM-2 SM-2
Su->off and Sl->on
.. .. ..
. . . Sub-Module
ON State OFF State
SM-N SM-N SM-N

Su
Ls Ls Ls On Su Off Su
va C
ia Sl Sl
vb Sl Off On
ib
vc
ic Vdc
On Su Off Su
Ls Ls Ls

SM-1 SM-1 SM-1 Off Sl On Sl

SM
vlow _a SM-2 SM-2 SM-2

.. .. ..
. . .
SM-N SM-N SM-N

ila ilb ilc

On Off
 5

3. MMC models
Depending on the type of study different type of modeling are presented:
Model 1 Model based on nonlinear IGBT models
Model 2 Model based on simplified switchable resistance
Model 3 Switching Function of Arm (SF-arm)
Model 4 Average Value Model of MMC (AVM-MMC)

..
.
..
.

Model 1 Model 2 Model 3 Model 4

 6

3. MMC models
Model 1 - Models based on nonlinear IGBT models
In this case IGBT/diode are modeled by nonlinear resistor and an ideal switch.

p p

p p Entered characteristic plot

g S1
g

RLC +
n C

pp 1
K1 K2
p
S2
p
vc_1

Voltage (V)
g S1 0.8
g S1
g n

RLC +
g n C

RLC +
g 0.6
K1 K2 S2

g n C p p
n

0 1000 2000 3000 4000 g S1

g

RLC +
Current (A) n C
K2 nS2
n p p
K1 K2 S2
vc_2
g S1
n
g

RLC +
n n C

K1 K2 S2

p p
n

g S1
g

RLC +
n C

Advantages: K1 K2
p
S2
p
vc_400
Very easy to achieve, it preserve the main structure of the IGBT g S1
g n

RLC +
n C

The V-I curve of the IGBT/diode is modeled. K1 K2 S2

Inconvenient:
Computation time is high
 7

3. MMC models S S
pos pos

Vc
Vc

S1 S1 vc1 Vc1

pos
S2 S2 vc2 Vc2
S3 S3 vc3 Vc3
S4 S4 vc4 Vc4
S5 Vc5
S6
S5 10 SM vc5
Vc6
S6 vc6
S7 S7 vc7 Vc7
S8 S8 vc8 Vc8
S9 10SM1 Vc9
S9 vc9
S10

pos ph
S10 vc10 Vc10
S11 S1 vc1 Vc11
S12 S2 vc2 Vc12
S13 S3 vc3 Vc13
S14 S4 vc4 Vc14
P S15 S5
10 SM vc5 Vc15
S16 S6 vc6 Vc16
P S17 S7 vc7 Vc17
S18 S8 vc8 Vc18
S19 10SM2 Vc19
S9 vc9
S20

pos ph
S10 vc10 Vc20

MMC_401L Base i_ar m

S21
S22
S23
S24
S25
S1
S2
S3
S4
vc1
vc2
vc3
vc4
Vc21
Vc22
Vc23
Vc24
Vc25

i(t)
Base i_ar m Base i_ar m S26
S5 10 SM vc5
Vc26

i(t)

i(t)
S6 vc6
i_up_C S27 Vc27
i_up_A i_up_B i_up_C i_arm_pu i_arm_A S28
S7
S8
vc7
vc8 Vc28
i_arm_pu i_arm_A i_arm_pu i_arm_A
P i_up_A i_up_B S29 10SM3 Vc29
S9 vc9

pos ph
iuc
S30 S10 vc10 Vc30
S31 Vc31

iua

iub
S1 vc1
S32 S2 vc2 Vc32
S33 S3 vc3 Vc33

MMC 401Levels
S34 S4 vc4 Vc34

AC S35
S36
S37
S5
S6
S7
10 SM vc5
vc6
vc7
Vc35
Vc36
Vc37

N S38
S39
S40
S8
S9
10SM4
vc8
vc9
Vc38
Vc39

pos ph
S10 vc10 Vc40
S41 S1 vc1 Vc41
S42 S2 vc2 Vc42
S43 S3 vc3 Vc43
S44 S4 vc4 Vc44
S45 Vc45
S46
S5 10 SM vc5
Vc46
S6 vc6
S47 S7 vc7 Vc47
S48 S8 vc8 Vc48

Input Ouput
S49 10SM5 Vc49
S9 vc9
S50

pos ph
S10 vc10 Vc50
S51 S1 vc1 Vc51
S52 S2 vc2 Vc52
S53 S3 vc3 Vc53
S54 S4 vc4 Vc54
S55 S5 vc5 Vc55

pos
S56
10 SM Vc56
S6 vc6

pos
S57 S7 vc7 Vc57

pos
S58 S8 vc8 Vc58
S59 10SM6 Vc59
S9 vc9
S60

pos ph
S10 vc10 Vc60
S61 S1 vc1 Vc61
S_ u p _ A
S 400 SM Vc Vc _ u p _ A S_ u p _ B 400 SM
S62 S2 vc2 Vc62

S_up_A Vc_up_A
S63 Vc63
S Vc S3 vc3
Vc _ u p _ B S_ u p _ C S 400 SM Vc Vc _ u p _ C
S64
S65
S66
S4
S5
S6
10 SM
vc4
vc5
vc6
Vc64
Vc65
Vc66
S67 Vc67

ph
S7 vc7
S68 Vc68

ph
4 0 0 SM _ u p _ A S8 vc8

S_low_A Vc_low_A
S69 10SM7 Vc69

ph
4 0 0 SM _ u p _ B S9 vc9

pos ph
S70 Vc70
4 0 0 SM _ u p _ C S71
S10
S1
vc10
vc1 Vc71
S72 S2 vc2 Vc72
S73 S3 vc3 Vc73
S74 S4 vc4 Vc74
S75 Vc75
S5 10 SM vc5

S_up_B Gate Capa.

S76 S6 vc6 Vc76
S77 Vc77

Vc_up_B
S7 vc7
S78 S8 vc8 Vc78

# L a rm #
S79 10SM8 Vc79
S9 vc9

L _ a rm 2

# L a rm #
S80

pos ph
S10 vc10 Vc80

L _ a rm 3
# L a rm #
S81 S1 vc1 Vc81

L _ a rm 1
S82 S2 vc2 Vc82

S_low_B signals Voltages Vc_low_B

S83 S3 vc3 Vc83
S84 S4 vc4 Vc84

+
S85 Vc85
S5 10 SM vc5

+
S86 S6 vc6 Vc86

+
S87 S7 vc7 Vc87
S88 S8 vc8 Vc88
S89 10SM9 Vc89
S9 vc9
S90

pos ph
S10 vc10 Vc90
S91 S1 vc1 Vc91

S_up_C Vc_up_C a
S92
S93
S94
S95
S96
S97
S2
S3
S4
S5
S6
10 SM
vc2
vc3
vc4
vc5
vc6
Vc92
Vc93
Vc94
Vc95
Vc96
Vc97
S7 vc7

S_low_C Vc_low_C AC
AC b S98
S99
S100
S8
S9
10SM10
vc8
vc9
Vc98
Vc99

pos ph
S10 vc10 Vc100
S101 S1 vc1 Vc101
S102 S2 vc2 Vc102
S103 S3 vc3 Vc103
S104 S4 vc4 Vc104
c S105
S106
S5
S6
10 SM vc5
vc6
Vc105
Vc106
S107 S7 vc7 Vc107
S108 S8 vc8 Vc108

i_up_A
S109 10SM11 Vc109
S9 vc9
S110

pos ph
S10 vc10 Vc110

# L a rm #
S111 S1 vc1 Vc111

L _ a rm 4

# L a rm #
S112 S2 vc2 Vc112

L _ a rm 6
S113 S3 vc3 Vc113
S114 S4 vc4 Vc114

i_low_A

# L a rm #
L _ a rm 5
S115 Vc115
S116
S5 10 SM vc5
Vc116
S6 vc6

+
S117 S7 vc7 Vc117

+
S118 S8 vc8 Vc118
S119 10SM12 Vc119
S9 vc9

pos ph
S120 S10 vc10 Vc120

+
Current
S121 S1 vc1 Vc121
S122 S2 vc2 Vc122

i_up_B
S123 S3 vc3 Vc123
S124 S4 vc4 Vc124
S125 Vc125
S126
S5 10 SM vc5
Vc126
S6 vc6
S127 S7 vc7 Vc127

Arms
S128 S8 vc8 Vc128

i_low_B
S129 10SM13 Vc129
S9 vc9
S130

pos ph
S10 vc10 Vc130
S131 S1 vc1 Vc131
S132 S2 vc2 Vc132

pos

pos

pos
S133 S3 vc3 Vc133
S134 S4 vc4 Vc134
S135 Vc135
S136
S5 10 SM vc5
Vc136
S6 vc6
S137 S7 vc7 Vc137

i_up_C S_ l o w_ A
S 400 SM Vc Vc _ l o w_ A
S_ l o w_ B
S 400 SM Vc Vc _ l o w_ B
S_ l o w_ C
S 400 SM Vc Vc _ l o w_ C
S138
S139
S140
S8
S9
10SM14
vc8
vc9
Vc138
Vc139

pos ph
S10 vc10 Vc140
S141 S1 vc1 Vc141
S142 S2 vc2 Vc142

i_low_C
S143 S3 vc3 Vc143
S144 S4 vc4 Vc144

ph

ph

ph
S145 S5 vc5 Vc145
4 0 0 SM _ l o w_ A 4 0 0 SM _ l o w_ B 4 0 0 SM _ l o w_ C S146
10 SM Vc146
S6 vc6
S147 S7 vc7 Vc147
S148 S8 vc8 Vc148
S149 10SM15 Vc149
S9 vc9
S150

pos ph
S10 vc10 Vc150
S151 S1 vc1 Vc151
S152 S2 vc2 Vc152
S153 S3 vc3 Vc153
S154 S4 vc4 Vc154
S155 S5 vc5 Vc155
S156
10 SM Vc156
S6 vc6
S157 S7 vc7 Vc157
S158 S8 vc8 Vc158
S159 10SM16 Vc159
S9 vc9

pos ph
S160 S10 vc10 Vc160
S161 S1 vc1 Vc161
S162 S2 vc2 Vc162
S163 S3 vc3 Vc163
S164 S4 vc4 Vc164
S165 Vc165
S166
S5 10 SM vc5
Vc166
S6 vc6
S167 S7 vc7 Vc167
S168 S8 vc8 Vc168
Base i_ar m Base i_ar m Base i_ar m

i(t)

i(t)

i(t)
S169 10SM17 Vc169
S9 vc9

VSC-MMC 401 levels

S170

pos ph
S10 vc10 Vc170
i _ l o w_ A i _ l o w_ B i _ l o w_ C S171 S1 vc1 Vc171
i _ l o w_ A i_arm_pu i_arm_A i _ l o w_ B i_arm_pu i_arm_A i _ l o w_ C i_arm_pu i_arm_A S172 S2 vc2 Vc172
S173 S3 vc3 Vc173
S174 Vc174

ila

ilb
S4 vc4

ilc
S175 Vc175
S176
S5 10 SM vc5
Vc176
S6 vc6
S177 S7 vc7 Vc177
S178 S8 vc8 Vc178
N S179 S9
10SM18
vc9 Vc179
N S180

pos ph
S10 vc10 Vc180
S181 S1 vc1 Vc181
S182 S2 vc2 Vc182
S183 S3 vc3 Vc183
S184 S4 vc4 Vc184
S185 Vc185
S186
S5 10 SM vc5
Vc186
S6 vc6

Model 1
S187 S7 vc7 Vc187
S188 S8 vc8 Vc188
S189 10SM19 Vc189
S9 vc9
S190

pos ph
S10 vc10 Vc190
S191 S1 vc1 Vc191
S192 S2 vc2 Vc192
S193 S3 vc3 Vc193
S194 S4 vc4 Vc194
pos S195 S5 vc5 Vc195
S196
10 SM Vc196
S6 vc6
S197 S7 vc7 Vc197
S198 S8 vc8 Vc198
S199 10SM20 Vc199
S9 vc9
SM_11 S200

pos ph
S10 vc10 Vc200
S201 Vc201
Sub-module (SM)
S1 vc1
S202 S2 vc2 Vc202
Gate_signals S203 S3 vc3 Vc203
S204 S4 vc4 Vc204
S205 Vc205
if S=0 --> [S1 S2] = [0 1] S5 10 SM vc5
S1 S1 S206 S6 vc6 Vc206
S1 S if S=1 --> [S1 S2] = [1 0] S207 S7 vc7 Vc207
if S=2 --> [S1 S2] = [0 0] S2 S2 S208 S8 vc8 Vc208
S209 10SM40 Vc209
S9 vc9
if S=3 --> [S1 S2] = [1 1]

pos ph
S210 S10 vc10 Vc210
V1 Vc vc1 S211 S1 vc1 Vc211
S212 S2 vc2 Vc212
S213 S3 vc3 Vc213
S214 S4 vc4 Vc214
S215 Vc215
S216
S5 10 SM vc5
Vc216
V0 S217
S6
S7
vc6
vc7 Vc217
S218 S8 vc8 Vc218

Total IGBT/diode in the HVDC-MMC 401 Level system:

S219 10SM41 Vc219
S9 vc9
SM_12 S220

pos ph
S10 vc10 Vc220

Sub-module (SM) S221

S222
S1
S2
vc1
vc2
Vc221
Vc222
Gate_signals S223 S3 vc3 Vc223
S224 S4 vc4 Vc224
if S=0 --> [S1 S2] = [0 1] S225 S5 10 SM vc5 Vc225
S1 S1 S226 S6 vc6 Vc226
S2 S if S=1 --> [S1 S2] = [1 0]
if S=2 --> [S1 S2] = [0 0] S2 S2 S227
S228
S7
S8
vc7
vc8
Vc227
Vc228
S229 10SM42 Vc229
if S=3 --> [S1 S2] = [1 1] S230
S9 vc9

pos ph
Vc230
V1 Vc vc2 S231
S10
S1
vc10
vc1 Vc231
S232 S2 vc2 Vc232
S233 S3 vc3 Vc233
S234 S4 vc4 Vc234
S235 S5 vc5 Vc235
10 SM
V0

2(IGBT/SM)*400(SM/arms)*2(arms/phase)*3(phases)*2(converters)
S236 S6 vc6 Vc236
S237 S7 vc7 Vc237
S238 S8 vc8 Vc238
S239 10SM43 Vc239
SM_13 S9 vc9
S240

pos ph
S10 vc10 Vc240

Sub-module (SM) S241

S242
S1 vc1 Vc241
Vc242
Gate_signals S243
S2
S3
vc2
vc3 Vc243
S244 S4 vc4 Vc244
if S=0 --> [S1 S2] = [0 1] S245 S5 vc5 Vc245
S1 S1 10 SM
S3 S if S=1 --> [S1 S2] = [1 0] S246 S6 vc6 Vc246

if S=2 --> [S1 S2] = [0 0] S2 S2 S247 S7 vc7 Vc247

S248 S8 vc8 Vc248
10SM44
if S=3 --> [S1 S2] = [1 1] S249 S9 vc9 Vc249
V1 Vc

pos ph
vc3 S250
S251
S10 vc10 Vc250
Vc251
S1 vc1
S252 S2 vc2 Vc252
S253 S3 vc3 Vc253

= 9 500 IGBTs/diodes
S254 S4 vc4 Vc254
S255 Vc255
V0 S256
S5 10 SM vc5
Vc256
S6 vc6
S257 S7 vc7 Vc257
S258 S8 vc8 Vc258
SM_14 S259 S9
10SM45
vc9 Vc259
S260

pos ph
S10 vc10 Vc260
Sub-module (SM) S261 S1 vc1 Vc261
Gate_signals S262
S263
S2
S3
vc2
vc3
Vc262
Vc263
S264 S4 vc4 Vc264
if S=0 --> [S1 S2] = [0 1]
S1 S1 S265 S5 10 SM vc5 Vc265
S4 S if S=1 --> [S1 S2] = [1 0] S266 S6 vc6 Vc266

if S=2 --> [S1 S2] = [0 0] S2 S2 S267 S7 vc7 Vc267

S268 S8 vc8 Vc268
if S=3 --> [S1 S2] = [1 1] S269 S9
10SM46
vc9 Vc269
V1 Vc vc4 S270

pos ph
S10 vc10 Vc270
S271 S1 vc1 Vc271
S272 S2 vc2 Vc272
S273 S3 vc3 Vc273
S274 S4 vc4 Vc274
S275 Vc275
V0 S276
S5
S6
10 SM vc5
vc6 Vc276
S277 S7 vc7 Vc277
S278 S8 vc8 Vc278
SM_15 S279 S9
10SM47
vc9 Vc279

Sub-module (SM)
S280

pos ph
S10 vc10 Vc280
S281 S1 vc1 Vc281
Gate_signals S282 S2 vc2 Vc282
S283 S3 vc3 Vc283
if S=0 --> [S1 S2] = [0 1] S284 S4 vc4 Vc284
S1 S1 S285 S5
10 SM vc5 Vc285
S5 S if S=1 --> [S1 S2] = [1 0] S286 S6 vc6 Vc286
if S=2 --> [S1 S2] = [0 0] S2 S2 S287 S7 vc7 Vc287
S288 S8 vc8 Vc288
if S=3 --> [S1 S2] = [1 1] S289 S9
10SM48
vc9 Vc289
V1 Vc vc5 S290

pos ph
S10 vc10 Vc290
S291 S1 vc1 Vc291
S292 S2 vc2 Vc292
S293 S3 vc3 Vc293
S294 S4 vc4 Vc294
V0 S295
S296
S5 10 SM vc5 Vc295
Vc296
S6 vc6
S297 S7 vc7 Vc297
S298 S8 vc8 Vc298
SM_16 S299 S9
10SM49
vc9 Vc299

D Sub-module (SM)

pos ph
S300 S10 vc10 Vc300
S301 S1 vc1 Vc301
Gate_signals S302 S2 vc2 Vc302
S303 S3 vc3 Vc303
if S=0 --> [S1 S2] = [0 1] S304 S4 vc4 Vc304
S1 S1 S305 Vc305
S6 S if S=1 --> [S1 S2] = [1 0] S5 10 SM vc5

if S=2 --> [S1 S2] = [0 0] S2 S2 S306

S307
S6 vc6 Vc306
Vc307
S7 vc7
S308 Vc308
if S=3 --> [S1 S2] = [1 1] S309
S8
10SM50
vc8
Vc309
V1 Vc vc6 S9 vc9

S1
S310

pos ph
S10 vc10 Vc310
S311 S1 vc1 Vc311
S312 S2 vc2 Vc312
S313 S3 vc3 Vc313
S314 S4 vc4 Vc314
V0 S315 S5 10 SM vc5 Vc315
S316 S6 vc6 Vc316
S317 S7 vc7 Vc317
SM_17 S318 S8
10SM51
vc8 Vc318
S319 S9 vc9 Vc319
Sub-module (SM) S320

pos ph
S10 vc10 Vc320
+

Gate_signals S321
S322
S1
S2
vc1
vc2
Vc321
Vc322
S323 S3 vc3 Vc323

V1 #Cp# Cp S7 S
if S=0 --> [S1 S2] = [0 1]
if S=1 --> [S1 S2] = [1 0]
S1
S2
S1
S2
S324
S325
S326
S4
S5
S6
10 SM
vc4
vc5
vc6
Vc324
Vc325
Vc326
+

if S=2 --> [S1 S2] = [0 0] S327 S7 vc7 Vc327

if S=3 --> [S1 S2] = [1 1] S328 S8 vc8 Vc328
+

V1 Vc vc7 S329 S9
10SM52
vc9 Vc329
RLC +

G !v
S330

pos ph
S10 vc10 Vc330
1M

S331 S1 vc1 Vc331

S332 S2 vc2 Vc332
S333 S3 vc3 Vc333
S334 S4 vc4 Vc334
V0 S335 S5 vc5 Vc335
S336
10 SM Vc336
S6 vc6
S337 S7 vc7 Vc337
SM_18 S338 S8 vc8 Vc338
10SM53

S2
S339 Vc339
Sub-module (SM)
S9 vc9

pos ph
S340 S10 vc10 Vc340
Gate_signals S341
S342
S1 vc1 Vc341
Vc342
S2 vc2
S343 S3 vc3 Vc343
if S=0 --> [S1 S2] = [0 1]
S1 S1 S344 S4 vc4 Vc344
S8 S if S=1 --> [S1 S2] = [1 0] S345 S5 10 SM vc5 Vc345
if S=2 --> [S1 S2] = [0 0] S2 S2 S346 S6 vc6 Vc346
S347 S7 vc7 Vc347
if S=3 --> [S1 S2] = [1 1] S348 S8 vc8 Vc348
V1 Vc vc8 S349 S9
10SM54
vc9 Vc349
S350

pos ph
S10 vc10 Vc350
S351 S1 vc1 Vc351
S352 S2 vc2 Vc352
S353 S3 vc3 Vc353

nonlinear diode model

S354 Vc354
V0 S355
S4 vc4
Vc355

V0 S356
S5 10 SM vc5
Vc356
S6 vc6
S357 S7 vc7 Vc357
SM_19 S358 S8 vc8 Vc358
10SM55
Sub-module (SM)
S359 S9 vc9 Vc359
S360

pos ph
S10 vc10 Vc360
Gate_signals S361 S1 vc1 Vc361
S362 S2 vc2 Vc362
if S=0 --> [S1 S2] = [0 1] S363 S3 vc3 Vc363
S1 S1 S364 S4 vc4 Vc364
S9 S if S=1 --> [S1 S2] = [1 0] S365 Vc365
if S=2 --> [S1 S2] = [0 0] S2 S2 S366
S5
S6
10 SM vc5
vc6 Vc366
S367 S7 vc7 Vc367
if S=3 --> [S1 S2] = [1 1] S368 S8 vc8 Vc368
V1 Vc vc9 S369 S9
10SM56
vc9 Vc369
S370

pos ph
S10 vc10 Vc370

p2 + S
S371
S372
S1
S2
vc1
vc2
Vc371
Vc372

p1
S373 S3 vc3 Vc373
V0 S374 S4 vc4 Vc374
S375 S5 vc5 Vc375
S376
10 SM Vc376
S6 vc6
S377 Vc377
SM_20 S378
S7 vc7
Vc378
S8 vc8
Sub-module (SM) S379 10SM57 Vc379
S9 vc9
0

S380

pos ph
S10 vc10 Vc380
Gate_signals S381 S1 vc1 Vc381
S382 S2 vc2 Vc382
if S=0 --> [S1 S2] = [0 1]
Rn1

S383 S3 vc3 Vc383

S1 S1 S384 Vc384
S10 S if S=1 --> [S1 S2] = [1 0] S4 vc4

if S=2 --> [S1 S2] = [0 0] S2 S2 S385

S386
S5 10 SM vc5 Vc385
Vc386
S6 vc6
if S=3 --> [S1 S2] = [1 1] S387 S7 vc7 Vc387
S388 Vc388
V1 Vc vc10 S389
S8
S9
10SM58
vc8
vc9 Vc389

pos ph
S390 S10 vc10 Vc390
S391 S1 vc1 Vc391
S392 S2 vc2 Vc392
S393 S3 vc3 Vc393
V0 S394 S4 vc4 Vc394
S395 Vc395
S396
S5 10 SM vc5
Vc396
S6 vc6
S397 S7 vc7 Vc397
S398 S8 vc8 Vc398
S399 10SM59 Vc399
S9 vc9
S400

ph
S10 vc10 Vc400
ph
ph ph
 8

3. MMC models
Model 2 - Models based on simplified switchable resistance
IGBT and diodes are represented by two-value resistors (Ron and Roff). A reduction is
performed to reduce the number of electrical nodes that describe converter.
iarm

r1_1
C vc_1 Rc req
r2_1 Vc_eq1
varm
veq

r1_2
Rc
C vc_2 Vc_eq2
r2_2 N N
varm (t ) rSM _ eq _ i (t ) .iarm (t ) vSM _ eq _ i (t T )
i 1 i 1

r 2(t ). r1(t ) Rc
r1_400 rSM _ eq (t )
C vc_400 Rc r 2(t ) r1(t ) Rc )
r2_400 Vc_eq400
v r 2(t )
(t T ) v (t T ).
SM _ eq
r 2(t ) r1(t ) Rc
c _ eq

Advantages:
Reduction of electrical nodes to 3 nodes, without loosing the variable information of each SM.
Low computation time
Inconvenient:
The model is hard-coded, hence the user has no more access to SM circuits
The V-I curve of IGBT/diode is not modeled
 9

3. MMC models

MMC_401L1
P
AC Detailed Equivalent-Circuit-based Model (DECM) N

Input MMC 401Levels Ouput

S_up_A Vc_up_A
S_low_A Vc_low_A
S_up_B Gate Capa. Vc_up_B
S_low_B signals Voltages Vc_low_B
+

S_up_C Vc_up_C P

S_low_C Vc_low_C

i(t)
i(t)

i(t)
i_up_C
i_up_A i_up_A i_up_B
+

i_low_A
Current i_up_B
Arms i_low_B S_up_A MMC arm
Vc_up_A MMC arm MMC arm
SM1
i_up_C S_up_B
SM1
Vc_up_B S_up_C
SM1
Vc_up_C
Vc1
i_low_C Vc1 Vc1
SM2
SM2 SM2
Varm_upA + Vc2
scope V Vc2 Vc2
- ..
..
. .. ..
SMi .. ..
. .

MMC Model 2
SMi SMi
Vci Vc_tot_upA
Vc_tot scope Vci Vci
Vc_tot Vc_tot
arm_upA
ModelData=MMC_arm_DLLemtp_06112012, arm_upB arm_upC
#Cp#, #Vc_init#, #Rlosses#, 1e4 ,20 ModelData=MMC_arm_DLLemtp_06112012, ModelData=MMC_arm_DLLemtp_06112012,
ParamsA=2,0,0,2,20,21,1, #Cp#, #Vc_init#, #Rlosses#, 1e4 ,20 #Cp#, #Vc_init#, #Rlosses#, 1e4 ,20
ParamsA=2,0,0,2,20,21,1, ParamsA=2,0,0,2,20,21,1,

#Larm#

#Larm#
#Larm#

+
+
a

AC

c #Larm#

#Larm#
#Larm#
+

+
+
MMC arm MMC arm MMC arm
S_low_A Vc_low_A S_low_B Vc_low_B S_low_C Vc_low_C
SM1 SM1 SM1

Vc1 Vc1 Vc1

Varm_lowA +
scope V
- SM2 SM2 SM2

Vc2 Vc2 Vc2

.. .. ..
.. .. ..
. . .
SMi SMi SMi

Vci Vc_tot_lowA Vci Vci

Vc_tot scope Vc_tot Vc_tot

DLL block
arm_lowA arm_lowB arm_lowC
ModelData=MMC_arm_DLLemtp_06112012, ModelData=MMC_arm_DLLemtp_06112012, ModelData=MMC_arm_DLLemtp_06112012,
#Cp#, #Vc_init#, #Rlosses#, 1e4 ,20 #Cp#, #Vc_init#, #Rlosses#, 1e4 ,20 #Cp#, #Vc_init#, #Rlosses#, 1e4 ,20
ParamsA=2,0,0,2,20,21,1, ParamsA=2,0,0,2,20,21,1, ParamsA=2,0,0,2,20,21,1,

Fortran 95 code
i(t)

i(t)

i(t)
i_low_A i_low_B i_low_C

N
 10

3. MMC models
Model 3 Switching function of Arm
Each MMC arm are modeled as controlled current and voltage sources for ON/OFF states and
half diode bridge for Blocked state.
These models can be used to study harmonics generated and control system which account
for energy regulation of MMC-arm.
It suppose that Capacitor voltages balancing control operate correctly
vCtot
Assuming that: vC1 vC2 ... vCi
N

varm sn .vCtot NRON iarm vCtot iarm

X X
sn sn
iCtot sn .iarm iarm + NRON +
iCtot

+
+ D +
-
N -

i S a) ON/OFF states C
where: sn i 1
varm vCtot
+ N
N D1
- -
+
Si 1 -> For ON state NRON
D2 -
-
Si 0 -> For OFF state
b) BLOCKED state
 11

3. MMC models

MMC_SF_arm
P
AC
Switching function model N
of MMC arm
S_up_A Vctot_up_A
S_low_A Vctot_low_A
S_up_B Vctot_up_B
S_low_B
+ Vctot_low_B
S_up_C Vctot_up_C
S_low_C Vctot_low_C
P

i_up_A

i(t)
i_low_A i_up_A

i(t)

i(t)
i_up_B i_up_C

i_up_B
i_low_B arm_up_phA arm_up_phB arm_up_phC

SF-arm SF-arm SF-arm

i_up_C
Vpos Vpos Vpos
i_low_C + + + +
scope V
Varm_up_A - Vneg Vneg Vneg

S_up_A s_arm Vc_tot_arm Vctot_up_A S_up_B s_arm Vc_tot_arm Vctot_up_B S_up_C s_arm Vc_tot_arm Vctot_up_C

MMC Model 3 mmc mmc

#Larm#
#Larm#

L19
#Larm#

L17
L10

+
+
+

AC

#Larm#
#Larm#

#Larm#
L18
L16

L20
+
+

+
arm_low_phA
arm_low_phB arm_low_phC
SF-arm SF-arm SF-arm
Vpos
Vpos Vpos
+ +
scope V + +
Varm_low_A - Vneg
Vneg Vneg

S_low_A s_arm Vc_tot_arm Vctot_low_A

S_low_B s_arm Vc_tot_arm Vctot_low_B S_low_C s_arm Vc_tot_arm Vctot_low_C
i(t)

DLL block
i(t)

i(t)
i_low_A
i_low_B i_low_C

Fortran 95 code
 12

3. MMC models
Model 4 AVM (Average Value Model)
The AC and DC side characteristics are modeled as controlled current and voltage sources.
These models can be used to study harmonics generated by such converters.
AVM model suppose that internal variables of MMC (Capacitor voltages and current of each
arm) are controlled correctly

AC side: DC side:
= , ,
= =
2
1
=
= 2
2 =,,

vrefabc
vrefabc
= . /2
1

va + 2 Rloss Larmdc
+ +

vb
+

+
econva

+
Larm / 2

+
C dc Vdc
+

vc +
econvb I dc
+

econvc
 13

3. MMC models

AVM1
P
AC
AVM N
MMC
varef
vbref +
vcref
Trip

MMC Model 4
Page Ia
Page Ib
Page Ic

Trip

c
R1 L1
i(t) Iac + +
P
AC b #R_eq_DCside_AVM# #Larm_eq_DCside_AVM#

a
#Larm_eq_ACside_AVM#

#Larm_eq_ACside_AVM#

#Larm_eq_ACside_AVM#

+
L2
+

L3
+

L4
+

DCside1 C1 +

+
DC_side #C_eq_DCside_AVM# V Page Vc_tot
!v -
Varef Page Vref_phA

+
Vbref Page Vref_phB
I_dc cI1
Vcref Page Vref_phC
0/1e15
Ia Page Iac_phA

+
AC_side_phA AC_side_phB
AC_side_phC Ib Page Iac_phB
AC_side AC_side AC_side
Ic Page Iac_phC
+

Vc_tot Page Vdc Vc_tot Page Vdc

+

Vac Vac Vc_tot Page Vdc

Varef Page Vref Vbref Page Vref Vac
0/1e15 0/1e15 Vcref Page Vref
0/1e15

N
 14

4. Control system
Basic idea:
By linearizing the power equation, active and reactive power can be decoupled, thus:
Regulating the phase angle -> active power is controlled
Regulating the voltage amplitude -> reactive power is controlled

S R
+
VSVR
X
P
R sin( ) PR fct ( )
X
+

+

Q VSVR cos( ) VR
2
QR fct (VR )
R X

However the control system is much more complex

Upper control (VSC control)

Since MMC topology is a VSC type, the generic Outer/Inner Control can be used

Lower control (MMC control)

Controller related to the MMC topology, in order to control internal variables

14
 15

4. Control system

Control system structure

MMC
Yg/
AC side DC
side

gate signal
measurements
CBA

Lower level control

Upper level control

supabc et slowabc
Outer Control
P/Q/Vdc NLC
Modulation

vup
SM
abc
et
v SM
lowabc
Inner Control
CCSC

eabc
 16

5. HVDC-MMC model in EMTP-RV

HVDC link modeled in EMTP-RV

Pac control VDC control

VSC_1 Cable_70km1 VSC_2

SRC1 SRC2
MMC P1 P2 MMC
+ +

N1 N2
monopole monopole
model1 model1
400 SM 100 SM
Equivalent source

VSC-MMC station

Underground cable
DC fault AC fault (3LT)
pole-to-pole

NB: This test case is included in the examples folder of EMTP-RV 2.5
 17

5. HVDC-MMC model in EMTP-RV

Section related with Type of model and circuit configuration

Section related with electrical parameters

of the MMC station

Section related with the start-up sequence if checked

 18

5. HVDC-MMC model in EMTP-RV

Section related with the

control type

Section related with protection system

 19

5. HVDC-MMC model in EMTP-RV

Subsystem structure of the VSC-MMC station

Power Transformer MMC model 1 to 4

Page V_Secondary_Transfo

Page I_Secondary_Transfo
Page V_Primary_Transfo

Page I_Primary_Transfo

Page Converter_BRK
Page AC_BRK

Page Idc

i(t)
AC_Converter p

+ MMC_21L1

AC side DC side
Converter_Tfos
+
v

AC_convertor_BRK
i

1 2 P
+ V Page Vdc
AC
-30
+
AC
MMC 21Levels N -
AC_BRK Primary2 1/1 Secondary2
1000
Exported Mask Input Ouput
Exported Mask, S_up_A Page n
Star_point_reactor
S_up_A Vc_up_A Page Vc_up_A
do not modify
4k,6500
S_low_A Page S_low_A Vc_low_A Page Vc_low_A
S_up_B Page S_up_B Gate Capa. Vc_up_B Page Vc_up_B
S_low_B Page S_low_B signals Voltages Vc_low_B Page Vc_low_B
+

S_up_C Page S_up_C Vc_up_C Page Vc_up_C

S_low_C Page S_low_C Vc_low_C Page Vc_low_C

i_up_A Page i_up_A

i_low_A Page i_low_A
Current i_up_B Page i_up_B
Arms i_low_B
i_up_C
Page i_low_B
Page i_up_C
Scope :
i_low_C Page i_low_C

V_Secondary_phA
V_Primary_ph va
va V_Secondary_Transfo Page scope
V_Primary_Transfo Page scope
#base_dc_Vrated#
#base_ac_Vrated#
Upper_Level_Ctrl I_Secondary_phA
I_Primary_phA I_Secondary_Transfo Page ia scope
I_Primary_Transfo Page
Upper Level Control ia scope

Page block_MMC
Lower_Level_Ctrl1
#base_dc_Irated#
#base_ac_Irated#
Vdc Page Vdc Vdc_meas Lower Level Control
P_meas Page P_meas Page Vabc_ref Vdc
V_Primary_Transfo Page V_Primary_Transfo Va_ref P_meas
Q_meas Page Q_meas Va_ref
P_meas Page scope
Vdc Page i Vdc in pu o scope
I_Primary_Transfo Page I_Primary_Transfo Vb_ref Vb_ref SM_protection
Vc_ref Q_meas
Vabc_ref Vc_ref
V_Secondary_Transfo Page V_Secondary_Transfo SM Q_meas Page scope Idc

theta theta protection Idc Page i Idc in pu o scope

I_Secondary_Transfo Page I_Secondary_Transfo
order
Vc_up_A Page Vc_up_A S_up_A B1 B2 Page S_up_A I_circular_phA
Vc_low_A Page Vc_low_A S_low_A B3 B4 Page S_low_A scope
Vabc_ref Page
Vc_up_B Page Vc_up_B Capa. Gate S_up_B B5 B6 Page S_up_B Vref_phA
Vc_low_B Page Vc_low_B Voltages signals S_low_B B7 B8 Page S_low_B Va_ref scope i_up_A Page i Iarm in pu o I_circular_phA
1
Vc_up_C Page Vc_up_C S_up_C B9 B10 Page S_up_C Vb_ref f(u) scope
2
Vc_low_C Page Vc_low_C S_low_C B11 B12 Page S_low_C (u[1]+u[2])/2
Start_up_Protect1
Vc_ref i_low_A Page i Iarm in pu o
Start-up sequence i_up_A Page i_up_A
i_low_A Page i_low_A
and Protection system Current
i_up_B Page i_up_B
Idc Page Idc AC_BRK Page AC_BRK i_low_B Page i_low_B Arms Vc_up_A Page
AC_BRK
converter_BRK Page Converter_BRK i_up_C Page i_up_C AC_BRK Page scope Vc1_up_phA
Vc1 1 scope
i_low_C Page i_low_C
block_MMC Page block_MMC
Converter_BRK #base_Vcapa_SM# Vc20_up_phA
scope Vc20 1 scope
Converter_BRK Page
#base_Vcapa_SM#
MMC_control Vc_low_A Page
block_MMC
block_MMC Page scope
Vc1_low_phA
Vc1 1 scope
#base_Vcapa_SM# Vc20_low_phA
Vc20 1 scope
#base_Vcapa_SM#

Control and Protection System

Acquisition system
 20

5. HVDC-MMC model in EMTP-RV

2
Model 1, 2 and 3
MMC model comparisons under AC fault 1

current (pu)
Simulation configuration: 0
MMC-401Level (N = 400SMs/arm)
-1
Time-Step = 10us Model 4
-2
Three-phase to ground fault of 200ms after 1sec of simulation
0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4
time (s)

2 1
Model 1, 2 and 3
Model 1, 2, 3 and 4

voltage (pu)
1 0.5
current (pu)

0.5
0 0 Model 1, 2 and 3
-0.50

current (pu)
-1
Model 4 -1
-0.5 Model 4
-2 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4
0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 -1
time (s) time (s)

MMC-2 phase A current: ia -1.5

0.95 1 1.05
MMC-2 phase A voltage: va
1.1 1.15 1.2 1.25 1.3 1.35 1.4
1
time (s)
Model 1, 2, 3 and 4
voltage (pu)

0.5
0.5 1.15
0 Model 1, 2 and 3
voltage (pu)

0 1.1
current (pu)

-0.5
Model 1 and 2 Model 3
-0.5
-1 Model 4 1.05
Model 4
0.95
-1 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1
time (s)
-1.5 0.95
0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4
time (s) time (s)
1.15 MMC-2 dc current: I dc MMC-2 dc voltage: Vdc
pu)

1.1
 21

5. HVDC-MMC model in EMTP-RV

5
Model 4
MMC model comparison under DC fault

current (pu)
Simulation configuration: 0
MMC-401Level (N = 400SMs/arm)
Time-Step = 10us Model 1, 2 and 3
-5
Permanent Pole-to-pole DC fault at 1.9sec of simulation
1.85 1.9 1.95 2
time (s)

5 10
Model 4
Model 1, 2 and 3

current (pu)
current (pu)

Zoomed
0 5
Model 4

Model 1, 2 and 3
-5 0
1.85 1.9 1.95 2 1.85 1.9 1.95 2
time (s) time (s)
10 MMC-1 ac current: ia MMC-1 dc current: I dc
Model 1, 2 and 3
current (pu)

8
5
Model 1, 2 and 3
Model 4
6
current (pu)

Model 4
4
0
1.85 1.9 1.95 2
2
time (s)
0
1.898 1.9 1.902 1.904 1.906
time (s)

8 Zoomed MMC-1 dc current: I dc

6
pu)
 22

5. HVDC-MMC model in EMTP-RV

Computation performances
401-levels MMC based HVDC link was tested for 1sec simulation.
The simulation time is compared for all models
The best computing performance is given by Model 4

Time step Computation time (s) in function of SMs/arm

Model
(s)
20 50 100 400
#1 10 258 822 2,106 13,459
#2 10 37 65 114 441
#3 10 18 18 18 18
#4 10 15 15 15 15
#4 100 2 2 2 2
 23

6. References
Saad H., Dennetire S., Mahseredjian J., Delaru P., Guillaud X., Peralta J., Nguefeu S., Modular multilevel
converter models for electromagnetic transients, submitted to IEEE Trans. on Power Delivery, TPWRD-
00396-2013

Saad H., Dufour C, Dennetire S., Mahseredjian J., Nguefeu S., Real Time simulation of MMCs using the
State-Space Nodal Approach, accepted in IPST 2013, International Power System Transient Conference

Saad, H.; Peralta, J.; Dennetiere, S.; Mahseredjian, J.; Jatskevich, J. and al, "Dynamic Averaged and
Simplified Models for MMC-Based HVDC Transmission Systems," Power Delivery, IEEE Transactions on ,
vol.PP, no.99, pp.1,10

Peralta J., Saad H., Dennetiere S., Mahseredjian J., Nguefeu S. "Detailed and Averaged Models for a 401-
Level MMCHVDC System," Power Delivery, IEEE Transactions on, vol. 27, no. 3, pp. 1501-1508, July 2012

Peralta J., Saad H., Dennetiere, S., Mahseredjian, J., "Dynamic performance of average-value models for
multi-terminal VSC-HVDC systems," Power and Energy Society General Meeting, 2012 IEEE, pp. 1-8, 22-26
July 2012
 24

Questions?