CMOS Fabrication Process

Raul Samaniego
Escuela de Ingenieria Electronica
y Telecomunicaciones
Universidad Nacional de Chimborazo
Riobamba, Ecuador
Email: rsamaniego.fie@unach.edu.ec

AbstractThe abstract goes here.
1. Introduction
Integrated circuits are fabricated using wafers. Wafers
are like thin circular slices of bread, in this case silicon
bread. On each wafer hundreds or thousands of individual
chips are fabricated. Technically, each of these individual
chips is called die, and each die might represent an IC.
There are several semiconductor industries fabricating ICs.
We call them foundries or fabs. Generally, each foundry
has several IC processes: e.g. 130nm, 90nm, 65nm, etc.
They also organize an annual run schedule (i.e. a fabrication
calendar) for the production in each process.
1.1. CMOS Manufacturing Process
In order to lower the costs associated to production,
MOSIS and EUROPRACTICE assemble small projects to
complete a wafer, therefore dividing the costs. This is called
Multi-Project Wafer. Afterwards, they cut the dies and indi-
vidually isolate the projects submitted for MPW.
It follows now the assembly process. Each die is dis-
posed inside a package cavity. For mass production the
package is generally made of plastic (depending also on
the application). For small production or circuits in which
the temperature can be significantly high, ceramics is often
preferred.
The pads are often defined in the die periphery. The
thin wires made of aluminium or gold (preferable) that are
soldered to the pad are called bondwires. These wired bond
the circuit to the outside. On the other end the bondwires
are soldered to the leadframe, which consists on the metallic
pins that are visible from outside the package.
wafer a epitaxial layer is grown, that is, a thin silicon layer
made of weak or moderate doping levels. This also reduces
the susceptibility of latch-up phenomenon.
SOI wafers are also based on bulk wafers. It are com-
prised of a oxide layer called BOX, and a very thin Si layer.
1.1.2. Wafer preparation. The foundries usually do not
produce the wafers, they buy them. The wafers are fabricated
by specific industries. The base material of the wafer is
silicon with great purity level. One of the most famous
techniques to form silicon ingot is called Czochralskis
method, named after the Polish chemist Jan Czochralski who
used this process in 1916.
The process can be simplified as follows. The silicon
is first melted through heat. A rotative block with a small
silicon crystal is introduced very slowly into the melted
silicon. The temperature is decreased as soon as the seed
touches the silicon surface. Gradually, the silicon attaches
the seed. Very slowly one lifts up the rotative block. The
crystal continues to grow, forming a cylindrical silicon ingot
.
The silicon ingots are then sliced to obtain the circular
wafers. The wafer surface is polished through chemical and
mechanical techniques to obtain a high quality substrate in
which the semiconductor devices will be fabricated. The
pure silicon of the wafer is then doped. That is, small
impurities are added in a controlled way to define the
substrate resistivity. The charge carrier type is also defined
within the doping process. Hence, one can have n-type or
p-type substrates.
When the material is highly doped the resulting resistiv-
ity is very low, thus denominated as p+ or n+ whatever the
doping case is. On the contrary, when the material is lightly
doped the material is referred as p- or n-.

1.1.1. Wafer. The typical silicon wafer is bulk. The diam-
eters vary generally between 50 to 300mm. The thickness
varies with the diameter due to rigidity of the material. The
circuits are built on the top of the wafer. These occupy
about 1m, while the remaining material are in the order
of hundreds m, only used to provide mechanical support.
Epitaxial wafers are obtained by applying strong doping
levels on the typical bulk wafers. On the surface of that
2. Silicon Processes Overview
Bulk CMOS
The most basic bulk process is the n-well process
(also called n-tub). It has a p-type substrate, and an n-well
is needed for PMOS devices. The p-well process is the
opposite, it has a n-type substrate, and the NMOS devices

Figure 1. Bulk process
Figure 2. soi process
require a p-well structure. In the following figures an
NMOS structure is shown in the left side of each process
figure, while in the right side a PMOS is shown.
SOI In the Silicon-on-Insulator process, instead of the
typical silicon substrate, an isolating substrate is used. The
isolating substrate is called buried oxide. On the top of
the BOX a silicon layer is deposited. It is the body of the
transistor and it is where the channel is formed.
Using SOI processes it is possible to build NMOS and
PMOS transistors practically side by side. The transistors are
isolated from each other. Other advantages over the typical
bulk processes include: higher density, latch up phenomena
avoidance, less parasitic capacitances and thus much faster
devices.
However, SOI wafers are pretty expensive essentially
due to the difficulty of silicon deposition on the top of
the BOX. Most popular SOI wafer fabrication methods are
Smart-cut, and SIMOX.
SOS belongs to the family of SOI processes. A silicon
thin-film is epitaxially deposited on the top of a sapphire
wafer. The sapphire is mono-crystalline form: an aluminium
oxide or alumina. The main advantage on using SOS is its
excellent electrical isolation. It is however difficult to align
silicon and sapphire crystalline structures.
It is not easy to produce transistors with reduced
dimensions in SOS technology. The great use of this type
of process can be found in military and space applications,
which are environments typically exposed to great radiation.
Strained Silicon This method consists on the silicon
deposition on the substrate surface with inter atomic spaces
wider than its own crystalline structure. The silicon atoms
stretch themselves in order to get aligned with other atoms.
As a consequence, higher distances between atoms are
achievable and the forces that interfere with charge motion
is reduced. The electron flow is noticeable improved (70
One method to form strained-Si is to include a SiGe
layer, which is very compatible with Si itself.
High-K Processes
During decades the silicon oxide has ruled as dielectric
between gate and substrate. SiO2 was chosen because it
is a native oxide, which is easily formed through thermal
TABLE 1. D IELECTRIC VS K
Dielectric k
SiO2 3.9
HfO2 25
HfSiO4 1518
ZrO2 2025
ZrSiO4 15
Ta2O5 25
growing. Therefore, it consists on an excellent interface
since the atoms are naturally aligned.
With the downscale of transistor dimensions, the oxide
capacity had to be increased to better control the drive, that
is the channel current control that in other words is exactly
the so called field-effect of the MOSFET
That is why the thickness of the gate has been contin-
ually reduced with the downscaling. When thickness below
20 angstrom was achieved . has a reference, Intel 65nm has
about 12 angstrom the leakage currents increased through
oxide tunnels, thus increasing the power consumption and
reducing also the reliability.
This looked like a great bottleneck for downscaling. The
alternative found for short-channel processes was to replace
the native oxide by high-K dielectrics such as hafnium
based the dielectric relative constant is usually denoted
by K. As an example, Intel 45nm processors have high-
K dielectrics, which allow the increase of gate capacitance
avoiding losses. However, a metal gate is needed instead
of a typical silicon structure. This is due to physical issues
related to the interface with the dielectric. Table 1 shows
some dielectric (K) values. For instance, one can compare
SiO2 and the much higher K value for HfO2.
Conclusions
The manufacturing process of integrated circuits re-
quire a large number of steps, each of which consists of
a sequence of basic operations. A number of these steps
and/or operations, such as photolithograpical exposure and
development, material deposition, and etching, are executed
very repetitively in the course of the manufacturing process.
The authors would like to thank...
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