PD - 97128

IRFP3306PbF
HEXFET Power MOSFET
Applications D VDSS 60V
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply RDS(on) typ. 3.3m:
l High Speed Power Switching max. 4.2m:
l Hard Switched and High Frequency Circuits G ID (Silicon Limited) 160A c
Benefits S ID (Package Limited) 120A
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness D
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability S
D
l Lead-Free G

TO-247AC

G D S
Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Silicon Limited) 160c
ID @ TC = 100C Continuous Drain Current, VGS @ 10V (Silicon Limited) 110
A
ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Wire Bond Limited) 120
IDM Pulsed Drain Current d 620
PD @TC = 25C Maximum Power Dissipation 220 W
Linear Derating Factor 1.5 W/C
VGS Gate-to-Source Voltage 20 V
dv/dt Peak Diode Recovery f 14 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range
C
Soldering Temperature, for 10 seconds 300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw 10lbxin (1.1Nxm)

Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy e 184 mJ
IAR Avalanche Currentd See Fig. 14, 15, 22a, 22b, A
EAR Repetitive Avalanche Energy g mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case k 0.67
RCS Case-to-Sink, Flat Greased Surface 0.24 C/W
RJA Junction-to-Ambient jk 40
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IRFP3306PbF
Static @ TJ = 25C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 60 V VGS = 0V, ID = 250A
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient 0.07 V/C Reference to 25C, ID = 5mAd
RDS(on) Static Drain-to-Source On-Resistance 3.3 4.2 m VGS = 10V, ID = 75A g
VGS(th) Gate Threshold Voltage 2.0 4.0 V VDS = VGS, ID = 150A
IDSS Drain-to-Source Leakage Current 20 A VDS = 60V, VGS = 0V
250 VDS = 48V, VGS = 0V, TJ = 125C
IGSS Gate-to-Source Forward Leakage 100 nA VGS = 20V
Gate-to-Source Reverse Leakage -100 VGS = -20V
RG Internal Gate Resistance 0.7
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 230 S VDS = 50V, ID = 75A
Qg Total Gate Charge 85 120 nC ID = 75A
Qgs Gate-to-Source Charge 20 VDS =30V
Qgd Gate-to-Drain ("Miller") Charge 26 VGS = 10V g
Qsync Total Gate Charge Sync. (Qg - Qgd) 59 ID = 75A, VDS =0V, VGS = 10V
td(on) Turn-On Delay Time 15 ns VDD = 30V
tr Rise Time 76 ID = 75A
td(off) Turn-Off Delay Time 40 RG = 2.7
tf Fall Time 77 VGS = 10V g
Ciss Input Capacitance 4520 pF VGS = 0V
Coss Output Capacitance 500 VDS = 50V
Crss Reverse Transfer Capacitance 250 = 1.0MHz, See Fig. 5
Coss eff. (ER) Effective Output Capacitance (Energy Related) 720 VGS = 0V, VDS = 0V to 48V i, See Fig. 11
Coss eff. (TR) Effective Output Capacitance (Time Related)h 880 VGS = 0V, VDS = 0V to 48V h

Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current 160c A MOSFET symbol D

(Body Diode) showing the

ISM Pulsed Source Current 620 A integral reverse G

S
(Body Diode)d p-n junction diode.
VSD Diode Forward Voltage 1.3 V TJ = 25C, IS = 75A, VGS = 0V g
trr Reverse Recovery Time 31 ns TJ = 25C VR = 51V,
35 TJ = 125C IF = 75A
Qrr Reverse Recovery Charge 34 nC TJ = 25C di/dt = 100A/s g
45 TJ = 125C
IRRM Reverse Recovery Current 1.9 A TJ = 25C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25C, L = 0.04mH
RG = 25, IAS = 96A, VGS =10V. Part not recommended for use
above this value .
ISD 75A, di/dt 1400A/s, VDD V(BR)DSS, TJ 175C.
Pulse width 400s; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
R is measured at TJ approximately 90C

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 IRFP3306PbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

8.0V 8.0V
6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
4.8V 4.8V
BOTTOM 4.5V BOTTOM 4.5V

100 100

4.5V
4.5V

60s PULSE WIDTH 60s PULSE WIDTH

Tj = 25C Tj = 175C
10 10
0.1 1 10 100 0.1 1 10 100

VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.5
ID = 75A

RDS(on) , Drain-to-Source On Resistance

VGS = 10V
ID, Drain-to-Source Current()

100 2.0
TJ = 175C
(Normalized)

10 1.5

TJ = 25C

1
1.0
VDS = 25V
60s PULSE WIDTH
0.1
0.5
2.0 3.0 4.0 5.0 6.0 7.0 8.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

8000 20
VGS = 0V, f = 1 MHZ ID= 75A
Ciss = Cgs + Cgd, Cds SHORTED
VDS = 48V
VGS, Gate-to-Source Voltage (V)

Crss = Cgd
16 VDS= 30V
6000 Coss = Cds + Cgd
VDS= 12V
C, Capacitance (pF)

Ciss
12

4000
8

2000
4
Coss
Crss
0
0
0 20 40 60 80 100 120 140
1 10 100
QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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 IRFP3306PbF
1000 10000
OPERATION IN THIS AREA
LIMITED BY R DS (on)

ID, Drain-to-Source Current (A)

ISD , Reverse Drain Current (A)

1000
100
TJ = 175C

1msec 100sec
100
10 TJ = 25C

10msec
10

1
1 Tc = 25C
Tj = 175C DC
VGS = 0V Single Pulse
0.1 0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.1 1 10 100
VSD , Source-to-Drain Voltage (V) VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area
Forward Voltage
180

V(BR)DSS , Drain-to-Source Breakdown Voltage

80
ID = 5mA
160
Limited By Package
140
ID, Drain Current (A)

120 70

100

80

60 60

40

20

0 50
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

T C , Case Temperature (C) TJ , Junction Temperature (C)

Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
1.5 800
EAS, Single Pulse Avalanche Energy (mJ)

ID
TOP 13A
18A
600 BOTTOM 96A
1.0
Energy (J)

400

0.5

200

0.0 0
0 10 20 30 40 50 60 25 50 75 100 125 150 175
VDS, Drain-to-Source Voltage (V) Starting TJ, Junction Temperature (C)

Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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 IRFP3306PbF
1

D = 0.50

0.20
Thermal Response ( Z thJC )
0.1
0.10
0.05
0.02
0.01 R1 R2
0.01
J
R1 R2
Ri (C/W) (sec)
C
J
1
1
2 0.249761 0.00028
2

Ci= i/Ri 0.400239 0.005548

0.001 SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100
Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150C and
0.01 Tstart =25C (Single Pulse)
Avalanche Current (A)

0.05
10 0.10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming j = 25C and
Tstart = 150C.

1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
200 Notes on Repetitive Avalanche Curves , Figures 14, 15:
TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 1% Duty Cycle 1. Avalanche failures assumption:
ID = 96A Purely a thermal phenomenon and failure occurs at a temperature far in
EAR , Avalanche Energy (mJ)

160
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
120
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
80 6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25C in Figure 14, 15).
40 tav = Average time in avalanche.
D = Duty cycle in avalanche = tav f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
25 50 75 100 125 150 175 PD (ave) = 1/2 ( 1.3BVIav) = DT/ ZthJC
Iav = 2DT/ [1.3BVZth]
Starting TJ , Junction Temperature (C)
EAS (AR) = PD (ave)tav

Fig 15. Maximum Avalanche Energy vs. Temperature

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IRFP3306PbF
4.5 16

ID = 1.0A
VGS(th) Gate threshold Voltage (V)

4.0 ID = 1.0mA
ID = 250A 12
3.5
ID = 150A

IRRM - (A)
3.0
8
2.5

2.0 IF = 30A
4
VR = 51V
1.5 TJ = 125C
TJ = 25C
1.0 0
-75 -50 -25 0 25 50 75 100 125 150 175 100 200 300 400 500 600 700 800 900 1000

TJ , Temperature ( C ) dif / dt - (A / s)

Fig 16. Threshold Voltage Vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

16 350

300

12
250
QRR - (nC)
IRRM - (A)

200
8
150

IF = 45A 100 IF = 30A

4
VR = 51V VR = 51V
TJ = 125C 50 TJ = 125C
TJ = 25C TJ = 25C
0 0
100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / s) dif / dt - (A / s)

Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt

350

300

250
QRR - (nC)

200

150

100 IF = 45A
VR = 51V
50 TJ = 125C
TJ = 25C
0
100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / s)

Fig. 20 - Typical Stored Charge vs. dif/dt

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 IRFP3306PbF
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+

VGS=10V *
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
- Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
Recovery Body Diode Forward
-
+ Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD

RG dv/dt controlled by RG VDD Re-Applied

Driver same type as D.U.T. + Voltage Body Diode Forward Drop
ISD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
D.U.T. - Device Under Test

Ripple 5% ISD

* VGS = 5V for Logic Level Devices

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01
I AS

Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms

LD
VDS VDS
90%
+
VDD -

D.U.T 10%
VGS VGS
Pulse Width < 1s
Duty Factor < 0.1% td(on) tr td(off) tf

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Current Regulator Id
Same Type as D.U.T. Vds

Vgs
50K

12V .2F
.3F

+
V
D.U.T. - DS
Vgs(th)
VGS

3mA

IG ID
Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRFP3306PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)

TO-247AC Part Marking Information

EXAMPLE: THIS IS AN IRFPE30
WIT H AS S EMBLY PART NUMBER
LOT CODE 5657 INTERNATIONAL
AS S EMBLED ON WW 35, 2001 RECT IFIER IRFPE30

IN T HE AS S EMBLY LINE "H" LOGO 135H

56 57
DAT E CODE
AS S EMBLY YEAR 1 = 2001
Note: "P" in ass embly line pos ition
indicates "Lead-Free" LOT CODE WEEK 35
LINE H

TO-247AC packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IRs Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 03/08
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