Goal of this chapter

Present intuitive understanding of device operation

Introduction of basic device equations
The Devices: Introduction of models for manual analysis

Diode Introduction of models for SPICE simulation

Analysis of secondary deep-sub -micron effects
Future trends

[Adapted from Rabaeys Digital Integrated Circuits , 2002, J. Rabaey et al.]

EE415 VLSI Design EE415 VLSI Design

Outline Semiconductor Basics I

l Motivation and Goals
l Semiconductor Basics l Electrons in intrinsic (pure) Silicon
l Diode Structure covalently bonded to atoms
l Operation juggled between neighbors
Static model thermally activated: density eT
Depletion capacitance move around the lattice, if free
Carrier density profiles
l Diffusion capacitance
leave a positively charged `hole behind

Dynamic response
Switching speed next session

l Spice model
EE415 VLSI Design EE415 VLSI Design

Semiconductor Basics II The Diode

l Two types of intrinsic carriers
Electrons (ni) and holes (pi)
B Al A
In an intrinsic (no doping) material, ni=pi SiO 2

At 300K, ni=pi is low (1010cm-3)

p
Use doping to improve conductivity
n
l Extrinsic carriers
Also two types of dopants (donors or acceptors) Cross section of pn-junction in an IC process
Donors bring electron (n-type) and become ive ions
Acceptors bring holes (p-type) and become +ive ions N-type region P-type region
Substantially higher densities ( 1015cm-3) doped with donor doped with
Majority and minority carriers impurities acceptor
if n>>p (n-type) electrons majority and holes minority (phosphorus, impurities (boron)
Random recombination and thermal generation arsenic)
EE415 VLSI Design EE415 VLSI Design

1
 The Diode Depletion Region
Concentration Gradient causes electrons to diffuse from n to p,
Simplified structure and holes to diffuse from p to n
This produces immobile ions in the vicinity of the boundary
A Al Region at the junction with the charged ions is called the
p A depletion region or space-charge region
n Charges create electric field that attracts the minority carriers,
B causing them to drift
The pn B
One-dimensional
region is representation diode symbol Drift counteracts diffusion causing equilibrium ( Idrift = -Idiffusion )
assumed to hole diffusion
be thin (step Different concentrations of electron diffusion

or abrupt electrons (and holes) of the p and n- p n

junction) type regions cause a concentration hole drift
gradient at the boundary electron drift

EE415 VLSI Design EE415 VLSI Design

Depletion Region Built-in Potential

hole diffusion

Zero bias conditions

electron diffusion
N N
p n
(a) Current flow. 0 = T ln A 2 D
p more heavily doped ni
hole drift
than n (NA > NB) electron drift
Where T is the thermal voltage
Charge
Electric field gives rise Density
+ x (b) Charge density.
to potential difference in -
Distance
kT
the junction, known as T = = 26mV (at 300 K )
the built-in potential Electrical
q
Field
x
n i is the intrinsic carrier concentration for
(c) Electric field.

1 1
pure Si (1.5 X 1010 cm-3 at 300K), so for N A = 101 5 3 , N B = 101 6 3 ,
Potential
V cm cm
0 x
(d) Electrostatic
potential. 10151016
0 = 26 ln mV = 638mV
( )
-W 1 W2
10 2
1. 5 *10
EE415 VLSI Design EE415 VLSI Design

Forward Bias Forward Bias

Metal contact to p-region

Metal contact to n-region

hole diffusion
electron diffusion
pn (W )
2

p n pn (x)

hole drift
electron drift
p n0
p p(x) Lp

+ -
n p0

Applied potential lowers the potential barrier -Wp -W 1 0 W2 Wn x

Idiffusion > I drift

p-region n-region

Mobile carriers drift through the dep. region into neutral regions diffusion

become excess minority carriers and diffuse towards terminals

Typically avoided in Digital ICs
EE415 VLSI Design EE415 VLSI Design

2
 Reverse Bias Reverse Bias

Metal contact to p-region

Metal contact to n-region

hole diffusion
electron diffusion

p n
pn0
hole drift
electron drift

- + n p0

Applied potential increases the potential barrier -Wp -W 1 0 W2 Wn x

Diffusion current is reduced p-region n-region

Diode works in the reverse bias with a very small drift current diffusion

The Dominant Operation Mode

EE415 VLSI Design EE415 VLSI Design

Models for Manual Analysis Typical Diode Parameters

Geometry, doping and material
constants lumped in Is
Diffusion coefficient
ID = IS (eV D/T 1) ID minority carrier concentration
+ + +
+
VD VD VDon VD
ID = IS (eV D / T 1)

Dn=25 cm2 /sec
IS = qAD (WnpWn02 + W np pW01 )
D p Dn

Dp=10cm2 /sec
(a) Ideal diode model (b) First-order diode model typical value
Conducting diode replaced Wn=5 m
Accurate IS = 10 1 7 A / m 2
by voltage source VDon=0.7V Wp=0.7 m
Strongly non-linear
Good for first order W2 =0.15 m
Prevents fast DC bias approximation
calculations W1 =0.03 m
EE415 VLSI Design EE415 VLSI Design

Diode Current Depletion Capacitance

VDon 0.7V
V D o n 0. 7V

l Due to depletion charges

VD changes space charge
Ideal diode equation: Forms a capacitor Cj
Charge modulated by voltage
l Ideality factor (m) depends on
junction gradient
EE415 VLSI Design EE415 VLSI Design

3
 Equivalent Capacitances I Equivalent Capacitances II
l Linearize diode capacitances Equivalent diffusion capacitance
Cj is a non-linear function of VD Must be worked out for currents at given V1V2 transition
When bias changes then Cj also changes
Qj I (V ) I D (V1 ) C (V ) Cd (V1)
Hard to use in manual analyses Ceq = = T D 2 = T d 2
Instead use equivalent capacitance VD V2 V1 V2 V1
Gives the same total charge for a given VD transition
Equivalent depletion capacitance l Ceq depends on process constants and {V 1,V 2}
Must be worked out for a given V1 V2 transition
Example:
Q j Q j (V2 ) Q j (V1 ) for AD =0.5 m2 Cj0=2 fF/m2, 0=0.64 V and m=0.5
C eq = = = Keq C j 0
VD V2 V1 l then at -2.5V, Cj 0.9 fF/m 2 or Cj 0.45 fF for the total diode area

[(0 V2 ) (0 V1 ) ]
l or Keq 0.622 and Ceq 1.24 fF/m2 if switched between 0 and - 2.5 V
m 1 m 1m
K eq = 0

(V2 V1 )(1 m)
EE415 VLSI Design EE415 VLSI Design

Secondary Effects: Breakdown Diode SPICE Model

l Cannot bear too large reverse biases l Required for circuit simulations
Drift field in depletion region will get extremely large Must capture important characteristics but also remain efficient
Minority carriers caught in this large field will get very energetic Extra parameter in the model: n (emission coefficient, 1 n< 2)
Energetic carriers can knock atoms and create a new n-p pair Fixes non-ideal behavior due to broken assumptions
These carriers will get energetic, too, and so on: thus large currents!
l Additional series resistance accounts for body+contact
0.1
l Two types l Nonlinear capacitance includes both CD and C j
Avalanche breakdown
Above mechanism I D = I S (eVD / nT 1)
Zener breakdown RS
I D (A)

0 More complicated
l Can damage diode +

VD ID CD
0.1 -
25.0 15.0 5.0 0 5.0
EE415 VLSI Design EE415 VLSI Design
VD (V)

SPICE Parameters
l Often supplied by the fab to the designer
If not must be measured and fit the parameters
l Assumes default values, if not explicitly defined
l Pay attention to the units and spelling

EE415 VLSI Design