LITERATURE SURVEY OF ADDER AND MULTIPLIER ARCHITECTURES

An Efficient and Enhanced Memory Based FFT Processor Using Radix 16 Booth with Carry
Skip Adder:

Abstract:
The main objective of this concept is to design a memory efficient FFT processor with low power
consumption. Enhanced memory addressing scheme is proposed to deal with these complex and
higher radix FFT processors. Dual port merged bank memory is designed in-order to deal with
memory based FFT processors. Each and every butterfly unit needs one memory to store those
computational permutations. So, if radix of FFT increases, memory requirement increases. Implies,
more density occupancy, more power consumption is yielded. Here in this concept, area efficient
algorithm (Algorithm AE) with single- port, merged-bank (SPMB) memory Algorithm with Low
Power (LP) using cached memory (CM) are proposed to deal with memory based FFT processor
problems. The butterfly unit in this concept is implemented with multiplier and adder modules.
An efficient and enhanced algorithm like Radix-16 modified booth and carry skip adders are used in
this process.

RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder

Abstract:
In this paper, we propose a fast yet energy-efficient reconfigurable approximate carry look-ahead
adder (RAP-CLA). This adder has the ability of switching between the approximate and exact
operating modes making it suitable for both error- resilient and exact applications. The structure,
which is more area and power efficient than state-of-the-art reconfigurable approximate adders, is
achieved by some modifications to the conventional carry look ahead adder (CLA). The efficacy of
the proposed RAP-CLA adder is evaluated by comparing its characteristics to those of two state-of-
the-art reconfigurable approximate adders as well as the conventional (exact) CLA in a 15nm
FinFET technology. The results reveal that, in the approximate operating mode, the proposed 32-bit
adder provides up to 55% and 28% delay and power reductions compared to those of the exact
CLA, respectively, at the cost of up to 35.16% error rate. It also provides up to 49% and 19% lower
delay and power consumption, respectively, compared to other approximate adders considered in
this work. Finally, the effectiveness of the proposed adder on two image processing applications of
smoothing and sharpening is demonstrated. The study shows that, on average, PSNR reductions of
12% and 16%, respectively, may be achieved by employing the proposed adder.

Design and Implementation of a Power and Speed Efficient Carry Select Adder on FPGA

Abstract:
Adders are one of the most common unit in digital systems. The speed, power and area occupied by
an adder play a vital role in Digital Signal Processing system, Image Processing system, etc. Hence,
they play an important role in deciding the time period of the clock, the place and route of various
units comprising of the system and total power consumed by the system. In this paper, we propose a
new architecture for a modified sequential high speed carry select adder. We have given emphasis
on optimizing the time period of the clock and power consumed, by using the carry ahead
generation technique of Carry Look Ahead Adder (CLAA) and multiplexing technique of Carry
Select Adder (CSA). The proposed CSA was implemented on Virtex-7 and results were calculated
using Vivado Design Suite 2014.4..
Implementation of Efficient Portable Low Delay Adder Using FPGA

Abstract:
No doubt that in this technological era the arithmetic circuit is the core of most all the Digital Signal
Processing applications (DSP), especially adder circuits. In this paper, various types of adder
circuits have been implemented on Field Programmable Gate Array (FPGA). Furthermore, another
architecture for adder called Carry Shifting Adder (CSHA) is proposed. This depends on shifting
the carry to the next stage. Then its combined with a carry increment circuit to get a low delay. The
goal of this paper is to efficiently carry out the proposed CSHA adder with carry increment circuit
over FPGA kit. Simulations are done to find out the circuit area and delay. Also, this is compared
with the related other adder circuits. The performance of this proposed adder circuit is better than
other related ones in both area and delay.

Multi-operand logarithmic addition/subtraction based on Fractional Normalization

Abstract:
This paper presents a method for adding several numbers represented in the Logarithmic Number
System (LNS). The proposed technique is based on the normalization towards the largest input
number. The distinct steps of the original two-input addition/subtraction using Fractional
Normalization method (FN) [1] are modified in order to achieve performance and reduce hardware
requirements. Three multi-operand adders are analyzed and compared: The first architecture uses
the original FN method, the second one uses an introduced two- step modified FN (MFN) method,
and the third architecture uses full MFN method. The proposed multi-operand adders are
synthesized and evaluated for complexity and performance using a 65-nm 0.9V UMC CMOS
library, for the cases of 4, 8, 16 inputs and an 11-bit word length.

An efficient power multiple valued look up table for adder circuit using quaternary FPGA

Abstract:
VLSI technology is used for designing, verifying, fabricating and testing a chip. In look up table
(LUT) system, the more interconnections are increasingly the dominant contributor to delay, area,
and energy consumption in CMOS digital circuits. In existing system would require four QLUTs to
properly implement this function, two QLUTs for each output, that is sum and carry out, working
with the two possible values of the carry in. This method will have signal propagation delay and
hence its decrease the speed of the circuit and more power is consumed. In order to overcome this
problem multiple-valued logic is used, it can decrease the average power required for level
transitions and reduces the number of required interconnections and also reducing the impact of
interconnections on overall energy consumption. In proposed scheme, a quaternary look up table
structure is designed to replace or complement binary LUT in FPGA. The proposed design include
full adder is constructed using 16:1 multiplexer which overcome the limitations of existing method.
The design will be synthesized using Modelsim 6.0 and Xilinx 14.2.
SWL Algorithms Optimization Using Alternative Adder Module in FPGA

Abstract:
Recently single-bit ternary FIR-like filter (SBTFF) hardware synthesize in FPGA is reported and
compared with multi-bit FIR filter on similar spectral characteristics. Results shows that SBTFF
dominates upon multi-bit filter overall. In this work, we have adopted ternary sigma-delta
modulated arithmetic adder (i.e., improved ternary adder (ITA)) and simulated it in ModelSim for
functional verification. Further, it is synthesized in Xilinx for chip cost and its maximum
performance measured in (F MAX ) compared to conventional adder module used in SBTFF. The
synthesize results show that ITA performs excellent while inputs are higher than 64 with lower chip
areas, whereas its performance is poor at lower inputs compared to conventional adder. These
results enhance the usefulness of existing short word length DSP algorithms for fast and efficient
mobile communication.

Fast Energy Efficient Radix-16 Sequential Multiplier

Abstract:
We propose a new sequential multiplier design that generates the radix-16 partial products (e.g., P)
as two high (H) and low (L) components, such that P = 4H + L, H, L {0, 1, 2, 3} X, where X
denotes the multiplicand. The required hard 3X multiple is generated in a preliminary cycle to the
advantage of reducing the cycle time of the main iteration. Two radix-16 carry-save adders are used
to generate the radix-16 accumulated partial product. The synthesis results show improved latency,
power dissipation, and energy consumption over the previous relevant designs at the cost of
additional silicon area, while however, the energy-area product is also lowered.

Implementation of a High Speed Multiplier desired for High-Performance Applications Using

Kogge Stone Adder

Abstract:
The performance of multiplication in terms of speed and power is crucial for most of the Digital
Signal Processing (DSP) applications. Many researchers have come up with various multipliers
such as array, Booth, carry save, Wallace tree and modified Booth multipliers. However, for the
present day applications Vedic multipliers based on Vedic Mathematics are presently under focus
due to their high speed and low power consumption. In this paper, we propose a design of 8 bit
multipliers using fast adders (carry save adder, kogge- stone adder and carry-select adder) to
minimize the power delay product of multipliers intended for high- performance applications.
Implementation results demonstrate that the proposed Vedic multipliers with fast adders really
achieve significant improvement in delay and power-delay product when compared with the
conventional multipliers.
MAC Unit for Reconfigurable Systems Using Multi-Operand Adders with Double Carry-Save
Encoding

Abstract:
In this work, carry-free redundant arithmetic based fused multiply-accumulate (MAC) units are
designed. In the first design, a regular redundant carry-save MAC unit is designed using well
known carry-save techniques. In the second design, a hybrid design is proposed to exploit fast carry
chains of the FPGA together with double carry-save output encoding. The proposed scheme exploits
fast-carry chains of the FPGA structure, and, multi-operand adders are divided into smaller blocks
to increase the performance. The outputs of the multi-operand adders are not merged and the results
are kept in double carry-save format where extra redundancy reduces critical path delay. Designed
MAC units have 16x16- bit multiplier with 40-digit accumulate output for recursive multiply-add
operations. The designs are synthesized on Altera TM Stratix III FPGAs and provide superior
performance compared to conventional pipelined carry-propagate multiply- accumulate units. The
fusion in the arithmetic structure provides best performance compared to conventional pipelined
multiplier based structures, hard multiplier based MAC units, and carry free redundant arithmetic
based MAC structures as well..

An Efficient Constant Multiplier Architecure Based on Vertical-Horizontal Binary Common

Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.
Abstract:
This paper proposes an efficient constant multiplier architecture based on vertical-horizontal binary
common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse
response (FIR) filter whose coefficients can dynamically change in real time. To design an efficient
reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2-bit binary common sub-
expression elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on the
2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm
horizontally within each coefficient. This technique is capable of reducing the average probability of use
or the switching activity of the multiplier block adders by 6.2% and 19.6% as compared to that of two
existing 2-bit and 3-bit BCSE algorithms respectively. ASIC implementation results of FIR filters using
this multiplier show that the proposed VHBCSE algorithm is also successful in reducing the average
power consumption by 32% and 52% along with an improvement in the area power product (APP) by
25% and 66% compared to those of the 2-bit and 3-bit BCSE algorithms respectively. As regards the
implementation of FIR filter, improvements of 13% and 28% in area delay product (ADP) and 76.1%
and 77.8% in power delay product (PDP) for the proposed VHBCSE algorithm have been achieved over
those of the earlier multiple constant multiplication (MCM) algorithms, viz. faithfully rounded truncated
multiple constant multiplication/accumulation (MCMAT) and multi-root binary partition graph (MBPG)
respectively. Efficiency shown by the results of comparing the FPGA and ASIC implementations of the
reconfigurable FIR filter designed using VHBCSE algorithm based constant multiplier establishes the
suitability of the proposed algorithm for efficient fixed point reconfigurable FIR filter synthesis
Design of fast FIR filter using compressor and Carry Select Adder
Abstract:
Speed and area are now a day's one of the fundamental design issues in digital era. To increase speed,
while doing the multiplication or addition operations, has always been a basic requirement of designing
of advanced system and application. Carry Select Adder (CSA) is a fastest adder used in many
processors to accomplish fast arithmetic function. Many different adder architecture designs have been
developed to increase the efficiency of the adder. It is very commonly known that per second any
processors performed millions of work functions in semiconductor industry. So when we do designing
of multipliers, one of the main standards is performing speed that should be taken in the mind. In this
paper, we propose a technique for designing of FIR filter using multiplier based on compressor and
carry select adder. Performance of all adder designs is implemented for 16, 32 and 64 bit circuits. These
structures are synthesized on Xilinx device family.