Steps in designing a system:

1. Define requirements
2. Define components
3. Complete design details
4. Build and test prototypes
5. Finalize design and begin production

Designer should understand operation of each component.

Control of system is responsibility of the processor. It puts addresses

to program memory, controls the sequence of operations performed, by
interpreting and executing instructions, it controls the actual
operations.

Processor reads first instruction in program, performs the task dictated

by bits in this instruction (execution).

Bit is a binary value (0 or 1).

Address Space
Address space is the total set of addresses which the
microprocessor can generate.

Internal organization of an n bit processor is around n bit

registers, n bit parallel data paths, etc. Most arithmetic operations
take place on 8 bits of data at a time.

The 16 bit counter determines which instruction is being executed

is also divided into two 8 bit busses. One contains bits 0-7 (low address
bits - ADL), the other contains bits 8-15 (high order address bits -
ADH).

The ADH indicates in which page the address is located, the ADL
indicates a specific address on that page.

The first page in memory ADH=0 is reffered to as page zero.

System Components
Clock Generator
Produces continuous waveform which is used to controll all
signal transitions. It acts as a "heart" of the system.
Address bus will change during one half of cycle,
Data will be transferred during second half.
The processor must also examine the clock to know when to put
out data or when to latch in data generated by another device.

Program Memory
Program memory stores sequence of instructions which
comprises the system program. This unit puts a pattern of 1's and 0's on
the data bus in response to the address on the address bus input.

Each unique address selects a set of 8 bits and places this

data on the data bus.
Given an address, it puts out corresponding 8 bits of data on
the data bus.
 Microprocessors usually have programs in Read Only memories
(ROM). Data is not lost when power is disconnected from chip. Read Only
means that in system operation, processor cannot cause data to be stored
on the device.

Data Memory
Temporary storage of input data, results of operations are
stored on RAM (Random Access Memory).

Each address corresponds to eight memory cells.

RAM data must be placed into memory by the processor.

Writing data into RAM takes place when Write-Enable signal

goes to WRITE state.
At that time, data on data bus will be stored into memory
cells corresponding to address on the address bus. Processor can READ
data by supplying roper address and keeping Write-Enable line in the Read
state.

Input/Output Devices
Input/Output Devices are circuits which interface the
printer, keyboard, displays, etc.

Transfer of data from processor to IO is accomplished by

writing data in same way as writing into RAM.

Microprocessor
Direct control over rest of system by the processor is
enabled through:
-address bus
-bi-directional data bus
-Write-Enable line

Address bus puts out addresses to control the source or

destination of data transfers.
During fetch of instructions from program memory, the
addresses are derived from a counter which controls execution of
sequential instructions.

Bi-directional data bus serves as path for transferring data

into and out of the processors.
Direction of data is determined by Write-Enable line.

Interrupt allows peripheral devices to affect processor

operation. When interrupt is generated, the processor completes the
instruction and then responds to interrupt.
It allows the processor to execute the system program
without the latter monitoring the status of peripheral devices.

System Concepts
Bus Structure
Two primary busses.

Address bus is used to transfer address generated by the

processor to the address inputs of the memory and peripheral interface
devices. The only source of addresses is usually the processor. It
consists of 16 lines.
 Data bus is an 8 bit data path. It transfers data from
processor to memory during WRITE operation and from memory to processor
during READ.

Direction of data is controlled by READ/WRITE line on

processor. This lines performs the Write-Enable function. If R/W line is
high (>2.4V DC), all data transfers will go from memory to processor.

Timing of data transfers is controlled by system clock. It

actually has two non-overlapping alternating square waves.

Processor Interrupts
Peripheral devices can request service from processor.

In 6502, interrupts are enabled, disabled and latched until

interrupt is processed. The peripheral interface device generates signals
which meet the requirements of the processor interrupt inputs.

There are two interrupt lines to the microprocessor, IRQ

(Interrupt Request) and NMI (Non-Maskable Interrupt).

Interrupt applications
Keyboard
Keyboard strobe line (key pressed signal) is connected
to interrupt input on a peripheral interface device. Each time a strobe
signal occurs, an interrupt occurs, processor reads data on peripheral
port into memory, analyses data, and then returns to the program that was
in process. If no keys are pressed, processor spends no time in servicing
the keyboard.

Display
Display is usually scanned such that each digit is
driven for a short period of time in sequence. Display requires attention
from processor at fixed intervals. Because it is difficult for the
processor to calculate repetitive time intervals while performing normal
system routines, it prefers to run the system program without
consideratio for display time intervals, only executing the display
software when required. A solution is the generation of processor
interrupts using an external counter or clock. Each time an interrupt
occurs, the data for next digit in display is placed on output port. The
processor then returns to program it had been executing.

Interrupt prioritising
If more than one interrupt source requires attention at one
time, a priority level must be established.

Two ways. Hardware methods involve using a priority encoder,

which allows processor to go to software wich services the highest
priority interrupt first, then next etc.

A less expensive way is "polled" interrupt.

When active interrupt source is detected, processor executes

a "polled" interrupt program that interrogates the highest priority
interrupt, and then the next until active interrupt is located. The
program services that interrupt and returns to the "polled" program until
all have been interrogated or clears the interrupt disable to allow
nested interrupts.

Interrupt request
The two interrupt lines for microprocessor are IRQ and NMI.

IRQ requirements are more precise than NMI.

With IRQ, processor will be interrupted any time the signal

on IRQ is < 0.4V and the Interrupt Disable flag (I) is cleared. I flag is
a bit in the P register.

I flag is important in IRQ interpretation. Positive or

negative transition from peripheral device is detected on inputs to
peripheral interface device.

If interrupt is enabled within the interface device, the IRQ

will go low. The condition is latched within peripheral interface device
to allow sufficient time for processor to poll the interrupt sources,
assuring that interrupt signal will not be cleared before the polling can
b completed.

I flag is set when processor recognizes interrupt. So the

nterrupt is not recognized again. Resetting I can be performed manually
or automatically with "Return from Interrupt" instruction. I can not be
cleared before interrupt is reset.

Performing the "Clear I" can cause the program to recognise

the interrupt again.

Non-Maskable Interrupt
NMI input to processor is edge sensitive. There must be a
negative transition of signal of the NMI input. This will cause a single
interrupt to occur. The processor will ignore this input until NMI signal
hoes high and then back to ground.

Response to an NMI interrupt signal cannot be disabled within

the processor.

Processing multiple interrupts in polled interrupt structure

requires all interrupts be polled before executing "Return from
Interrupt" instruction. If one of the interrupts is left unserviced, it
will hold the NMI signal to ground, disabling all other interrupts. That
doesn't happen with IRQ.

System reset
Reset pins on all peripheral devices are to be held low
during power on until the supply voltages and clocks are stabilised.

After power on, the contents of latches, registers, etc. is

random after power is applied. The only way to force lines to a known
condition is to apply the reset signal.

In the processor, the single register which must be placed in

a known state is the program counter. This is the register which selects
the instructions to be executed. The RESET input causes the program
counter to go to the first instruction in the system program.