Internal Use Only

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Asia/Oceania http://biz.lgservice.com

LCD TV
SERVICE MANUAL
CHASSIS : LD01I

MODEL : 47LD920 47LD920-ZA

MODEL : 47LD950 47LD950-ZA
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

P/NO : MFL62863041 (1005-REV01) Printed in Korea

 CONTENTS

CONTENTS .............................................................................................. 2

PRODUCT SAFETY ................................................................................. 3

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 10

BLOCK DIAGRAM...................................................................................16

EXPLODED VIEW .................................................................................. 18

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

Copyright 2010 LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
 SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance Leakage Current Hot Check (See below Figure)

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10mm away from PCB.
Keep wires away from high voltage or high temperature parts.
Plug the AC cord directly into the AC outlet.
Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
Leakage Current Hot Check circuit

Before returning the receiver to the customer, AC Volt-meter

always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical Good Earth Ground
shock. such as WATER PIPE,
To Instruments CONDUIT etc.
0.15 uF
Leakage Current Cold Check(Antenna Cold Check) exposed
With the instrument AC plug removed from AC source, connect an METALLIC PARTS
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC 1.5 Kohm/10W
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc. When 25A is impressed between Earth and 2nd Ground
If the exposed metallic part has a return path to the chassis, the for 1 second, Resistance must be less than 0.1
measured resistance should be between 1 M and 5.2 M.
*Base on Adjustment standard
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Copyright 2010 LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only
Only for training and service purposes
 SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the
SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conflict between the
following servicing precautions and any of the safety precautions on
page 3 of this publication, always follow the safety precautions.
Remember: Safety First.
General Servicing Precautions
1. Always unplug the receiver AC power cord from the AC power
source before;
a. Removing or reinstalling any component, circuit board
module or any other receiver assembly.
b. Disconnecting or reconnecting any receiver electrical plug or
other electrical connection.
c. Connecting a test substitute in parallel with an electrolytic
capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an
explosion hazard.
2. Test high voltage only by measuring it with an appropriate high
voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".
3. Do not spray chemicals on or near this receiver or any of its
assemblies.
4. Unless specified otherwise in this service manual, clean
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10 % (by volume) Acetone and 90 %
(by volume) isopropyl alcohol (90 % - 99 % strength)
CAUTION: This is a flammable mixture.
Unless specified otherwise in this service manual, lubrication of
contacts in not required.
5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.
6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks are
correctly installed.
7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.
8. Use with this receiver only the test fixtures specified in this
service manual.
CAUTION: Do not connect the test fixture ground strap to any
heat sink in this receiver.
Electrostatically Sensitive (ES) Devices
Some semiconductor (solid-state) devices can be damaged easily
by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES
devices are integrated circuits and some field-effect transistors and
semiconductor "chip" components. The following techniques
should be used to help reduce the incidence of component
damage caused by static by static electricity.
1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground.
Alternatively, obtain and wear a commercially available
discharging wrist strap device, which should be removed to
prevent potential shock reasons prior to applying power to the
unit under test.
Copyright 2010 LG Electronics. Inc. All rights reserved. -4-
Only for training and service purposes
2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or
exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES
devices.
4. Use only an anti-static type solder removal device. Some solder
removal devices not classified as "anti-static" can generate
electrical charges sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate
electrical charges sufficient to damage ES devices.
6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads
electrically shorted together by conductive foam, aluminum foil
or comparable conductive material).
7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective material
to the chassis or circuit assembly into which the device will be
installed.
CAUTION: Be sure no power is applied to the chassis or circuit,
and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged
replacement ES devices. (Otherwise harmless motion such as
the brushing together of your clothes fabric or the lifting of your
foot from a carpeted floor can generate static electricity
sufficient to damage an ES device.)
General Soldering Guidelines
1. Use a grounded-tip, low-wattage soldering iron and appropriate
tip size and shape that will maintain tip temperature within the
range or 500 F to 600 F.
2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.
3. Keep the soldering iron tip clean and well tinned.
4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.
5. Use the following unsoldering technique
a. Allow the soldering iron tip to reach normal temperature.
(500 F to 600 F)
b. Heat the component lead until the solder melts.
c. Quickly draw the melted solder with an anti-static, suction-
type solder removal device or with solder braid.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
(500 F to 600 F)
b. First, hold the soldering iron tip and solder the strand against
the component lead until the solder melts.
c. Quickly move the soldering iron tip to the junction of the
component lead and the printed circuit foil, and hold it there
only until the solder flows onto and around both the
component lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
d. Closely inspect the solder area and remove any excess or
splashed solder with a small wire-bristle brush.
LGE Internal Use Only
IC Remove/Replacement
Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent flat against the
circuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.
Removal
1. Desolder and straighten each IC lead in one operation by gently
prying up on the lead with the soldering iron tip as the solder
melts.
2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing the
IC.
Replacement
1. Carefully insert the replacement IC in the circuit board.
2. Carefully bend each IC lead against the circuit foil pad and
solder it.
3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).
"Small-Signal" Discrete Transistor
Removal/Replacement
1. Remove the defective transistor by clipping its leads as close as
possible to the component body.
2. Bend into a "U" shape the end of each of three leads remaining
on the circuit board.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.
Power Output, Transistor Device
Removal/Replacement
1. Heat and remove all solder from around the transistor leads.
2. Remove the heat sink mounting screw (if so equipped).
3. Carefully remove the transistor from the heat sink of the circuit
board.
4. Insert new transistor in the circuit board.
5. Solder each transistor lead, and clip off excess lead.
6. Replace heat sink.
Circuit Board Foil Repair
Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed whenever
this condition is encountered.
At IC Connections
To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC
connections).
1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).
2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.
4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the good
copper pattern. Solder the overlapped area and clip off any
excess jumper wire.
At Other Connections
Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.
1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.
2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly
connected to the affected copper pattern.
3. Connect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.

Diode Removal/Replacement
1. Remove defective diode by clipping its leads as close as
possible to diode body.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.

Fuse and Conventional Resistor

Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.

Copyright 2010 LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only
Only for training and service purposes
 SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.

1. Application range 3. Test method

This specification is applied to the LCD TV used LD01I 1) Performance: LGE TV test method followed
chassis. 2) Demanded other specification
- Safety: CE, IEC specification
2. Requirement for Test - EMC:CE, IEC
Each part is tested as below without special appointment.

1) Temperature
: 25 C 5 C (77 F 9 F), CST : 40 C 5 C
2) Relative Humidity : 65 % 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~ 50 / 60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.

4. Module General Specification

No. Item Specification Remark

1 Display Screen Device 119 cm(47 inch) Wide color display module CCFL LCD

2 Aspect Ratio 16:9

3 LCD Module 119 cm(47 inch) TFT LCD FHD (100 Hz)

4 Storage Environment Temp. : -20 deg ~ 60 deg

Humidity : 10 % ~ 90 %

5 Input Voltage AC 100-240 V~ 50 / 60 Hz

6 Power Consumption Power on (Blue)

Total 220 W(Typ.) [Logic = 7.08 W, Backlight = 213 W(VBR-A = 1.65 V)] LCD (Module) + Backlight(Lamp)

8 Pixel Pitch 0.5415 mm x 0.5415 mm x RGB

9 Back Light CCFL

10 Display Colors 1.06 Billion colors

11 Coating Anti-Reflection coating(2H)

Copyright 2010 LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only
Only for training and service purposes
5. Module optical specification
No. Item Specification Min. Typ. Max. Remark
1. Viewing Angle 2D (CR > 10) Right/Left 89/89 Degree
Up/Down 89/89
3D (CT < 7 %) Right/Left 89/89
Up/Down 10/10
2. Luminance Luminance 2D 320 400 cd/m2
3D 120 150
Variation - 1.3
3. Contrast Ratio 2D 830:1 1200:1
3D 33:1 100:1
4. CIE Color Coordinates RED Rx 0.636
Ry 0.334
Green Gx 0.290
Gy Typ. 0.606 Typ.
Blue Bx -0.03 0.145 +0.03
By 0.064
White Wx 0.279
Wy 0.292
5. 3D Crosstalk 3% At viewing angle Right/
Left/ Up/ Down 0.1 %

1) Standard Test Condition (The unit has been ON)

2) Stable for approximately 30 minutes in a dark environment at 25 C 2 C.
3) The values specified are at approximate distance 50 Cm from the LCD surface.
4) Ta = 25 C 2 C, VLCD = 12.0 V, fv = 60 Hz, Dclk = 74.25 MHz, IBL = 195 mARMS Iout duty = 100 %

6. Component Video Input (Y, CB/PB, CR/PR) - 2D Mode

Specification
No. Remark
Resolution H-freq(kHz) V-freq(Hz)
1. 720x480 15.73 60.00 SDTV,DVD 480i
2. 720x480 15.63 59.94 SDTV,DVD 480i
3. 720x480 31.47 59.94 480p
4. 720x480 31.50 60.00 480p
5. 720x576 15.625 50.00 SDTV,DVD 625 Line
6. 720x576 31.25 50.00 HDTV 576p
7. 1280x720 45.00 50.00 HDTV 720p
8. 1280x720 44.96 59.94 HDTV 720p
9. 1280x720 45.00 60.00 HDTV 720p
10. 1920x1080 31.25 50.00 HDTV 1080i
11. 1920x1080 33.75 60.00 HDTV 1080i
12. 1920x1080 33.72 59.94 HDTV 1080i
13. 1920x1080 56.250 50 HDTV 1080p
14. 1920x1080 67.5 60 HDTV 1080p

Copyright 2010 LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only
Only for training and service purposes
7. RGB (PC) - 2D Mode
Specification
No. Proposed Remark
Resolution H-freq(kHz) V-freq(Hz) Pixel Clock(MHz)
1. 720*400 31.468 70.08 28.321 For only DOS mode
2. 640*480 31.469 59.94 25.17 VESA Input 848*480 60 Hz, 852*480 60 Hz
-> 640*480 60 Hz Display
3. 800*600 37.879 60.31 40.00 VESA
4. 1024*768 48.363 60.00 65.00 VESA(XGA)
5. 1280*768 47.78 59.87 79.5 WXGA
6. 1360*768 47.72 59.8 84.75 WXGA
7. 1280*1024 63.595 60.0 108.875 SXGA
8. 1920*1080 66.587 59.93 138.625 WUXGA

8. HDMI Input - 2D Mode

(1) DTV Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*480 31.469 /31.5 59.94 /60 27.00/27.03 SDTV 480P
2. 720*576 31.25 50 54 SDTV 576P
3. 1280*720 37.500 50 74.25 HDTV 720P
4. 1280*720 44.96 /45 59.94 /60 74.17/74.25 HDTV 720P
5. 1920*1080 33.72 /33.75 59.94 /60 74.17/74.25 HDTV 1080I
6. 1920*1080 28.125 50.00 74.25 HDTV 1080I
7. 1920*1080 26.97 /27 23.97 /24 74.17/74.25 HDTV 1080P
8. 1920*1080 33.716 /33.75 29.976 /30.00 74.25 HDTV 1080P
9. 1920*1080 56.250 50 148.5 HDTV 1080P
10. 1920*1080 67.43 /67.5 59.94 /60 148.35/148.50 HDTV 1080P

(2) PC Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*400 31.468 70.08 28.321 HDCP
2. 640*480 31.469 59.94 25.17 VESA HDCP
3. 800*600 37.879 60.31 40.00 VESA HDCP
4. 1024*768 48.363 60.00 65.00 VESA(XGA) HDCP
5. 1280*768 47.78 59.87 79.5 WXGA HDCP
6. 1360*768 47.72 59.8 84.75 WXGA HDCP
7. 1280*1024 63.595 60.0 108.875 SXGA HDCP/FHD model
8. 1920*1080 67.5 60.00 138.625 WUXGA HDCP/FHD model

Copyright 2010 LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only
Only for training and service purposes
9. 3D Mode - HDMI & USB
(1) HDMI Input
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1 1280*720 45.00 60.00 74.25 Side by Side HDTV 720P
Top & Bottom
89.9 / 90 59.94 / 60 148.35 / 148.5 HDMI(V1.4 with 3D)
Frame Packing
2 1280*720 37.500 50 74.25 Side by Side HDTV 720P
Top & Bottom
75 50 148.5 HDMI(V1.4 with 3D)
Frame Packing
3 1920*1080 33.75 60.00 74.25 Side by Side HDTV 1080I
Top & Bottom
4 1920*1080 28.125 50.00 74.25 Side by Side HDTV 1080I
Top & Bottom
5 1920*1080 27.00 24.00 74.25 Side by Side HDTV 1080P
Top & Bottom
Checkerboard
53.95 / 54 23.98 / 24 148.35 / 148.5 HDMI(V1.4 with 3D)
Frame Packing
6 1920*1080 67.50 60.00 148.50 Side by Side HDTV 1080P
Top & Bottom
Checkerboard
Single Frame Sequential
7 1920*1080 56.250 50 148.5 Side by Side HDTV 1080P
Top & Bottom
* For 3D video feed that is input in the HDMI(V1.4 with 3D) frame Packing format, it is automatically switched to 3D.
** You press the BLUE Button, the left/right video switches.

(2) USB Input

No. Video Size 3D input proposed mode Proposed
1 1920*1080(30FPS) Side by Side HDTV 1080P
Top & Bottom
Checkerboard

(3) 3D Input mode

No. Side by Side Top & Bottom Checkerboard Single Frame Sequential
1
L R
L

Copyright 2010 LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only
Only for training and service purposes
 ADJUSTMENT INSTRUCTION
1. Application Range (2) (3)
This specification sheet is applied to all of the LCD TV with
LD01I chassis.

2. Designation
1) The adjustment is according to the order which is
designated and which must be followed, according to the Please Check the Speed :
To use speed between
plan which can be changed only on agreeing. from 200KHz to 400KHz
2) Power Adjustment: Free Voltage
3) Magnetic Field Condition: Nil.
5) Click Auto tab and set as below
4) Input signal Unit: Product Specification Standard
6) Click Run.
5) Reserve after operation: Above 5 Minutes (Heat Run)
7) After downloading, check OK message.
Temperature : at 25 C 5 C
Relative humidity : 65 % 10 % (4)
Input voltage : 220 V, 60 Hz
filexxx.bin
6) Adjustment equipments : Color Analyzer(CA-210 or CA- (5)
110), Pattern Generator(MSPG-925L or Equivalent), DDC
(7) .OK
Adjustment Jig equipment, Service remote control.
7) Push The IN STOP key - For memory initialization.
(6)

Case1 : Software version up

1. After downloading S/W by USB, TV set will reboot
automatically
2. Push In-stop key * USB DOWNLOAD
3. Push Power on key 1) Put the USB Stick to the USB socket
4. Function inspection 2) Automatically detecting update file in USB Stick
5. After function inspection, Push In-stop key. - If your downloaded program version in USB Stick is Low,
Case2 : Function check at the assembly line it didnt work. But your downloaded version is High, USB
1. When TV set is entering on the assembly line, Push data is automatically detecting
In-stop key at first. 3) Show the message Copying files from memory
2. Push Power on key for turning it on.
-> If you push Power on key, TV set will recover
channel information by itself.
3. After function inspection, Push In-stop key.

3. Main PCB check process

* APC - After Manual-Insult, executing APC

* Boot file Download

1) Execute ISP program Mstar ISP Utility and then click
Config tab.
2) Set as below, and then click Auto Detect and check OK
message
If Error is displayed, Check connection between
computer, jig, and set.
3) Click Read tab, and then load download file (XXXX.bin)
by clicking Read

(1)

fi lexxx.bin

4) Click Connect tab. If Cant is displayed, check

connection between computer, jig, and set.

Copyright 2010 LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
 4) Updating is staring. 3.1. ADC Process
Input signal : Component 480i
Signal equipment displays.

- Component 480I
MODEL: 209 in Pattern Generator(480i Mode)
PATTERN : 65 in Pattern Generator(MSPG-925 Series)

After enter Service Mode by pushing ADJ key,

Enter Internal ADC mode by pushing G key at 5. ADC
Calibration

5) Uploading completed, The TV will restart automatically.

<Caution> Using power on button of the Adjustment R/C,
6) If your TV is turned on, check your updated version and
power on TV.
Tool option.(explain the Tool option, next stage)
* If downloading version is more high than your TV have,
* ADC Calibration Protocol (RS232)
TV can lost all channel data. In this case, you have to
channel recover. if all channel data is cleared, you didnt Item CMD1 CMD2 Data0
have a DTV/ATV test on production line. Adjust Mode In A A 0 0 When transfer the Mode In,
Carry the command.
* After downloading, have to adjust Tool Option again. ADC Adjust A D 1 0 Automatically adjustment
1) Push "IN-START" key in service remote control. (The use of a internal pattern)
2) Select Tool Option 1 and Push OK button.
3) Punch in the number. (Each model hax their number)
Module Tool option1 Tool option2 Tool option3 Tool option4 Adjust Sequence
aa 00 00 [Enter Adjust Mode]
LGD 35393 3110 52902 3584
xb 00 40 [Component1 Input (480i)]
ad 00 10 [Adjust 480i Comp1]
4) Completed selecting Tool option. xb 00 60 [RGB Input (1024*768)]
ad 00 10 [Adjust 1024*768 RGB]
aa 00 90 End Adjust mode
* Required equipment : Adjustment R/C.

3.2. Function Check

(1) Check display and sound
- Check Input and Signal items.
1) TV
2) AV (SCART1/SCART2/ CVBS)
3) COMPONENT (480i)
4) RGB (PC : 1024 x 768 @ 60hz)
5) HDMI
6) PC Audio In
* Display and Sound check is executed by Remote control.

Copyright 2010 LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
4. Total Assembly line process ** Caution **
Color Temperature : COOL, Medium, Warm.
4.1. Adjustment Preparation One of R Gain/G Gain/ B Gain should be kept on 0xC0, and
W/B Equipment condition adjust other two lower than C0.
CA210 : CH 9, Test signal : Inner pattern (85IRE) (when R/G/B Gain are all C0, it is the FULL Dynamic Range
Above 5 minutes H/run in the inner pattern. (power on key of Module)
of adjust remote control)
Cool 13,000 K X=0.269(0.002)
* Manual W/B process using adjusts Remote control.
After enter Service Mode by pushing ADJ key,
Y=0.273(0.002) <Test Signal> Enter White Balance by pushing G key at 6. White
Medium 9,300 K X=0.285(0.002) Inner pattern Balance.
Y=0.293(0.002) (216gray,85IRE)
Warm 6,500 K X=0.313(0.002)
Y=0.329(0.002)

* Connecting picture of the measuring instrument

(On Automatic control)
Inside PATTERN is used when W/B is controlled. Connect to
auto controller or push Adjustment R/C POWER ON ->
Enter the mode of White-Balance, the pattern will come out.

* After done all adjustments, Press In-start button and

Full White Pattern CA-210
compare Tool option and Area option value with its BOM, if
COLOR it is correctly same then unplug the AC cable. If it is not
ANALYZER
TYPE: CA-210 same, then correct it same with BOM and unplug AC cable.
For correct it to the models module from factory Jig model.
* Push the IN STOP key after completing the function
RS-232C Communication
inspection. And Mechanical Power Switch must be set
ON.

* Auto-control interface and directions

1) Adjust in the place where the influx of light like floodlight
4.2. DDC EDID Write (RGB 128Byte )
around is blocked. (illumination is less than 10 lux). Connect D-sub Signal Cable to D-sub Jack.
2) Adhere closely the Color Analyzer (CA210) to the module Write EDID Data to EEPROM(24C02) by using DDC2B
less than 10 cm distance, keep it with the surface of the protocol.
Module and Color Analyzers prove vertically.(80 ~ 100). Check whether written EDID data is correct or not.
3) Aging time * For SVC main Assembly, EDID have to be downloaded to
- After aging start, keep the power on (no suspension of Insert Process in advance.
power supply) and heat-run over 5 minutes.
- Using no signal or full white pattern or the others, 4.3. DDC EDID Write (HDMI 256Byte)
check the back light on. Connect HDMI Signal Cable to HDMI Jack.
Write EDID Data to EEPROM(24C02) by using DDC2B
Auto adjustment Map(RS-232C) protocol.
RS-232C COMMAND Check whether written EDID data is correct or not.
[CMD ID DATA] * For SVC main Assembly, EDID have to be downloaded to
Wb 00 00 White Balance Start Insert Process in advance.
Wb 00 ff White Balance End
RS-232C COMMAND MIN CENTER MAX 4.4. EDID DATA
1) All Data : HEXA Value
[CMD ID DATA] (DEFAULT)
2) Changeable Data :
Cool Mid Warm Cool Mid Warm *: Serial No : Controlled / Data:01
R Gain jg Ja jd 00 172 192 192 192 **: Month : Controlled / Data:00
***:Year : Controlled
G Gain jh Jb je 00 172 192 192 192 ****:Check sum
B Gain ji Jc jf 00 192 192 172 192
R Cut 64 64 64 128
G Cut 64 64 64 128
B Cut 64 64 64 128

Copyright 2010 LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only
Only for training and service purposes
- Auto Download 1) FHD RGB EDID data
After enter Service Mode by pushing ADJ key, 0 1 2 3 4 5 6 7 8 9 A B C D E F
Enter EDID D/L mode. 00 00 FF FF FF FF FF FF 00 1E 6D
Enter START by pushing OK key. 10 01 03 68 73 41 78 0A CF 74 A3 57 4C B0 23
20 09 48 4C A1 08 00 81 80 61 40 45 40 31 40 01 01
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 7E 8A 42 00 00 1E 01 1D 00 72 51 D0 1E 20
50 6E 28 55 00 7E 8A 42 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20
70 00
80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
90 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
A0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
B0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
C0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
D0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
E0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

2-1) FHD HDMI EDID data(47LD920)

0 1 2 3 4 5 6 7 8 9 A B C D E F
00 00 FF FF FF FF FF FF 00 1E 6D

* Edid data and Model option download (RS232) 10 01 03 80 73 41 78 0A CF 74 A3 57 4C B0 23

20 09 48 4C A1 08 00 81 80 61 40 45 40 31 40 01 01
Item CMD1 CMD2 Data0 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C

Download A A 0 0 When transfer the Mode In, 40 45 00 7E 8A 42 00 00 1E 01 1D 00 72 51 D0 1E 20

50 6E 28 55 00 7E 8A 42 00 00 1E 00 00 00 FD 00 3A
Mode In Carry the command. 60 3E 1E 53 10 00 0A 20 20 20 20 20 20
Download A E 00 10 Automatically Download 70 01
80 02 03 26 F1 4E 10 1F 84 13 05 14 03 02 12 20 21
(The use of a internal Data)
90 22 15 01 26 15 07 50 09 57 07
A0 E3 05 03 01 01 1D 80 18 71 1C 16 20 58 2C
B0 25 00 7E 8A 42 00 00 9E 01 1D 00 80 51 D0 0C 20
- Manual Download C0 40 80 35 00 7E 8A 42 00 00 1E 02 3A 80 18 71 38
* Caution D0 2D 40 58 2C 45 00 7E 8A 42 00 00 1E 66 21 50 B0
1) Use the proper signal cable for EDID Download E0 51 00 1B 30 40 70 36 00 7E 8A 42 00 00 1E 00 00
- Analog EDID : Pin3 exists F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F9
- Digital EDID : Pin3 exists
2) Never connect HDMI & D-sub Cable at the same time. 2-2) FHD HDMI EDID data(47LD950)
3) Use the proper cables below for EDID Writing
0 1 2 3 4 5 6 7 8 9 A B C D E F
4) Download HDMI1, HDMI2, separately because HDMI1 is 00 00 FF FF FF FF FF FF 00 1E 6D
different from HDMI2 10 01 03 80 73 41 78 0A CF 74 A3 57 4C B0 23
For Analog EDID For HDMI EDID 20 09 48 4C A1 08 00 81 80 61 40 45 40 31 40 01 01
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
D-sub to D-sub DVI-D to HDMI or HDMI to HDMI
40 45 00 A0 5A 00 00 00 1E 01 1D 00 72 51 D0 1E 20
50 6E 28 55 A0 00 5A 00 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20
70 01
80 02 03 26 F1 4E 10 1F 84 13 05 14 03 02 12 20 21
90 22 15 01 26 15 07 50 09 57 07
A0 20 C0 0E 01 40 0A 3C 08 20 18 20 98 20 58
B0 20 38 20 E3 05 03 01 01 1D 80 18 71 1C 16 20 58
C0 2C 25 00 A0 5A 00 00 00 9E 01 1D 00 80 51 D0 1A
Item Condition Data(Hex)
D0 20 6E 88 55 00 A0 5A 00 00 00 1A 02 3A 80 18 71
Manufacturer ID GSM 1E6D E0 38 2D 40 58 2C 45 00 A0 5A 00 00 00 1E 00 00 00
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7B
Version Digital : 1 01
Revision Digital : 3 03

Copyright 2010 LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
Only for training and service purposes
 * Detail EDID Options are below 5. Model name & Serial number D/L
Product ID
Press Power on key of service remocon.
Model Name HEX EDID Table DDC Function (Baud rate : 115200 bps)
FHD Model 0001 01 00 Analog/Digital Connect RS232 Signal Cable to RS-232 Jack.
Write Serial number by use RS-232.
Must check the serial number at the Diagnostics of SET UP
Serial No : Controlled on production line. menu. (Refer to below).
Month, Year :
ex) Monthly : 02 -> 02
Year : 2009 -> 13
Model Name(Hex):
MODEL MODEL NAME(HEX)
47LD920 00 00 00 FC 00 34 47 4C 44 36 33 30 2D 5A 41 0A 20 20

Checksum: Changeable by total EDID data.

Vendor Specific(HDMI) 5.1. Signal TABLE
INPUT MODEL NAME(HEX) CMD LENGTH ADH ADL DATA_1 ... Data_n CS DELAY

HDMI1 67030C001000B82D
CMD : A0h
HDMI2 67030C002000B82D LENGTH : 85 h ~ 94h (1 byte ~ 16 byte)
HDMI3 67030C003000B82D ADH : EEPROM Sub Address high (00~1F)
ADL : EEPROM Sub Address low (00~FF)
HDMI4 67030C004000B82D Data : Write data
CS : CMD + LENGTH + ADH + ADL + Data_1 ++ Data_n
Delay : 20 ms
4.6. Outgoing condition Configuration
- When pressing IN-STOP key by SVC remocon, Red LED 5.2. Command Set
are blinked alternatively. And then Automatically turn off.
No. Adjust mode CMD(hex) LENGTH(hex) Description
(Must not AC power OFF during blinking)
1 EEPROM WRITE A0h 84h+n n-bytes Write (n = 1~16)

4.7. Internal pressure

Confirm whether is normal or not when between power * Description
boards ac block and GND is impacted on 1.5 kV(dc) or 2.2 FOS Default write : <7mode data> write
kV(dc) for one second. Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart, 0,
Phase
Data write: Model name and Serial number write in
EEPROM.

5.3. Method & notice

A. Serial number D/L is using of scan equipment.
B. Setting of scan equipment operated by Manufacturing
Technology Group.
C. Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0.

Copyright 2010 LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only
Only for training and service purposes
 * Manual Download (Model Name and Serial Number)
If the TV set is downloaded by OTA or Service man,
6. 3D function test
Sometimes model name or serial number is initialized.(Not (Pattern Generator MSPG-3233, HDMI mode No. 371, Pattern
always) No. 81)
There is impossible to download by bar code scan, so It need
Manual download. (1) Must input the signal(No.81) for 3D test like below.
1) Press the instart key of ADJ remote controller.
2) Go to the menu 5.Model Number D/L like below photo.
3) Input the Factory model name or Serial number like photo.

(2) After change to 3D mode, and then select side by side

format.
4) Check the model name Instart menu -> Factory name Can see like the below pattern, if you dont put on the 3D
displayed (ex 42LD920-ZA) glasses.
5) Check the Diagnostics (DTV country only) -> Buyer model
displayed (ex 42LD920)

(3) If you see the TV using by only the left side glass, If Can
see the Red on the center position like below
Its OK.

(4) If you see the TV using by only the light side glass, If Can
see the Red on the center position like below
Its OK.

Copyright 2010 LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only
Only for training and service purposes
 I2C, FPGA Reset

FRC
1. Main board
BUF_TS_CLK/ ERR/ SYN/ DATA[0] 4Ch LVD S ( 10 b it)
LVDS ( 10 b it) LGE7329A

IC502
Buffer
IC900

74LVC541A
CI_TS_DATA[ 0: 7] DDR_A_D[ 0: 15] DDR2 SDRAM 12 V
DDR_A_A[ 0: 12] ( 512Mb )
FE_TS_DATA[ 0: 7] PCM_D[ 0: 7 ] -> CI_DATA[ 0: 7]

Only for training and service purposes

IC1001
DDR_B_D[ 16: 31]

Tu ner
-> CI_MDI[ 0: 7]

CI Slot
DDR_B_A[ 0: 12] DDR2 SDRAM

( P5 00 )

TU10 00
CI_ADDR[ 0: 7] PCM_A[ 0:7] ( 512Mb )

( TDFW-G235 D1 )
IC1000

Buff er
I C501
Reset 74LX1G14C KIA7027
3D Formatter B/D

74LCX244
( IC108) ( IC101)
FE_VMAIN Sc hm it t Trig g er Voltage Detector
Serial Flash Serial Flas h
FE_ VOUT

Copyright 2010 LG Electronics. Inc. All rights reserved.

IC103 IC104
F-SCART Fo r Bo o t Fo r Trit o n
SC1_CVBS_IN SDDR_D[ 0: 15] DDR2 SDRAM
SC1_R/ G/ B Mst ar S6 ( 1Gb )
SDDR_A[ 0: 12]
H-SCART DTV/ MNT_VOUT IC300
SC2_CVBS_IN LGE3369A TDDR_D[ 0: 15] DDR2 SDRAM
TDDR_A[ 0: 12] ( 512Mb )
AV3 AV_CVBS_IN
IC301

- 16 -
/ LGE3369B PCM_A[ 0: 7] NAND Flash EEPROM
COMPONENT AT24C512
COMP_Y/Pb/ Pr HYNIX
( IC105)
IC102
EEPROM
RGB DSUB_ R/ G/ B ( DVIX) I2C
AT24C512
DSUB_H/ VSYNC ( HDCP) IC107
BLOCK DIAGRAM

( IC100) I2S Dig it al am p

SC1/ 2_L/ R_IN, FE_AM_AUDIO, AUDIO IN L/ R
( NTP3100L)
AV_L/ R_IN, COMP_L/ R_IN, PC_L/ R_IN
IC701

USB_DM/ DP USB USB Po wer MP6211DH

USB Po w er
Head
HP_L/ ROUT IC402
TPA6110A HPD1/ 2/ 3/ 4,
Pho ne IC700
HDMI_CEC
5V_HDMI_1/ 2/ 3/ 4
RS-232C HDMI
RGB_TX/ RX
MAX3232 CDR HDMI4 TMDS[ 0: 7] ( Dat a, Clo c k ( + /-) ) 1/ 2/ 3/
IC403 4
SPDIF SPDIF_OUT
HDMI1/ 2/ 3 TMDS[ 0: 7] (Data, Cloc k (+/ -)) HDMI S/ W
( TMDS351)
IC603

LGE Internal Use Only

 Main Board Formatter Board

Only for training and service purposes

2. 3D Formatter Board

Oscill ator

Main B oard I/F, I2C 2.5V 1.8V 1.2V

Copyright 2010 LG Electronics. Inc. All rights reserved.

LVDS, I/ F, I2C LVDS LVDS
51P LVDS 51P LVDS LVDS Rx LVDS Tx 51P LVDS
(2 Ch) (2 Ch)
LVDS
FPGA LVDS
LVDS, 12V
41P LVDS 41P LVDS LVDS Rx LVDS Tx 41P LVDS
(2 Ch) (2 Ch)

- 17 -
12V

Power
FPGA DDR2
Block
config . H5PS5162FFR-S6C
32Mb x 16 x 2

2.5V
1.8V

LGE Internal Use Only

 EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

A32

Child
400

A31

Adult
521
804

540

550
580
803
800

802

805
LV1
LV2
LV3
LV4

900
530

801

A10
A5
200

A2

120
121
300

500

122
310
510

Copyright LG Electronics. Inc. All rights reserved. - 18 - LGE Internal Use Only
Only for training and service purposes
 IC102
+3.3V HY27US08121B-TPCB +3.3V
NAND FLASH MEMORY VOLTAGE DETECTOR

C105 *Mstar reset:Active high reset

NC_1 NC_28
1 48 10uF
/PF_CE0 6.3V
H : Serial Flash NC_2 NC_27
2 47
L : NAND Flash PCM_A[0-7]
/PF_CE1 NC_3 NC_26 +3.3V_ST
3 46
3.9K

H : 16 bit AR102
R105 OPT 1K

1K

NC_4 NC_25
L : 8 bit 4 45
22 R107
NC_5 I/O7 PCM_A[7]
5 44 470
R1540

R111

NC_6 I/O6 PCM_A[6]

6 43
R/B I/O5 PCM_A[5] C102
7 42 10uF
/F_RB R116 IC100 X100 080923_Time Delay
RE
1386 WON I/O4 PCM_A[4]
6.3V
0
12MHz C111
/PF_OE 8 41 LGE3369A (SATURN6 NON RM)
CE NC_24
/PF_CE0 9 40 R193 20pF
PCM_D[0-7]
NC_7 NC_23 1M
1K

10 39 IC101 D4 HWRESET B3
XIN C112
A3
OPT

NC_8 PRE KIA7427F R172 0

C103 11 38 C106 VCC 1 3 OUT XOUT
AC16
R112

PCM_D[0] 20pF
0.1uF VCC_1 VCC_2 0.1uF PCMD0/CI_D0
12 37 C101 2 PCM_D[1] AA15 E6 R173 0
R115 PCMD1/CI_D1 TESTPIN/GND
VSS_1 VSS_2 0.022uF GND 10K PCM_D[2] AA16
13 36 16V PCMD2/CI_D2
PCM_D[3] AC6
NC_9 NC_22 PCMD3/CI_D3
14 35 PCM_D[4] Y10 AE11 R1524 33 SPI_DI G12
PCMD4/CI_D4 SPI_DI
NC_10 NC_21 PCM_D[5] Y11 AF12 SPI_DO
15 34 PCMD5/CI_D5 SPI_DO
PCM_D[6] Y12 AE12 R1525 33 SPI_CS
CLE NC_20 AR103 PCMD6/CI_D6 /SPI_CS
16 33 PCM_A[0-14] PCM_D[7] Y13 AD11 R1526 33 SPI_CK
/PF_CE1 22 PCMD7/CI_D7 SPI_CK
ALE I/O3 PCM_A[3]
PF_ALE 17 32 PCM_A[0] AB16
WE I/O2 PCM_A[2] PCM_A[1] PCM_A0/CI_A0
18 31 AC15
/PF_WE PCM_A[2] PCM_A1/CI_A1
AC14
R1539

WP I/O1 PCM_A[1]
19 30 PCM_A[3] PCM_A2/CI_A2
AB14
1K

+3.3V_ST +3.3V NC_11 I/O0 PCM_A[0] PCM_A[4] PCM_A3/CI_A3

20 29 AC12 B5 R174 0
PCM_A[5] PCM_A4/CI_A4 USB_DP_1
NC_12 NC_19 AB8 A5 R175 0
21 28 PCM_A[6] PCM_A5/CI_A5 USB_DM_1
AC13 AC10 R178 0
R103 NC_13 NC_18 PCM_A[7] PCM_A6/CI_A6 USB_DM_2 SIDE_USB_DM 4:AJ6
R114 22 27 AA9 AB10 R179 0
OPT R151 10K PCM_A7/CI_A7 USB_DP_2 SIDE_USB_DP 4:AJ5
PCM_A[8] AB5
0 NC_14 NC_17 R132 R133 SIDE_USB
23 26 PCM_A[9] PCM_A8/CI_A8
PF_WP AA4 15K 15K
C NC_15 NC_16 PCM_A[10] PCM_A9/CI_A9 OPT
R1509 24 25 V4 OPT
0 PCM_A[11] PCM_A10/CI_A10
B Q100 Y4
KRC103S PCM_A[12] PCM_A11/CI_A11 +3.3V_ST
OPT AB9
OPT PCM_A[13] PCM_A12/CI_A12
E AA7
PCM_A[14] PCM_A13/CI_A13
AD6
PCM_A14/CI_A14 R195 PM GPIO Assignment Recommended by MStar
10K
R1510 33 AA14 E5
PCM_RST PCM_RST/CI_RST GPIO_PM0/GPIO134 WARM_LED_ON 8:B11
R1511 33 AB18 F5 R1520 100
/PCM_CD PCM_CD/CI_CD GPIO_PM1/GPIO135 DBG_TX
+3.3V IC103 +3.3V
R1512 33 Y5 G5 R184 100
W25X32VSSIG EEPROM IC105: EAN43352801(ATMEL SHRINK) /PCM_OE /PCM_OE GPIO_PM2/GPIO136
INV_CTL
8:M10
Serial FLASH MEMORY
R1533

R1513 33 AB15 H5 R185 100 PANEL_CTL OPT 100

4.7K

/PCM_REG R182
L102

0IMMRMP008A(MICROCHIP) PCM_REG/CI_CLK GPIO_PM3/GPIO137 8:Q8 POWER_DET

for BOOT IC105 +3.3V /PCM_WAIT R1514 33 AA10 F6 R186 100 POWER_ON/OFF1 8:P5
M24512-WMW6 PCM_WAIT/CI_WACK GPIO_PM4/GPIO138
CS VCC R1515 33 AC8 G6 DBG_RX
/PCM_IRQA
Flash_WP_1

SPI_CS 1 8 /PCM_IRQA GPIO_PM5/INT1/GPIO139

R1516 33 AC7 H6 R1523 100
/PCM_WE /PCM_WE GPIO_PM6/INT2/GPIO140 POWER_DET
+3.3V
0.1uF

$0.76 E0
1 8
VCC
C100 /PCM_IOWR R1517 33 AA5 AC17 R188 100
/3D_FPGA_RESET 10:AA4
PCM_IOWR/CI_WR GPIO131/LDE/SPI_WPn1
C104

R1530 DO HOLD 0.1uF W4 AB17 OPT

SPI_DO 2 7 R1518 33 R187 100
R104

/PCM_IORD
10K

$0.418 AR100 PCM_IOR/CI_RD GPIO130/LCK ISP_TXD

E1 WC T4 AF11
33 2 7 R1519 33
/PCM_CE /PCM_CE GPIO132/LHSYNC/SPI_WPn
WP CLK /PF_CE0 AE6 AA18
R101 0 3 6 SPI_CK C4 /PF_CE0 GPIO60/PCM2_RESET/RX1
E2 SCL 22 AF6 AA17 R167 100
3 6 R110 /PF_CE1 FE_BOOSTER_CTL 10:AA4
C EEPROM_SCL E19;T19;Y13 D6 /PF_CE1 GPIO62/PCM2_CD_N/TX1
AA12 R159 100 Flash_WP_1 A11
R100 C4 /PF_OE
0 GND DIO 22 /PF_OE
R102 B 4 5 SPI_DI 0 VSS 4 5
SDA
/PF_WE AR101 AA11 R1535 0 SDA1 T22
EEPROM_SDA E20;T19;Y14 D7 /PF_WE
OPT C107 C108 R113 22 PF_ALE AC9 R1536 0 SCL1 T22
Q101 8pF 8pF D6 PF_ALE
E PF_WP Y14
KRC103S OPT OPT A7 PF_AD15
OPT /F_RB AB11 E7 R1537 22 FE_TUNER_SCL
C3 22 F_RBZ LHSYNC2/I2S_OUT_MUTE/RX1
AC18 R1534 100 OPC_EN 11:N20
LVSYNC/GPIO133
EEPROM_SCL R162 0 F8 C6 R1538 22 FE_TUNER_SDA
E16;E19;T19 UART2_TX/SCKM GPIO79/LVSYNC2/TX1
EEPROM_SDA R163 0 D11 F9 R108 22
E16;E20;T19 UART2_RX/SDAM UART2_RX/GPIO84 5V_HDMI_3
R164 0 AB21 F10
SDA0 DDCR_DA UART2_TX/GPIO85 USB_OCD 4:AG3
HDCP EEPROM +3.3V
MCU BOOT STRAP DIMMING SCL0
R165 0 AC21
DDCR_CK UART1_RX/GPIO86
A6 R169 22
5V_HDMI_1
Addr:10101-- 10 : BOOT 51 B6 R170 22
5V_HDMI_2
UART1_TX/GPIO87
11 : BOOT RISC R140 22 J1 AF5
ISP_RXD DDCA_CLK GPIO42/PCM2_CE_N PCM_5V_CTL 5:D24
+3.3V R141 22 J2 AF10 R127 100 CI_TS_DATA[0-7]
ISP_TXD DDCA_DA GPIO43/PCM2_IRQA_N AV_CVBS_DET 4:M4
R142 22 W5
R1545 100 DBG_RX UART_RX2
IC107 PWM0 R143 22 V5 AA8 CI_TS_DATA[0]
CAT24WC08W-T A_DIM DBG_TX
C114 UART_TX2 TS0_D0
R158 Y8 CI_TS_DATA[1]
4.7K 0.1uF R198 R1501 R1544 100 TS0_D1
A0 1 VCC 1K PWM_DIM PWM2 Y9 CI_TS_DATA[2]
8 1K TS0_D2
$0.199 PWM0 AB7 CI_TS_DATA[3]
A1 2 WP R109 4.7K TS0_D3
7 E16;T19;Y13 AA6 CI_TS_DATA[4]
EEPROM_SCL PWM1 C1500 C1501 TS0_D4
A2 3 SCL R161 22 AB6 CI_TS_DATA[5]
6 1uF 2.2uF TS0_D5
R199 R1500 OPT OPT U4 CI_TS_DATA[6]
VSS 4 SDA TS0_D6
5 1K 1K AC5 CI_TS_DATA[7]
R171 22 EEPROM_SDA OPT OPT TS0_D7
AC4 CI_TS_SYN
E16;T19;Y14 TS0_SYNC 5:D10
AD5 CI_TS_VAL
TS0_VLD 5:D10
AB4 CI_TS_CLK
TS0_CLK 5:D10

AB19 BUF_TS_DATA[0] 5:V22

TS1_D0
AA20 BUF_TS_SYN
+3.3V_TUNER TS1_SYNC 5:V22
+5V_GENERAL AB13 AC19
PWM0 BUF_TS_VAL_ERR 5:V21
I2C +3.3V
AB12
PWM0 TS1_VLD
AA19
PWM1 BUF_TS_CLK
PWM1 TS1_CLK 5:V21
AD12
11:AE17 PWM2 PWM2
R150 22 AA13 C10 R154 100
R1505
R1504

R1506

R1507

SCART2_DET
R1503

R1502

PWM3 ET_TXD0
4.7K
4.7K

1.2K

1.2K

2.2K

2.2K

R124

4.7K

B11 R177 100

R125

4.7K

OPT ET_TXD1 SC_RE2 9:N25

A4 A9 R183 100
11:Y9 KEY1 SAR0 ET_TX_CLK SC_RE1 9:N24
AI13;10:I9 FE_TUNER_SDA EEPROM_SDA E16;E20;Y14 B4 C11
11:Y10 KEY2 SAR1 ET_RXD0 SIDE_HP_MUTE 7:G26
AI13;10:I9 FE_TUNER_SCL EEPROM_SCL E16;E19;Y13 F4 C9
LED_ON SAR2 ET_RXD1 HP_DET
R122 0 R1550 100 E4 B10 R190 100
10:I12 FE_DEMOD_SDA SDA0 T21;Y14 7:G25;7:R15;9:AI24;9:AI25 SB_MUTE SAR3 ET_TX_EN EDID_WP 6:AI16;6:AL7;6:AL12
R123 0 R146 0 C4 A10 R191 100 3D_POWER_EN 9:AI24
10:I12 FE_DEMOD_SCL SCL0 IR IRIN ET_MDC
T21;Y14 B9 OPT
R130 0 11:X16;11:AD14 ET_MDIO MODEL_OPT_3
11:J8 MEMC_SDA SDA0 A11 R153 100
T21;Y14 SCART1_DET
MEMC_SCL R131 0 ET_COL
11:Q8 SCL0 T21;Y14 R106 100 AC11
3D_SDA R136 0 HPD3 GPIO44
11:J8
R139 0 3D_I2C_OPT
9:AI24 SCART2_MUTE R156 100 D9
R138 0 3D_I2C_OPT GPIO96
3D_SCL R137 0 AMP_RST R157 100 D10
11:Q8 7:F6 GPIO88
R189 0 D7
SDA_SUB/AMP R128 0 MODEL_OPT_1 GPIO90/I2S_OUT_MUTE
7:F12;11:AG10 SDA1 AK12 R168 0 E11
SCL_SUB/AMP R129 0 MODEL_OPT_2 GPIO91
7:F13;11:AG9 SCL1 AK12 100 E8
8:C6 ERROR_OUT R160
MODEL OPTION GPIO97
NTP_MUTE R166 100 E10
7:R15 GPIO98
R126 0 D6
MODEL_OPT_0 GPIO99
R148 100 D5
COMP_DET GPIO103/I2S_OUT_SD3
R147 100 C5
POWER DETECT DSUB_DET GPIO102
+3.3V

+24V +12V

R1603 R1605 R1607 R1609

+3.3V_ST 3.3K 3.3K
42~47 3.3K 3.3K
32~37 OPT
R1521 R1528
3.9K 2.7K
1% 1% R1612 100
R1543 MODEL_OPT_0
10K SEL2_HDMI_SW
IC1500
+5V_GENERAL MEMC_RESET R1600 100 MODEL_OPT_1
KIA7042AF
I 1 3 O
POWER_DET
+12V
2 R117 10K
32~37
R1527 R1529 G R120
R1601 100
MODEL OPTION +3.3V
32~37 FE_AGC_SPEED_CTL MODEL_OPT_2
1K 1.8K 22
32~37 C 32~37
1% 42~47
R119 R134 /FE_RESET R1611 100 MODEL_OPT_3 PIN NAME PIN NO. HIGH LOW
Q102 B R152
2SC3052 12K 4.7K
32~37
1K C MODEL_OPT_0 D6 LCD PDP OPT
32~37 1%
E R121 R1604 R1606 R1608 R1610
R118 Q103 B 3.3K 3.3K 3.3K 3.3K B9(FHD) FRC NO_FRC
2.2K 2SC3052 OPT OPT MODEL_OPT_1 D7
1K OPT B9(HD) LVDS_B LVDS_A A7
32~37 32~37 R192 100
32~37 32~37 GPIO67 USB_CTL 4:AL4
E R135 MODEL_OPT_2 E11 LED_NORMAL LED_MOVING B8 R155 100 SCART1_MUTE 9:AI25
1.1K GPIO68
MODEL_OPT_3 B9 FHD HD

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX57644502 2009.05.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN_1 1 12

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 +1.26V_VDDC

C2028 C2002 C243 C246 C249 C252 C257 C264 C275 C281 C289 C294 C297 C2000 C2001 C2003 C2005 C219 C220 C261 C268 C270 C278 C280 C282 C290 C295 C298 C299
10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

+3.3V
+3.3V_VDDP +1.8V_DDR
L210
BLM18PG121SN1D

C2004 C2026 C276 C265 C258 C253 C250 C247 C244 C241 C2027 C242 C245 C248 C251 C254 C259 C266 C277 C283 C291 C296
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

IC100
LGE3369A (Saturn6 Non RM)

+1.26V_VDDC
F1 RXACKP AE16 IC100 VDDC : 970mA
CK+_HDMI_SW MEMC_RXE0+
6:X15
F2 RXACKN
LVA0P
AD16
002:Z22;009:S28 LGE3369A (Saturn6 Non RM)
6:X14 CK-_HDMI_SW LVA0M MEMC_RXE0- 002:Z22;009:S28
G2 RXA0P AD15
6:X15 D0+_HDMI_SW LVA1P MEMC_RXE1+ 002:Z23;009:R28
G3 RXA0N AF16
6:X15 D0-_HDMI_SW LVA1M MEMC_RXE1- 002:Z22;009:R28 E16 D16
H3 RXA1P AF15 VDDC_1
D1+_HDMI_SW GND_2
6:X16 LVA2P MEMC_RXE2+ 002:Z23;009:R28 E17 VDDC_2 D17
D1-_HDMI_SW G1 RXA1N AE15 GND_3
6:X16 LVA2M MEMC_RXE2- 002:Z23;009:R28 E18 VDDC_3 D18
H1 RXA2P AD13 GND_4
6:X17 D2+_HDMI_SW LVA3P MEMC_RXE3+ 002:Z25;009:Q28 F7 D19
H2 RXA2N AF14 VDDC_4
D2-_HDMI_SW GND_5
6:X17 LVA3M MEMC_RXE3- 002:Z25;009:Q28 L9 VDDC_5 D20
R207 0 A1 DDCD_A_DA AF13 GND_6
6:X13;6:AL14 DDC_SDA_SW LVA4P MEMC_RXE4+ 002:Z26;009:Q28 L10 H18
B2 DDCD_A_CK AE13 VDDC_6
DDC_SCL_SW R208 0 GND_7
6:X13;6:AL13 LVA4M MEMC_RXE4- 002:Z25;009:Q28 L11 VDDC_7 H19
R247 100 A2 HOTPLUG_A GND_8

LVDS OUT
6:J6 HPD1 VDDC_8 H20
AE14
LVACKP MEMC_RXEC+ 002:Z24;009:Q28 VDDC_9 J20
C3 RXBCKP AD14
LVACKM MEMC_RXEC- 002:Z24;009:R28 L12 VDDC_10 K20
B1 RXBCKN GND_9
L13 VDDC_11 L20
C1 RXB0P AE20 GND_10
LVB0P MEMC_RXO0+ 002:Z17;009:U28 L14 VDDC_12 M20
C2 RXB0N AD20 GND_11
HDMI

LVB0M MEMC_RXO0- 002:Z17;009:V28 L15 VDDC_13 P7

D2 RXB1P AD19 GND_12
LVB1P MEMC_RXO1+ 002:Z18;009:U28 L16 VDDC_14 R7
D3 RXB1N AF20 GND_13
LVB1M MEMC_RXO1- 002:Z18;009:U28 L17 GND_14 VDDC_15 T7
E3 RXB2P AF19
LVB2P MEMC_RXO2+ 002:Z18;009:U28 L18 GND_15 T22
D1 RXB2N AE19 VDDC_16
LVB2M MEMC_RXO2- 002:Z18;009:U28 M9 GND_16 U7
E1 DDCD_B_DA AD17 VDDC_17
LVB3P MEMC_RXO3+ 002:Z20;009:T28 U20
F3 DDCD_B_CK AF18 VDDC_18
LVB3M MEMC_RXO3- 002:Z20;009:T28 M10 GND_17 U22
R201 100 E2 HOTPLUG_B AF17 VDDC_19
6:J6 HPD2 LVB4P MEMC_RXO4+ 002:Z21;009:S28 M11 GND_18 V7
AE17 VDDC_20
LVB4M MEMC_RXO4- 002:Z21;009:T28 M12 V22
AE8 RXCCKP GND_19 VDDC_21
6:X15 CK+_HDMI4 M13 W11
AD8 RXCCKN AE18 GND_20 VDDC_22
6:X14 CK-_HDMI4 LVBCKP MEMC_RXOC+ 002:Z19;009:T28 M14 W12
AD9 RXC0P AD18 GND_21 VDDC_23
6:X15 D0+_HDMI4 LVBCKM MEMC_RXOC- 002:Z19;009:T28 M15 W19
AF8 RXC0N GND_22 VDDC_24
6:X15 D0-_HDMI4 M16 W20
AF9 RXC1P GND_23 VDDC_25
6:X16 D1+_HDMI4 M17 W22
AE9 RXC1N GND_24 VDDC_26
6:X16 D1-_HDMI4 Y22
AE10 RXC2P AA3 C229 2.2uF VDDC_27
6:X17 D2+_HDMI4 AUR0 SC1_R_IN 9:J12 M18
AD10 RXC2N Y1 C230 2.2uF GND_25 +3.3V_VDDP VDDP : 102.3mA
6:X17 D2-_HDMI4 AUL0 SC1_L_IN 9:J10 N4
R248 0 AE7 DDCD_C_DA AE1 C2006 2.2uF GND_26
6:X13;6:AL14 DDC_SDA_4 AUR1 N9 H9
R249 0 AF7 DDCD_C_CK AF3 C2007 2.2uF GND_27 VDDP_1
6:X13;6:AL13 DDC_SCL_4 AUL1 N10 H10
R200 100 AD7 HOTPLUG_C AE3 C2008 2.2uF GND_28 VDDP_2

AUDIO IN
6:W11 HPD4 AUR2 SC2_R_IN 9:AE11 N11 H11
R204 100 J3 CEC AUL2 AE2 C2009 2.2uF GND_29 VDDP_3
6:AM25 HDMI_CEC SC2_L_IN 9:AE10 N12 H12
AA1 C2011 2.2uF GND_30 VDDP_4
AUR3 AV_R_IN 4:M6 N13 N20
AB1 C2012 2.2uF GND_31 VDDP_5
AUL3 AV_L_IN 4:M5 N14 P20
AB2 C2013 2.2uF GND_32 VDDP_6
AUR4 COMP_R_IN 4:K15 W9
N2 HSYNC0/SC1_ID AC2 C2014 2.2uF VDDP_7 +3.3V
SCART_RGB

9:P8 SC1_ID AUL4 COMP_L_IN 4:K13 N15 W10 +3.3V_S6

R210 47 N1 VSYNC0/SC1_FB AB3 C2015 2.2uF GND_33 VDDP_8
9:O6 SC1_FB AUR5 PC_R_IN 4:Z5 N16 AVDD_AU : 36.11mA
R211 47 C200 0.047uF P2 RIN0P/SC1_R AC3 C2016 2.2uF GND_34
9:J6 SC1_R AUL5 PC_L_IN 4:Z6 N17 L209
R212 47 C201 0.047uF R3 GIN0P/SC1_G GND_35 BLM18PG121SN1D
9:J8 SC1_G FE_SIF 10:P13 N18 W7
R213 47 C202 0.047uF R1 BIN0P/SC1_B GND_36 AVDD_AU
9:J9 SC1_B P4 +1.8V_DDR
R214 470 C203 1000pF P3 SOGIN0/SC1_CVBS GND_37
E21;9:O4 SC1_CVBS_IN P9 C284 C293
R215 47 C204 0.047uF P1 RINM W3 C231 0.1uF R241 47 GND_38
SIF0P P10 G12
R216 47 C205 0.047uF T3 BINM W2 C232 0.1uF R242 47 GND_39 AVDD_DDR_1 0.1uF 0.1uF
SIF0M G13
R217 47 C206 0.047uF R2 GINM AVDD_DDR_2
H13
AVDD_DDR_3
R243 R244 P11 H14
F11 R266 100 GND_40 AVDD_DDR_4
10K 10K SPDIF_IN 5V_HDMI_4 P12 H15
R246 22 K3 HSYNC1/DSUB_HSYNC E9 R230 100 GND_41 AVDD_DDR_5
4:C22 DSUB_HSYNC SPDIF_OUT SPDIF_OUT 4:T11 P13 H16
R245 22 K2 VSYNC1/DSUB_VSYNC GND_42 AVDD_DDR_6
4:C22 DSUB_VSYNC P14 W14
R218 47 C212 0.047uF L1 RIN1P/DSUB_R GND_43 AVDD_DDR_7
DSUB

4:C26 DSUB_R P15 W15

R219 47 C207 0.047uF L3 GIN1P/DSUB_G GND_44 AVDD_DDR_8
4:C24 DSUB_G P16 W16
R220 47 C213 0.047uF K1 BIN1P/DSUB_B GND_45 AVDD_DDR_9
4:C23 DSUB_B P17 W17
R221 470 C208 1000pF L2 SOGIN1 AF1 R237 100
HP_ROUT P18
GND_46 AVDD_DDR_10
W18
+3.3V_S6 AVDD_MEMPLL : 23.77mA
AUOUTR0/HP_ROUT 7:G21
AF2 100

AUDIO OUT
R238 HP_LOUT GND_47 AVDD_DDR_11
AUOUTL0/HP_LOUT 7:G19
AD3 R239 100
AUOUTR1/SC1_ROUT SCART1_Rout 9:T14 R4 H17
R222 47 C214 0.047uF V1 RIN2P/COMP_PR+ AD1 R240 100 SCART1_Lout GND_48 AVDD_MEMPLL_1
4:K13 COMP_Pr AUOUTL1/SC1_LOUT 9:S12 R9 T20
COMP

R223 47 C215 0.047uF V2 GIN2P/COMP_Y+ AC1 R250 100 SCART2_Rout GND_49 AVDD_MEMPLL_2
4:K11 COMP_Y AUOUTR2/SC2_ROUT 9:AN15 R10 V20 C262 C269 C273
R224 47 C216 0.047uF U1 BIN2P/COMP_PB+ AD2 R251 100 SCART2_Lout GND_50 AVDD_MEMPLL_3 0.1uF 0.1uF 0.1uF
4:K12 COMP_Pb AUOUTL2/SC2_LOUT 9:AM13 R11
0.01uF

0.01uF

0.01uF

0.01uF

0.01uF

0.01uF

R225 470 C209 1000pF V3 SOGIN2 GND_51

C2017

C2018

C2020

C2021

C2022

C2023

R12
R252

R253

R254

R255

R256

+3.3V_S6 AVDD_LPLL : 4.69mA

R257
22K

22K

22K

22K

22K

R284 100 J5 VSYNC2 GND_52

22K

9:P8 SC2_ID R13

GND_53
R14
A8 R231 22 GND_54
I2S_OUT_MCK AUDIO_MASTER_CLK 7:F7 R15 R20
B7 R232 22 GND_55 AVDD_LPLL
R205 47 C210 0.047uF U3 CVBS1/SC1_CVBS I2S_OUT_WS MS_LRCK 7:F12 +3.3V_AVDD_MPLL
E17;9:O4 SC1_CVBS_IN C7 R233 22
0.047uF U2 CVBS2/SC2_CVBS R16
CVBS

R206 47 C211 I2S_OUT_BCK MS_SCK 7:F12 C279

9:AE2 SC2_CVBS_IN D8 R234 22 GND_56
R226 47 C217 0.047uF T1 CVBS3/SIDE_CVBS I2S_OUT_SD MS_LRCH 7:F12 R17 H7 0.1uF
4:M2 AV_CVBS_IN C8 R274 100 GND_57 AVDD_MPLL
R227 47 C218 0.047uF T2 VCOM1 I2S_IN_SD C236 C237 C238 C239 R18
SEL1_HDMI_SW GND_58
22pF 22pF 22pF 22pF T5 C2029 C2025
OPT OPT OPT OPT GND_59 0.1uF 10uF
C235 T9
M1 CVBS4/S-VIDEO_Y C223 0.1uF 6.3V
GND_60
M2 CVBS6/S-VIDEO_C K4
0.1uF T10 AVDD_33 : 281mA
GND_61
VCLAMP T11 +3.3V_AVDD
H4 GND_62
REFP C233 T12 L206
R235 47 C2024 0.047uF N3 CVBS5 J4 0.1uF GND_63 BLM18PG121SN1D
REFM C234 J7
R236 47 C2019 0.047uF M3 CVBS7 G4 R229 390 0.1uF AVDD_33_1
REXT T13 K7
1% +3.3V GND_64 AVDD_33_2 C263 C271 C274 C260 C267
T14 L7 C286
R228 100 C221 0.047uF W1 CVBS0/RF_CVBS Check GND_65 AVDD_33_3 0.1uF
TV/MNT

10:AA8 FE_VMAIN T15 M7 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

R209 100 C222 0.047uF Y3 VCOM0 AE5 C224 0.1uF GND_66 AVDD_33_4
AUCOM T16 N7
AE4 GND_67 AVDD_33_5 +3.3V_S6
AUVRM T17
Y2 CVBSOUT0/SC2_MNTOUT AF4 C225 10uF 6.3V GND_68
9:AL4 DTV/MNT_VOUT AUVRP T18
AA2 CVBSOUT1 AD4 C226 0.1uF GND_69
FE_VSCART_OUT AUVAG U5 W8
C227 1uF GND_70 AVDD_DM
W13 +3.3V_S6
C228 4.7uF GND_71
Y21 C2030
GND_72 0.1uF
AA23 H8 AVDD_DM : 0.03mA
GND_73 AVDD_USB

C256
0.1uF
Close to IC
as close as possible

AVDD_OTG : 22.96mA

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX57644502 2009.05.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN_2 2 12
MAIN_2

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 DDR2 1.8V By CAP - Place these Caps near Memory
+1.8V_DDR +1.8V_DDR

0.1uF
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
C325

C327

C329

C337
C330

C331

C332

C334

C336

C338

C339

C340

C341
0.1uF

0.1uF
C302 C323

C326

C342
C324

C328
C314

10uF
C303

10uF

C306

C310

C316

C319

C320
C304

C305

C307

C308

C312

C313

C315

C317

C318
0.1uF 0.1uF

Close to DDR Power Pin Close to DDR Power Pin

+1.8V_DDR
+1.8V_DDR +1.8V_DDR

1K 1%

R345
R301

R321

1K 1%

1K

1%
0.1uF
0.1uF

R302 1K 1%

1%
C300 0.1uF

0.1uF
R322

R343
C333 C335
IC300 IC301

1%
0.1uF 0.1uF

1K
IC100

C311
1K
C301

C309
HY5PS1G1631CFP-S6 LGE3369A (Saturn6 Non RM) H5PS5162FFR-S6C

SDDR_D[0] DQ0 G8 J2 VREF AR300 D15 VREF J2 G8 DQ0 TDDR_D[0]

SDDR_A[5] ADDR2_A[5] A_MVREF
SDDR_D[1] DQ1 G2 AR303 G2 DQ1 TDDR_D[1]
SDDR_A[3] ADDR2_A[3] BDDR2_A[9] TDDR_A[9]
SDDR_D[2] DQ2 H7 H7 DQ2 TDDR_D[2]
M8 A0 SDDR_A[0] SDDR_A[1] ADDR2_A[1] ADDR2_A[0] C13 T26 BDDR2_A[0] BDDR2_A[3] TDDR_A[3] TDDR_A[0] A0 M8
SDDR_D[3] DQ3 H3 A_DDR2_A0 B_DDR2_A0 H3 DQ3 TDDR_D[3]
A1 SDDR_A[1] SDDR_A[10] 56 56 ADDR2_A[10] ADDR2_A[1] A22 AF26 BDDR2_A[1] BDDR2_A[1] TDDR_A[1] TDDR_A[1] A1
DQ4 M3 M3 DQ4
SDDR_D[4] H1 A_DDR2_A1 B_DDR2_A1 H1 TDDR_D[4]
M7 A2 SDDR_A[2] ADDR2_A[2] B13 T25 BDDR2_A[2] BDDR2_A[10] 56 TDDR_A[10] TDDR_A[2] A2 M7
SDDR_A[0-12]

TDDR_D[0-15]
SDDR_D[5] DQ5 AR301 A_DDR2_A2 B_DDR2_A2 DQ5 TDDR_D[5]

ADDR2_A[0-12]
H9 AR304 H9
SDDR_D[0-15]

N2 A3 SDDR_A[3] SDDR_A[9] ADDR2_A[9] ADDR2_A[3] C22 AF23 BDDR2_A[3] TDDR_A[3] A3 N2

SDDR_D[6] DQ6 F1 A_DDR2_A3 B_DDR2_A3 F1 DQ6 TDDR_D[6]
N8 A4 SDDR_A[4] SDDR_A[12] ADDR2_A[12] ADDR2_A[4] A13 T24 BDDR2_A[4] TDDR_A[4] A4 N8
BDDR2_A[5] TDDR_A[5]

TDDR_A[0-12]
SDDR_D[7] DQ7 A_DDR2_A4 B_DDR2_A4 DQ7 TDDR_D[7]

BDDR2_A[0-12]
F9 A5 A23 AE23 BDDR2_A[5] A5 F9
N3 SDDR_A[5] SDDR_A[7] ADDR2_A[7] ADDR2_A[5] BDDR2_A[12] TDDR_A[12] TDDR_A[5] N3
SDDR_D[8] DQ8 C8 A_DDR2_A5 B_DDR2_A5 C8 DQ8 TDDR_D[8]
N7 A6 SDDR_A[6] AR302 ADDR2_A[6] C12 R26 BDDR2_A[6] 56 TDDR_A[6] A6 N7
SDDR_D[9] DQ9 SDDR_A[0] ADDR2_A[0] A_DDR2_A6 B_DDR2_A6 BDDR2_A[7] TDDR_A[7] DQ9 TDDR_D[9]
C2 A7 B23 AD22 BDDR2_A[7] A7 C2
P2 SDDR_A[7] ADDR2_A[7] AR305 TDDR_A[7] P2
SDDR_D[10] DQ10 D7 SDDR_A[2] ADDR2_A[2] A_DDR2_A7 B_DDR2_A7 BDDR2_A[0] TDDR_A[0] D7 DQ10 TDDR_D[10]
P8 A8 SDDR_A[8] ADDR2_A[8] B12 R25 BDDR2_A[8] TDDR_A[8] A8 P8
SDDR_D[11] DQ11 D3 SDDR_A[4] ADDR2_A[4] A_DDR2_A8 B_DDR2_A8 BDDR2_A[2] TDDR_A[2] D3 DQ11 TDDR_D[11]
P3 A9 SDDR_A[9] ADDR2_A[9] C23 AC22 BDDR2_A[9] TDDR_A[9] A9 P3
SDDR_D[12] DQ12 D1 SDDR_A[6] 56 ADDR2_A[6] A_DDR2_A9 B_DDR2_A9 BDDR2_A[4] TDDR_A[4] D1 DQ12 TDDR_D[12]
M2 A10/AP SDDR_A[10] ADDR2_A[10] B22 AD23 BDDR2_A[10] TDDR_A[10] A10/AP M2
SDDR_D[13] DQ13 SDDR_A[11] R319 56 ADDR2_A[11] A_DDR2_A10 B_DDR2_A10 BDDR2_A[6] 56 TDDR_A[6] DQ13 TDDR_D[13]
D9 A11 R24 BDDR2_A[11] A11 D9
P7 SDDR_A[11] ADDR2_A[11] A12 TDDR_A[11] P7
SDDR_D[14] DQ14 B1 SDDR_A[8] R320 56 ADDR2_A[8] A_DDR2_A11 B_DDR2_A11 BDDR2_A[11] R325 56 TDDR_A[11] B1 DQ14 TDDR_D[14]
R2 A12 SDDR_A[12] ADDR2_A[12] A24 AE22 BDDR2_A[12] TDDR_A[12] A12 R2
SDDR_D[15] DQ15 B9 A_DDR2_A12 B_DDR2_A12 BDDR2_A[8] R326 56 TDDR_A[8] B9 DQ15 TDDR_D[15]

+1.8V_DDR +1.8V_DDR
L2 BA0 SDDR_BA[0] 56 R303 ADDR2_BA[0] C24 AC23 BDDR2_BA[0] R327 56 TDDR_BA[0] BA0 L2
A_DDR2_BA0 B_DDR2_BA0
L3 BA1 SDDR_BA[1] 56 R304 ADDR2_BA[1] B24 AC24 BDDR2_BA[1] R328 56 TDDR_BA[1] BA1 L3
VDD5 A1 A_DDR2_BA1 B_DDR2_BA1 A1 VDD5
L1 BA2 SDDR_BA[2] 56 R305 ADDR2_BA[2] D24 AB22 BDDR2_BA[2] OPT R329 56 TDDR_BA[2] NC4 L1
VDD4 E1 A_DDR2_BA2 B_DDR2_BA2 E1 VDD4
22 R306 ADDR2_MCLK B14 V25 BDDR2_MCLK R330 22
VDD3 J9 A_DDR2_MCLK B_DDR2_MCLK J9 VDD3
R300

R344
OPT

OPT
TDDR_MCLK
150

150
VDD2 M9 J8 CK SDDR_CK CK J8 M9 VDD2
VDD1 R1 K8 CK /SDDR_CK 22 R307 /ADDR2_MCLK A14 V24 /BDDR2_MCLK R331 22 /TDDR_MCLK CK K8 R1 VDD1
/A_DDR2_MCLK /B_DDR2_MCLK
K2 CKE SDDR_CKE 56 R308 ADDR2_CKE D23 AB23 BDDR2_CKE R332 56 TDDR_CKE CKE K2
A_DDR2_CKE B_DDR2_CKE
R350

R351
OPT +1.8V_DDR +1.8V_DDR
OPT

R346 4.7K R348 OPT 4.7K

0

0
VDDQ10 A9 K9 ODT OPT SDDR_ODT 56 R309 ADDR2_ODT D14 U26 BDDR2_ODT R333 56 ODT K9 A9 VDDQ10
R347 4.7K A_DDR2_ODT B_DDR2_ODT
VDDQ9 C1 L8 CS R349 OPT 4.7K CS L8 C1 VDDQ9
VDDQ8 C3 K7 RAS /SDDR_RAS 56 R310 /ADDR2_RAS D13 U25 /BDDR2_RAS R334 56 /TDDR_RAS RAS K7 C3 VDDQ8
/A_DDR2_RAS /B_DDR2_RAS
VDDQ7 C7 L7 CAS /SDDR_CAS 56 R311 /ADDR2_CAS D12 U24 /BDDR2_CAS R335 56 /TDDR_CAS CAS L7 C7 VDDQ7
/A_DDR2_CAS /B_DDR2_CAS
VDDQ6 C9 K3 WE /SDDR_WE 56 R312 /ADDR2_WE D22 AB24 /BDDR2_WE R336 56 /TDDR_WE WE K3 C9 VDDQ6
/A_DDR2_WE /B_DDR2_WE
VDDQ5 E9 E9 VDDQ5
VDDQ4 G1 G1 VDDQ4
F7 LDQS SDDR_DQS0_P 56 R313 ADDR2_DQS0_P B18 AB26 BDDR2_DQS0_P R337 56 TDDR_DQS0_P LDQS F7
VDDQ3 G3 A_DDR2_DQS0 B_DDR2_DQS0 G3 VDDQ3
B7 UDQS SDDR_DQS1_P 56 R314 ADDR2_DQS1_P C17 AA26 BDDR2_DQS1_P R338 56 TDDR_DQS1_P UDQS B7
VDDQ2 G7 A_DDR2_DQS1 B_DDR2_DQS1 G7 VDDQ2
VDDQ1 G9 G9 VDDQ1
F3 LDM SDDR_DQM0_P 56 R315 ADDR2_DQM0_P C18 AC25 BDDR2_DQM0_P R339 56 TDDR_DQM0_P LDM F3
A_DDR2_DQM0 B_DDR2_DQM0
B3 UDM SDDR_DQM1_P 56 R316 ADDR2_DQM1_P A19 AC26 BDDR2_DQM1_P R340 56 TDDR_DQM1_P UDM B3
A_DDR2_DQM1 B_DDR2_DQM1
VSS5 A3 A3 VSS5
VSS4 E3 E8 LDQS SDDR_DQS0_N 56 R317 ADDR2_DQS0_N A18 AB25 BDDR2_DQS0_N R341 56 TDDR_DQS0_N LDQS E8 E3 VSS4
A_DDR2_DQSB0 B_DDR2_DQSB0
VSS3 J3 A8 UDQS SDDR_DQS1_N 56 R318 ADDR2_DQS1_N B17 AA25 BDDR2_DQS1_N R342 56 TDDR_DQS1_N UDQS A8 J3 VSS3
A_DDR2_DQSB1 B_DDR2_DQSB1
VSS2 N1 N1 VSS2
AR306 AR310
VSS1 P9 SDDR_D[11] ADDR2_D[11] ADDR2_D[0] B15 W25 BDDR2_D[0] BDDR2_D[11] TDDR_D[11] P9 VSS1
R3 NC5 A_DDR2_DQ0 B_DDR2_DQ0 NC5 R3
SDDR_D[12] ADDR2_D[12] ADDR2_D[1] A21 AE26 BDDR2_D[1] BDDR2_D[12] TDDR_D[12]
R7 NC6 A_DDR2_DQ1 B_DDR2_DQ1 NC6 R7
SDDR_D[9] ADDR2_D[9] ADDR2_D[2] A15 W24 BDDR2_D[2] BDDR2_D[9] TDDR_D[9]
A_DDR2_DQ2 B_DDR2_DQ2
SDDR_D[14] 56 ADDR2_D[14] ADDR2_D[3] B21 AF24 BDDR2_D[3] BDDR2_D[14] TDDR_D[14]
VSSQ10 B2 A_DDR2_DQ3 B_DDR2_DQ3 AR311 B2 VSSQ10
NC1 AR307 ADDR2_D[4] C21 AF25 BDDR2_D[4] 56 NC1
VSSQ9 A2 SDDR_D[4] ADDR2_D[4] BDDR2_D[4] TDDR_D[4] A2 VSSQ9
B8 A_DDR2_DQ4 B_DDR2_DQ4 B8
E2 NC2 ADDR2_D[5] C14 V26 BDDR2_D[5] NC2 E2
BDDR2_D[0-15]

VSSQ8 SDDR_D[3] ADDR2_D[3] A_DDR2_DQ5 B_DDR2_DQ5 BDDR2_D[3] TDDR_D[3] VSSQ8

A7 A7
ADDR2_D[0-15]

R8 NC3 ADDR2_D[6] C20 AE25 BDDR2_D[6] NC3 R8

VSSQ7 SDDR_D[1] ADDR2_D[1] A_DDR2_DQ6 B_DDR2_DQ6 BDDR2_D[1] TDDR_D[1] VSSQ7
D2 C15 W26 D2
SDDR_D[6] 56 ADDR2_D[6] ADDR2_D[7] BDDR2_D[7] BDDR2_D[6] 56 TDDR_D[6]
VSSQ6 D8 A_DDR2_DQ7 B_DDR2_DQ7 D8 VSSQ6
AR308 ADDR2_D[8] C16 Y26 BDDR2_D[8] AR312
VSSQ5 E7 VSSDL SDDR_D[15] ADDR2_D[15] A_DDR2_DQ8 B_DDR2_DQ8 BDDR2_D[15] TDDR_D[15] VSSDL E7 VSSQ5
J7 ADDR2_D[9] C19 AD25 BDDR2_D[9] J7
VSSQ4 F2 SDDR_D[8] ADDR2_D[8] A_DDR2_DQ9 B_DDR2_DQ9 BDDR2_D[8] TDDR_D[8] +1.8V_DDR F2 VSSQ4
+1.8V_DDR ADDR2_D[10] B16 Y25 BDDR2_D[10]
VSSQ3 F8 SDDR_D[10] ADDR2_D[10] A_DDR2_DQ10 B_DDR2_DQ10 BDDR2_D[10] TDDR_D[10] F8 VSSQ3
ADDR2_D[11] B20 AE24 BDDR2_D[11]
VSSQ2 H2 SDDR_D[13] 56 ADDR2_D[13] A_DDR2_DQ11 B_DDR2_DQ11 BDDR2_D[13] TDDR_D[13] H2 VSSQ2
AR309 ADDR2_D[12] A20 AD26 BDDR2_D[12] AR313
VSSQ1 VDDL A_DDR2_DQ12 B_DDR2_DQ12 56 VDDL VSSQ1
H8 J1 SDDR_D[7] ADDR2_D[7] Y24 BDDR2_D[7] TDDR_D[7] J1 H8
ADDR2_D[13] A16 BDDR2_D[13]
SDDR_D[0] ADDR2_D[0] A_DDR2_DQ13 B_DDR2_DQ13 BDDR2_D[0] TDDR_D[0]
ADDR2_D[14] B19 AD24 BDDR2_D[14]
SDDR_D[2] ADDR2_D[2] A_DDR2_DQ14 B_DDR2_DQ14 BDDR2_D[2] TDDR_D[2]
ADDR2_D[15] A17 AA24 BDDR2_D[15]
SDDR_D[5] ADDR2_D[5] A_DDR2_DQ15 B_DDR2_DQ15 BDDR2_D[5] 56 TDDR_D[5]
56

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX57644502 2009.05.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. DDR2 3 12
DDR2

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 AV
R400
JK402 0
AV_CVBS_IN
PPJ218-01 AMOTECH
R411 C414
D406 47pF
[YL]O_SPRING 75
4A 30V
+3.3V 50V PC AUDIO
5A [YL]CONTACT
JK401
R401
[YL]U_CAN 4.7K PEJ024-01
2A R409
AV_CVBS_DET E_SPRING
3
[WH]C_LUG AMOTECH C404 1K
3B D403 0.1uF
5.6V 16V 6A T_TERMINAL1
2B [WH]U_CAN

7A B_TERMINAL1
R413 PC_R_IN
4C [RD]O_SPRING 10K 2:S16
AV_L_IN D421 R451 R455
4 R_SPRING C422 15K 0
AMOTECH AMOTECH 100pF R449
[RD]CONTACT
R415
5C 5.6V 470K R453
12K
D404 R410 C413 50V
470K T_SPRING OPT 10K
5.6V 100pF 5
[RD]U_CAN 50V
2C
R452
R414 7B B_TERMINAL2 15K
10K PC_L_IN 2:S16
AV_R_IN
R456
AMOTECH T_TERMINAL2 D422 C424 R450 0
R417

6B
AMOTECH
12K

D405 100pF 470K

5.6V R408 C412 5.6V 50V R454
470K 100pF SHIELD_PLATE OPT 10K
8
50V

+3.3V

COMPONENT
R418
4.7K
R425
AMOTECH 1K
COMP_DET 1:AA22
JK400
D412
SPDIF OPTIC JACK
PPJ229-01
5.6V
Side USB (Minerva OPT)
2A [GN]1P_CAN +5V_GENERAL +5V_GENERAL

IC402
4A [GN]CONTACT MP6211DH +5V_USB_SIDE

ADMC5M03200L_AMODIODE
R419 R462 OUT_3 GND
AMOTECH 0
8 1
3A [GN]O_SPRING 1K
COMP_Y 2:E20
D407 OPT JK403
OUT_2
7 2
IN_1
75
R426

2B [BL]1P_CAN

0.1uF
30V JST1223-001 C405 C407 OUT_1
6 3
IN_2

C403
SPDIF_OUT 0.1uF 10uF
OPT FLAG
5 4
EN

5B [BL]C_LUG_L GND

1
AMOTECH COMP_Pb 2:E20 USB_CTL

Fiber Optic
2:X18 R420
75
R427

D408 C408 1:AI26 10K

2C [RD]1P_CAN1 30V 100pF OPT VCC

2
OPT ZD403
5C [RD]C_LUG_L C406 R403
AMOTECH COMP_Pr 2:E20 0.1uF 47 USB_OCD
VINPUT
D409 16V
75
R428

3
2D [WH]1P_CAN

4
30V 1:AI14
R432 R435
10K 0 FIX_POLE
5D [WH]C_LUG_L
COMP_L_IN 2:S16

KJA-UB-4-0004
JK405

1
D410 C415
R434

R429

USB DOWN STREAM

12K

2E [RD]1P_CAN2 AMOTECH 1000pF

470K
5.6V 50V

2
4E [RD]CONTACT SIDE_USB_DM 1:AL8

R431 R436
3E [RD]O_SPRING 10K 0

3
COMP_R_IN SIDE_USB_DP 1:AL7
2:S16
D411
C417 D425
R433

AMOTECH R430
12K

5.6V 1000pF CDS3C05HDMI1 D426

470K

4
50V 5.6V CDS3C05HDMI1
5.6V

5
+5V_ST
D400
ENKMC2838-T112
A1
C
A2
IC400
CAT24C02WI-GT3 C400
0.1uF
RS232C +5V_ST
A0 VCC
16V
1 8
C425
R406 EDID_WP 1:AJ19 0.33uF
A1 WP R404 R412 R416 16V
2 7
2.2K 2.2K
10K 100
A2 SCL

[ PC ] VSS
3 6

SDA
ISP_RXD C429
0.33uF
4 5 ISP_TXD C428 16V
0.33uF
16V C430
C401 C402 0.047uF
18pF 18pF 25V
50V 50V
DOUT2
RIN2

C2-

C2+

C1-

C1+

R444 R445
V-

V+

22 22
8

D413 IC403
30V
MAX3232CDR
D414
30V
ADUC30S03010L_AMODIODE
0 R437 D419
ADMC5M03200L_AMODIODE
10

11

12

13

14

15

16

2:E18 DSUB_VSYNC
9

5.6V
0 R440
OPT

2:E18 DSUB_HSYNC
ROUT2

DIN2

DIN1

ROUT1

RIN1

DOUT1

GND

VCC

D418
ADMC5M03200L_AMODIODE +3.3V
5.6V +5V_ST
OPT

C431
R447 0.1uF
2:E19 DSUB_B
D415 4.7K 16V
C418 ADUC30S03010L_AMODIODE JP414 R448
R443

OPT 30V DSUB_DET IR_OUT

75

JP412 D420 1K
R446 ADMC5M03200L_AMODIODE
0 R461
5.6V R457 R458 D423 OPT
6.2K 6.2K 0
R460

R459
OPT

OPT OPT ADUC30S03010L_AMODIODE

100

100
@maker

30V
2:E19 DSUB_G
JP413
C419 DBG_TX
R441

D416
OPT ADUC30S03010L_AMODIODE
75

30V DBG_RX
D424 OPT
11

12

13

14

15

ADUC30S03010L_AMODIODE
C426 220pF 50V 30V
16
10
6

C427 220pF 50V

1

2:E18 DSUB_R
C420
R442

D417 P400 P401

OPT ADUC30S03010L_AMODIODE KCN-DS-1-0088
75

KCN-DS-1-0089
30V
6

10
1

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX57644502 2009.05.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. INTERFACE 4 12
INTERFACE

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 DVB-CI SLOT
+5V_CI_ON
DVB-CI TS INPUT

CI_DATA[0-7] AR506
33 FE_TS_DATA[7]
CI_MDI[7] FE_TS_DATA[6]
CI_MDI[6]

FE_TS_DATA[0-7]
FE_TS_DATA[5]
CI_MDI[5] FE_TS_DATA[4]
CI_MDI[4]

CI_DATA[0-7]
+5V_GENERAL AR507 FE_TS_DATA[3]
C505 33
CI_MDI[3] FE_TS_DATA[2]
10uF
10V CI_MDI[2] FE_TS_DATA[1]
R505

EAG41860101
10K

CI_MDI[1] FE_TS_DATA[0]
P500 CI_MDI[0]
/CI_CD1
C501 10067972-050LF
FE_TS_DATA[0-7]
0.1uF
16V 35 AR513
33
R511 100 36 CI_DATA[3] D14 CI_MISTRT FE_TS_SYN
37 3 CI_DATA[4] FE_TS_VAL_ERR

R517
AR500 CI_MIVAL_ERR

10K
33 38 4 CI_DATA[5]
CI_TS_DATA[4]
39 5 CI_DATA[6] FE_TS_CLK
CI_TS_DATA[5] CI_MCLKI
40 6 CI_DATA[7]
CI_TS_DATA[6]
CI_TS_DATA[7] 41 7 R515 47
/PCM_CE
42 8 CI_ADDR[10]
R508 10K 43 9 CI_OE
44 10 CI_ADDR[11]
CI_IORD
45 11 CI_ADDR[9] +5V_GENERAL
CI_IOWR
46 12 CI_ADDR[8]
CI_ADDR[13]

R518
47 13

10K
CI_MDI[0]
48 14 CI_ADDR[14]
CI_MDI[1]
CI_MDI[2] 49 15 CI_WE
50 16 R516 100
CI_MDI[3] /PCM_IRQA
C503 0.1uF 51 17
R513 0 R514 0 C509
52 18 C508
GND 0.1uF
OPT 53 19 OPT 0.1uF
CI_MDI[4] 16V
GND
CI_MDI[5] 54 20
55 21 CI_ADDR[12]
CI_MDI[6]
GND
DVB-CI HOST I/F
56 22 CI_ADDR[7]
CI_MDI[7]
R509 10K 57 23 CI_ADDR[6]
R503 47 58 24 CI_ADDR[5]
PCM_RST
R500 47 59 25 CI_ADDR[4] CI_DET
/PCM_WAIT
AR503 60 26 CI_ADDR[3]
REG
33 61 27 CI_ADDR[2]
CI_TS_CLK
CI_TS_VAL 62 28 CI_ADDR[1]
CI_TS_SYN 63 29 CI_ADDR[0] IC501 +3.3V_CI
64 30 CI_DATA[0] C511
65 31 CI_DATA[1] 0.1uF
CI_ADDR[0-14] 1OE VCC 16V
CI_TS_DATA[0] 66 32 CI_DATA[2] 1 20
33 TOSHIBA
CI_TS_DATA[1] 67 33
CI_TS_DATA[2] 68 34 1A1 2OE
CI_TS_DATA[3] PCM_A[0] 2 19
0
OPT

AR504 G2
2 G1
1 0ITO742440D
2Y4 1Y1
R512

R510 100 CI_ADDR[7] 3 18 CI_ADDR[0]

/CI_CD2
R507

+5V_GENERAL GND
10K

1A2 2A4
PCM_A[1] 4 17 PCM_A[7]
GND
2Y3 1Y2

TC74LCX244FT
CI_ADDR[6] 5 16 CI_ADDR[1]
R506 GND
1A3 2A3
10K C502 6 15
PCM_A[2] PCM_A[6]
0.1uF
16V
2Y2 1Y3
CI_ADDR[5] 7 14 CI_ADDR[2]
CI_MISTRT
CI_MIVAL_ERR 1A4 2A2
PCM_A[3] 8 13 PCM_A[5]

CI_MCLKI 2Y1 1Y4

CI_ADDR[4] 9 12 CI_ADDR[3]

GND 2A1
10 11 PCM_A[4]

DVB-CI SERIAL BUFFER TS

+3.3V_CI CI_DATA[0] AR508 PCM_D[0]

33
CI_DATA[1] PCM_D[1]

CI_DATA[0-7]
CI_DATA[2] PCM_D[2]
DVB-CI DETECT CI_DATA[3] PCM_D[3]

PCM_D[0-7]
+3.3V_CI CI_DATA[4] AR509 PCM_D[4]
+3.3V_CI 33
IC502 CI_DATA[5] PCM_D[5]
IC500
74LVC1G32GW CI_DATA[6] PCM_D[6]
E12 74LVC541A(PW)
B 1 5 VCC CI_DATA[7] PCM_D[7]
/CI_CD2
0.1uF
0.1uF

R520

C512
C510

10K

A 2
/CI_CD1 16V
OE1 VCC
D4 GND 3 4 Y 1 20
PCM_D[0-7]

AB9 AE5;10:J17 A0 OE2 CI_DATA[0-7]

GND FE_TS_CLK 2 19
R519
CI_DET
47 AE5;10:W19 R526
R521 A1 Y0 47
/PCM_CD
1:AA10 FE_TS_VAL_ERR 3 18 BUF_TS_CLK
AR510
47 33
AE5;10:J17 R528 CI_ADDR[8] PCM_A[8]
A2 Y1 47
FE_TS_SYN 4 17 BUF_TS_VAL_ERR CI_ADDR[9] PCM_A[9]
BUFFER

R527 CI_ADDR[10] PCM_A[10]

AG4;10:J17 A3 Y2 47
FE_TS_DATA[0] 5 16 CI_ADDR[11] PCM_A[11]
BUF_TS_SYN

R522 R525
10K A4 Y3 47
6 15 BUF_TS_DATA[0]
CI POWER ENABLE CONTROL AR511
R523 33
A5 Y4 CI_ADDR[12] PCM_A[12]
10K
7 14 CI_ADDR[13] PCM_A[13]
CI_ADDR[14] PCM_A[14]
A6 Y5 /PCM_REG
+5V_CI_ON 8 13 REG
+5V_ST Q501
RSR025P03 A7 Y6
S D 9 12
AR512
33
GND Y7 CI_OE /PCM_OE
R504
C500 22K G C507 10 11 CI_WE /PCM_WE
0.1uF 0.1uF R524
16V 33K CI_IORD /PCM_IORD
16V
CI_IOWR /PCM_IOWR
C504
R529
10uF
2.2K
10V
C
R502
10K B Q500
PCM_5V_CTL 2SC3052

E
R501
33K

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX57644502 2009.05.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. PCMCIA 5 12
PCMCIA

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 5V_HDMI_1

HDMI EEPROM
C
R615
Q601 B 10K
2SC3052 HPD1
22 5V_HDMI_1 +5V_ST
E
C600
19

A2

A1
0.1uF
18
16V UI_HW_PORT2 ENKMC2838-T112
JP600

R612
R600
2K

1K D600
17

C
R610 22
16 DDC_SDA_1 IC600

D0+_HDMI2
D0-_HDMI2

CK+_HDMI2
CK-_HDMI2
DDC_SCL_2
DDC_SDA_2
D2+_HDMI2
D2-_HDMI2

D1+_HDMI2
D1-_HDMI2
2:E10;AL9 EDID_WP
JP601

DDC_SCL_1
CAT24C02WI-GT3
15 R611 22 +3.3V JP606
2:E10;AL9

BLM18PG121SN1D
14 R607 +5V_HDMI_SW
0 K19;X14;AH25 A0 VCC
CEC_REMOTE 1 8
13

L600
2:E8
CK-_HDMI1 R618
12 A1 WP 0 R626 R629

MMBD301LT1G
2 7
EAG39789402

C603
0.1uF 4.7K 4.7K
11 2:E8
CK+

OPT
10 CK+_HDMI1 A2 SCL

D605
3 6

30V
D0- 2:E9 DDC_SCL_1
9 R623 0
D0-_HDMI1 C608 C609 C610 C611 C612 C613 C614
D0_GND 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF VSS SDA
8 4 5
2:E8 C616 R621 0 DDC_SDA_1

RESERVE2
D0+ 0.1uF
7 D0+_HDMI1
OPT

VCC_8

GND_7

VCC_7
D1- 2:E9

HPD3

SCL2
SDA2
HPD2
6

A24
B24

A23
B23

A22
B22

A21
B21
D1-_HDMI1
D1_GND

EDID_WP
5
D1+

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
2:E9
4

UI_HW_PORT1

UI_HW_PORT3
D1+_HDMI1
D2- 2:E9 SDA3 1 48 A14
3 DDC_SDA_1 D2+_HDMI3
D2-_HDMI1 SCL3 47 B14
DDC_SCL_1 2
D2_GND D2-_HDMI3
2 GND_1 3 46 VCC_6 5V_HDMI_2
+5V_ST
D2+ 2:E9 B31 4 45 A13
1 D2+_HDMI1
CK-_HDMI1
A31 B13 D1+_HDMI3 IC602
44

A2

A1
5
CK+_HDMI1
VCC_1 GND_6 D1-_HDMI3 CAT24C02WI-GT3
6 IC603 43 JP611 ENKMC2838-T112
20 B32 A12
7 42 D602
D0-_HDMI1
A32
BU16027KV B12
D0+_HDMI3

C
21 8 41 A0 VCC
D0+_HDMI1 D0-_HDMI3 1 8
GND_2 9 40 VCC_5
B33 10 39 A11 R640
D1-_HDMI1 CK+_HDMI3 A1 WP 0 R649
R646
J600
GND UI_HW_PORT1 D1+_HDMI1
VCC_2
A33 11
12
38
37
B11
SCL1
CK-_HDMI3
2 7 C607
0.1uF 4.7K 4.7K
DDC_SCL_3
B34 13 36 SDA1 A2 SCL
D2-_HDMI1 DDC_SDA_3 3 6 DDC_SCL_2
A34 14 35 HPD1
D2+_HDMI1 R645 0
R624 GND_3 15 34 RESERVE1
5V_HDMI_2 4.7K VSS SDA
VSADJ 16 33 S2 4 5 DDC_SDA_2
+3.3V
1/10W R642 0

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1%
C
R616

4.7K
R650
OPT
Y4
Z4
VCC_3
Y3
Z3
GND_4
Y2
Z2
VCC_4
Y1
Z1
GND_5
SCL_SILK
SDA_SILK
HPD_SILK
S1
Q602 B 10K GND
2SC3052 HPD2
22
E

R633
C601 5V_HDMI_3
19 +5V_ST
0.1uF

HDMI4_LH_TOOL
16V
18 R613
R601
2K

A2

A1
1K JP609
17 2:E12;AL19 ENKMC2838-T112
R603 22
DDC_SDA_2 D606
16 2:E12;AL18

C
15 R604 22 DDC_SCL_2 SEL1_HDMI_SW IC6004
CAT24C02WI-GT3 EDID_WP
14 R605 JP603 K8;X14;AH25 SEL2_HDMI_SW
0
CEC_REMOTE JP608
D2+_HDMI_SW
D2-_HDMI_SW

D1+_HDMI_SW
D1-_HDMI_SW

D0+_HDMI_SW
D0-_HDMI_SW

CK+_HDMI_SW
CK-_HDMI_SW
13 +3.3V A0 VCC

HDMI4_LH_TOOL
2:E11 HDMI4_LH_TOOL
CK-_HDMI2 1 8

HDMI4_LH_TOOL
12
R641 HDMI4_LH_TOOL
EAG39789402

11 2:E10 A1 WP 0 R644
CK+ 2 7 C615 R643
10 0.1uF 4.7K
CK+_HDMI2 HDMI4_LH_TOOL 4.7K
D0- 2:E11

4.7K
R651
9 A2 SCL

4.7K
R652
D0-_HDMI2 R647 0
3 6
D0_GND DDC_SCL_3
8 HDMI4_LH_TOOL
D0+ 2:E11 VSS SDA
7 D0+_HDMI2 DDC_SDA_SW 4 5
R648 0 DDC_SDA_3
D1- 2:E11 DDC_SCL_SW
6 D1-_HDMI2 HDMI4_LH_TOOL
D1_GND
5
D1+ 2:E11
4 D1+_HDMI2
D2- 2:E12
3 5V_HDMI_4
D2-_HDMI2 +5V_ST
D2_GND
2

A2

A1
D2+ 2:E12
1 D2+_HDMI2 ENKMC2838-T112
D601

C
20
IC601
21 CAT24C02WI-GT3 EDID_WP
JP607

J601
UI_HW_PORT2 A0
1 8
VCC

GND
R619

SIDE HDMI A1

A2
2 7
WP

SCL
0 C604
0.1uF
R628
4.7K
R630
4.7K

R620 0
3 6
DDC_SCL_4
5V_HDMI_3
5V_HDMI_4 VSS SDA
4 5
HDMI4_LH_TOOL R622 0 DDC_SDA_4
C
R634
Q604 B 10K C
JACK_GND R617
2SC3052 HPD3 10K
22 Q603 B
HDMI4_LH_TOOL 2SC3052 HPD4
E HDMI4_LH_TOOL 20
HDMI4_LH_TOOL

C606
19 E
0.1uF
C602
16V 19
18 R635 0.1uF
R636
2K

1K HDMI4_LH_TOOL JP610 16V

18 R614
JP604

17
R602

HDMI4_LH_TOOL
2K

R637 22 1K
DDC_SDA_3 17 22 2:E14;AL14
16 R608
HDMI4_LH_TOOL DDC_SDA_4
JP605

DDC_SCL_3 16
15 R638 22 2:E15;AL13 +3.3V_ST
14

13
R639
HDMI4_LH_TOOL
0
JP602
CEC_REMOTE
$0.26
15

14
R606

R609
22
K19;K8;AH25
DDC_SCL_4
HDMI_CEC
0
CEC_REMOTE R627
CK-_HDMI3 13 R631
12 2:E13 68K
HDMI4_LH_TOOL

CK-_HDMI4 9.1K
EAG39789402

12
11
CK+
EAG42463001

10 CK+_HDMI3 11 Q600 MMBD301LT1G

CK+ 2:E13 SSM6N15FU
D0- 10 D603
9 D0-_HDMI3 CK+_HDMI4
D0- 2:E13 30V
D0_GND 9
8 D0-_HDMI4
D0_GND SOURCE1 DRAIN1
D0+ 8 HDMI_CEC 1 6 CEC_REMOTE
7 D0+_HDMI3
D0+ 2:E13
D1- 7
6 D0+_HDMI4 GATE1 GATE2
D1-_HDMI3 2 5
D1- 2:E14
D1_GND 6
5 D1-_HDMI4
D1_GND DRAIN2 SOURCE2
D1+ 5
4 3 4
D1+_HDMI3 C605
D1+ 2:E14
D2- 4 0.1uF
3 D2-_HDMI3 D1+_HDMI4
D2- 16V
D2_GND 3 2:E14
2 D2-_HDMI4
D2_GND
D2+ 2 R625 0 GND
1 D2+_HDMI3
D2+ 2:E14
1 OPT
D2+_HDMI4
20

21

UI_HW_PORT3
J603
GND GND UI_HW_PORT4
J602

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX57644502 2009.05.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 6 12
HDMI

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 D704 R725 R705
1N4148W 12 12 SPK_L+ AB10
100V
+24V OPT C755
L704 0.01uF
C741 DA-8580 50V
1000pF C749 R730
EAP38319001 R734
50V 0.1uF 4.7K
2S 2F 50V 3.3
C733 C729
0.1uF C725 C742
C745
0.47uF SPEAKER_L
0.1uF 1000pF 50V
50V 10uF 50V 1S 1F R735
50V 35V
D705 C750 3.3
0.1uF R731
1N4148W R726 50V C756
R713 4.7K 0.01uF
100V 50V
OPT 12 12
C716 SPK_L- AB11
22000pF
50V C726
22000pF
50V

PGND1A_2
PGND1A_1

PVDD1A_2
PVDD1A_1
PVDD1B_2
PVDD1B_1

PGND1B_2
PGND1B_1
C727

OUT1A_2
OUT1A_1

OUT1B_2
OUT1B_1
0.1uF
R704 16V

BST1B
VDR1B
100
1:AA21 AMP_RST
C707

56
55
54
53
52
51
50
49
48
47
46
45
44
43
1000pF
50V R740 C730
0 BST1A 42 NC 0.1uF R727 R716
2:X21 AUDIO_MASTER_CLK C713 1 C732 SPK_R+
16V D706 AB11
VDR1A 2 41 VDR2A 22000pF 12 12
0.1uF16V 1N4148W
RESET 40 BST2A 50V
+3.3V 3 100V L705
+1.8V_AMP C757
AD 4 39 PGND2A_2 OPT C743 DA-8580
1000pF 0.01uF
+1.8V_AMP DVSS_1 38 PGND2A_1 50V EAP38319001 C746 C751 R732
C709 5 0.47uF 50V
2S 2F
BLM18PG121SN1D

0.1uF VSS_IO 37 OUT2A_2 50V 0.1uF 4.7K R736

6 IC701
CLK_I 7 36 OUT2A_1 C744
50V 3.3 SPEAKER_R
BLM18PG121SN1D

L701 1000pF
C708 VDD_IO 8 35 PVDD2A_2 50V 1S 1F
R703

C705 1000pF R737

L700 50V DGND_PLL EAN60664001 PVDD2A_1
9 34 3.3
100pF
0

R708 AGND_PLL 33 PVDD2B_2 D707 C752 R733

50V 10 R728
1N4148W R719 0.1uF 4.7K C758
3.3K LFM 11 NTP-3100L 32 PVDD2B_1 0.01uF
100V 12 12 50V
AVDD_PLL OUT2B_2 OPT 50V
12 31 SPK_R- AB12
DVDD_PLL 13 30 OUT2B_1
C728 C720
TEST0 14 29 PGND2B_2 0.1uF 0.1uF
50V 50V
C700 C702
1uF 0.1uF C704 C706 +24V

15
16
17
18
19
20
21
22
23
24
25
26
27
28
10V 16V 1uF 0.1uF
10V 16V

DVSS_2
DVDD
SDATA
WCK
BCK
SDA
SCL
MONITOR_0
MONITOR_1
MONITOR_2
FAULT
VDR2B
BST2B
PGND2B_1
+1.8V_AMP
C734 C735 C736
10uF
0.1uF 0.1uF 35V
50V 50V
MCLK SDATA WCK BCK TP is necessory C760 C724
1uF C715 0.1uF C731
10V 0.1uF 16V
16V
22000pF
50V
R722 100
2:X21 MS_LRCH +3.3V_ST
R720 100 C721
2:X21 MS_LRCK 0.1uF
R721 100 16V
2:X21 MS_SCK
R709 100 R724
1:L22;11:AG10 SDA_SUB/AMP R718 100 10K D709
R710 100 ENKMC2838-T112
1:L22;11:AG9 SCL_SUB/AMP C A1
R729 SB_MUTE 1:AA19;G25;9:AI24;9:AI25
Q701 B C
C712 C714 R717
33pF 33pF 33K OPT 2SC3052 10K A2
NTP_MUTE 1:AA22
50V 50V E WAFER-ANGLE

L706
120-ohm
AE3 SPK_L+
4
L707
120-ohm
Monitor0_1_2 TP is necessory AE5 SPK_L-
3
L709
120-ohm
AE7 SPK_R+
2
L708
120-ohm
AE9 SPK_R-
1

P700

2A => 5A

EARPHONE AMP

HP_LOUT IC700
TPA6110A2DGNRG4
2:X19 +3.3V
+5V_EARPHONE
C717
R712 0.22uF
BYPASS IN1- 20K
1 8
47uF
C718

16V
27K
R711

C701 16V R707

R701 1uF 10K
10K GND VO1
6.3V 2 7
D710 4
R714 C723 C761
5.6V
SHUTDOWN VDD 0.1uF 22uF
3 6 1K AMOTECH
16V
47uF
C719

3
16V

C703 C710
HP_ROUT 0.22uF R702 HP_DET
16V 20K IN2- VO2 0.1uF
4 5 2
16V
R715 C722 D711 C762
2:X19 1
0.1uF AMOTECH 22uF
1K 5.6V
+5V_EARPHONE 16V 5
+5V_EARPHONE +5V_GENERAL
R706 D700
C711 ENKMC2838-T112 DJ-S3600LM
27K
R742 100uF A1
JK700
10K C 16V C
R700 B A2
Q700
10K 2SC3052
C
E
R741 B Q705
HP_MUTE
10K 2SC3052
J25;M25
E

D708
ENKMC2838-T112
A1
1:AA19;R15;9:AI24;9:AI25 SB_MUTE
C
HP_MUTE
A2
1:AJ19 SIDE_HP_MUTE E23;M25

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX57644502 2009.05.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. AMP 7 12
AMP

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 FROM LIPS & POWER B/D +12V
L810
+12V
BLM18PG121SN1D
+12V
C842 C845
C841 0.1uF 10uF
0.01uF 16V 16V R848
25V 100K
+5V_GENERAL OPT Q806
RSR025P03 +5V_HDMI_SW
+3.3V_ST S D
IC808
R818 MP2305DS
BackLight On/Off +5V_ST BLM18PG121SN1D
3.3K R842 C847 PANEL_POWER C868
10K 4.7uF 0.1uF L818
R814 G 16V
R822 +3.3V_ST R837 16V C853 BS SS
100 RT1P141C-T112 1 8
10K 22K
Q801 C864
R815 P800 +1.8V_DDR 1uF $0.28 0.1uF
C R804 R843 IN EN
R821 6.8K FW20020-24S 1.8K 25V 16V
INV_CTL 10K 2 7
10K B Q802 OPT 3 1 C860
C848
2SC3052 R807 R805 OPT C1130 5.6nF R852
OPT 0.01uF 50V
33K 2 4.7K R806 C SW COMP 9.1K
. . R832 C835 C839 25V 3 6
R823 E 1 2 OPT 0 10K B Q805 22uF 0.47uF
10K . .
3 4 C R802 2SC3052 25V 25V
OPT +24V . 5 6 . 10K OPT C859 GND FB
Q800 B R810 0 C 4 5
. . R833 E 0.1uF
L804 7 8 2SC3052
PANEL_CTL
10K B Q804 R839 16V R2 R853 +5V_GENERAL
CB3216UA121 . 9 10 . POWER_ON/OFF1 22K 12.4K R811
E 2SC3052 R847
. . 1:AK10 R1 1% +5V_USB_SIDE
11 12 56K BLM18PG121SN1D
OPT E 1% 1
C813 . 13 14 . +5V_ST
C832 C821 Vout=0.923*(1+R1/R2) L821 R801
68uF 68uF 0.1uF . 15 16 . L806
35V 35V 50V CB3216UA121
17 . 18 . L819 1 C809
C858 C850 C812
. 22UH 470uF
19 12 20 22uF 0.1uF 0.1uF
L829 16V 16V
BLM18PG121SN1D 21 11 14 22 16V 16V
C802 C885
. C824 +3.3V +1.8V_DDR
23 13 24 0.1uF 0.1uF
OPC_OUT2 220uF
16V 16V
37"42"47"_OPC2 C834
16V
16V +5V 450 mA
0.1uF
OPT +12V L826
L807 C877
2.2uH
0.1uF

R872
CB3216UA121 Vout=0.8*(1+R1/R2)

10K
ERROR_OUT R841 C807 R1
16V
+12V
0 0.1uF
16V
C820
C865
0.1uF
C826
100uF
R809
10.5K
5V SEPERATE FRC WITH TUNER 5V
0.1uF
OPT 16V 16V 16V 1% +12V
C829

PGND2_2
1uF
6.3V

SW2_2

SW2_1
R2 R803
A_DIM R859 22 R871

EN2

FB2
R851 4.7K PWM_DIM 100K
8.2K 22uF
OPT
1% C876 IC810
C818

20

19

18

17

16
6.3V
OPC_OUT1 +5V_ST MP2305DS
1uF BLM18PG121SN1D PGND2_1 1 15 ITH2 C823
C895 L828 0.1uF
L817 PVCC_1 2 14 AVCC 16V
OPT 0.1uF BS SS
BLM18PG121SN1D 10uF 1 8
16V
C878 PVCC_2 3 IC806 13 NC
BD9150MUV
R874 $0.28
PVCC_3 AGND IN EN
4 12 75K 2 7
10uF C862
R873 C863
C879 PGND1_1 5 11 ITH1 5.6nF R813
5% 0.01uF 50V
SW COMP 9.1K
56000 C816 25V

10
C804 3 6

9
22uF 0.47uF
5% C883 25V
25V

PGND1_2

SW1_1

SW1_2

EN1

FB1
330pF GND FB

Stand-by +3.3V 22uF

C880
C882
330pF
4 5
R2 R850
12.4K
+3.3V_MEMC

33K
R849
+3.3V_AVDD

1%
R1 1%
L827 BLM18PG121SN1D
L805 L815
2.2uH BLM18PG121SN1D Vout=0.923*(1+R1/R2)
+5V_ST +3.3V_ST
GND
L808
C811 22UH C867 C869
Replaced Part GND
+3.3V_ST +3.3V_AVDD_MPLL 0.1uF 22uF 0.1uF
IC801 16V 16V 16V
L803 +3.3V
AP1117E33G-13 +3.3V_ST
BLM18PG121SN1D
IN $0.048 ADJ/GND
3 1
C815
C803 2 C806 C808 0.1uF
100uF R856 C825 +3.3V_CI
0.1uF OUT 0.1uF 16V
16V 16V 16V 4.7K 0.1uF
16V L814
R800 BLM18PG121SN1D
1:AK11 POWER_ON/OFF1
10K C852
0.1uF
10uF
C866
16V +1.26V Core for FRC
Vout=0.8*(1+R1/R2)
600mA
+3.3V Replaced Part
IC803
+1.8V_AMP
AP1117E18G-13

IN $0.048 ADJ/GND
3 1
+5V_GENERAL +3.3V_TUNER 50 mA +3.3V_MEMC
2
Replaced Part OUT C822 C827
C800 C814 100uF
100uF 0.1uF
IC809 0.1uF 16V
16V 16V IC802
AP1117E33G-13 16V
BD9130EFJ-E2 R844
IN $0.048 ADJ/GND 10K
3 1
C890 2 C893 C894 ADJ EN
C892 100uF +3.3V IC804 1 8
0.1uF OUT 0.1uF +1.2V_TUNER
100uF 16V C320 MUST BE PLACED NEAR PVCC PIN
16V
16V
16V AZ1117H-1.2TRE1 $0.23
VCC PVCC +1.26V_MEMC
IN OUT 2 7
3 $0.05 2 C830
180 mA 10uF L809
1 ITH SW
C801 C810 3 6 6.3V
ADJ/GND C884
100uF C805 100uF 0.1uF R829 2.2uH
16V 0.1uF 16V 16V
16V 18K GND PGND
4 5
C819 R834
C817 10K
10uF 0.1uF
C828 1% C831 C833
6.3V 16V 0.1uF 22uF
330pF R1 16V 16V
50V

S6 core 1.26 volt R835

17.4K
1%
+5V_ST
465 mA @85% efficiency R2

+3.3V

BLM18PG121SN1D
L812 Replaced Part R831 MAX 3A +1.8V_MEMC for DDR
OPT 1/16W
10K +1.26V_VDDC
R830

10K C891 415 mA @85% efficiency

1/16W Close to IC 0.47uF
Vout=0.8*(1+R1/R2) R825 25V
400 mA
Close to IC 22K 1%
IC805
R824 MP2212DN
22K +3.3V_MEMC +1.8V_FRC_DDR
R1 $0.07
1%
4.9A 0.0150OHM 34MHZ IC807
FB EN/SYNC 1600 mA SC4215ISTRT
1 8 Vout=0.8*(1+R1/R2)
R827
75K L813
R2

1/10W
1/8W GND SW_2 3.6uH

R838
1% 2 7 NC_1 GND R1/R2 : 27K / 20K => Vout=1.88

12K
$0.24 1 8 R1

1%
R1/R2 : 15K / 12K => Vout=1.80
DEVELOPE NR8040T3R6N
OPT R836
$0.195 R1/R2 : 12K / 9.1K => Vout=1.85
IN SW_1 EN ADJ R1/R2 : 18K / 13K => Vout=1.90
Placed on SMD-TOP 3 6 C843 C849 10K
C856 2 7
22uF 22uF 0.1uF
10V 10V
BS VCC VIN VO
C838 C837 4 5 C836 3 6
C IN 22uF 22uF 0.1uF
OPT 50V Placed on SMD-TOP
NC_2 NC_3 C854 C855

1%
1/10W

9.1K
R862 C846 C851 4 5 100uF 0.1uF

R840
0 100uF 0.1uF R2 16V 16V
R861
R826 16V 16V 1uF
10V
10 C840
1/10W 1uF
1% 6.3V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX57644502 2009.05.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER 8 12
POWER

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 SPI FLASH +3.3V_MEMC

MEMC_RXE4+
MEMC_RXE4-
MEMC_RXE3+
MEMC_RXE3-
MEMC_RXEC+
MEMC_RXEC-
MEMC_RXE2+
MEMC_RXE2-
MEMC_RXE1+
MEMC_RXE1-
MEMC_RXE0+
MEMC_RXE0-

MEMC_RXO4+
MEMC_RXO4-
MEMC_RXO3+
MEMC_RXO3-
MEMC_RXOC+
MEMC_RXOC-
MEMC_RXO2+
MEMC_RXO2-
MEMC_RXO1+
MEMC_RXO1-
MEMC_RXO0+
MEMC_RXO0-
PANEL_POWER

CB3216PA501E
0.1uF

IC902
C903
R927

10K

W25X20AVSNIG

L907
M_XTALO
M_XTALI
R925 56 CS
1 8
VCC R928 R929
M_SPI_CZ
R926 56 DO
2 7
HOLD 100 100
M_SPI_DO
WP CLK R947 56 R930 R931
3 6
WP_FLASH_MEMC M_SPI_CK

URSA_A0P
URSA_A0M
URSA_A1P
URSA_A1M
URSA_A2P
URSA_A2M
URSA_ACKP
URSA_ACKM
URSA_A3P
URSA_A3M
URSA_A4P
URSA_A4M

URSA_B0P
URSA_B0M
URSA_B1P
URSA_B1M
GND
4 5
DIO R948 56 100 100 OPT
M_SPI_DI C951 C952 C953
R935 R936 +3.3V_MEMC 10uF
16V 1000pF 0.1uF
100 100
+3.3V_MEMC +3.3V_MEMC_AVDD R945 R946
100 100 BLM18PG121SN1D
R938 R939 P900

L905 TF05-51S

BLM18PG121SN1D 100 100 +3.3V_MEMC_AVDD

0.1uF
+1.26V_MEMC

C906
C904

1uF
1

Placed on SMD-TOP R942 R943 2

L904 3
100 100

10V
10V
4

0.1uF
22uF

C901
C956 0.1uF
10uF

C908
5
16V

C939
6

10uF
10uF
7

0.1uF
8

C937
C914
C912

10
URSA_B4M

AVDD_LVDS_1

AVDD_LVDS_2
11

R954 C907 10uF +3.3V_MEMC URSA_B4P 12

GPIO[25]

AVDD_PLL
URSA_B3M 13

GPIO_13
GPIO_14

GPIO_12
820 C905 URSA_B3P

GPIO_2
GPIO_1

GPIO_9
GPIO_8

LVACKP
LVACKM

GPIO_6
GPIO_4
14

RECKP
RECKN

GND_6

ROCKP
ROCKN

GND_5

GND_2

LVA0P
LVA0M
LVA1P
LVA1M
LVA2P
LVA2M

LVA3P
LVA3M
LVA4P
LVA4M

LVB0P
LVB0M
LVB1P
LVB1M
RE4P
RE4N
RE3P
RE3N

RE2P
RE2N
RE1P
RE1N
RE0P
RE0N

RO4P
RO4N
RO3P
RO3N

RO2P
RO2N
RO1P
RO1N
RO0P
RO0N

XOUT

SDAM
SCLM

REXT
15

XIN
URSA_BCKM

4.7K

470

4.7K
16

+3.3V_MEMC 10uF 10V URSA_BCKP 17

18
URSA_B2M

R972 OPT
OPT

OPT
B1
A1
C1
C2
A2
B2
B3
A3
C3
C4
A4
B4
F11
H8
B5
A5
C5
C6
A6
B6
B7
A7
C7
C8
A8
B8
G11
H7
K15
K16
D4
D3
B14
A14
D5
D6
N7
E11
D13
D11
G8
F10

B9
A9
C9
C10
A10
B10
B11
A11
C11
C12
A12
B12
D9
D7
B13
A13
C13
C14

D12
19

R992 100 SDAS GPIO_5 URSA_B2P

R949 1K D8 20
MEMC_SDA URSA_B1M

R970
100 SCLS GPIO_7 21

R978
R993 D10 URSA_B1P
MEMC_SCL 22
GPIO[8] F1 E10 GPIO_11 URSA_B0M 23

GPIO[9] GPIO_10 URSA_B0P

C928 G1 E3 24

0.1uF GND_14 GPIO_3 25

+3.3V_MEMC K8 E1 [E1] D2
R950 1K 26

OPT VDDC_1 E5 D1 C15 LVB2P URSA_B2P URSA_A4M

GPIO12 GPIO14 [D1] 27

GPIO[10] LVB2M URSA_B2M 37"42"47"_OPC2 URSA_A4P 28

E2 B15
L908 URSA_A3M 29
URSAII LVDS TYPE GPIO[11] F2 A15 LVBCKP URSA_BCKP BLM18PG121SN1D URSA_A3P
LOW LOW GPIO[12] LVBCKM URSA_BCKM
30

VENUS (MST7329N) F3 A16

R941

31
OPC_OUT2
R940
OPT 1K

1K

GPIO[13] LVB3P URSA_B3P URSA_ACKM 32

G2 B16 L909 URSA_ACKP
OPT

URSAII MINI LVDS TYPE GPIO[22] LVB3M URSA_B3M BLM18PG121SN1D 33

LOW HIGH M4 C16
M+S NORMAL 42"(MST7327N) GPIO[23] LVB4P URSA_B4P OPC_EN 34

M5 D15 URSA_A2M 35
L910 URSA_A2P
GPIO[14] G3 D16 LVB4M URSA_B4M 36
URSAII MINI LVDS TYPE BLM18PG121SN1D URSA_A1M
R957

R956

HIGH LOW GPIO[15] AVDD_33_2 C949 37

M+S NORMAL 47"(MST7327N) E4 F9 OPC_OUT1 URSA_A1P 38

1K

1K

GPIO[16] F4 G10 GND_4 URSA_A0M 39

L911 URSA_A0P
URSAII MINI LVDS TYPE GPIO[17] G4 E15 LVC0P URSA_C0P 40
HIGH HIGH BLM18PG121SN1D
41
M+S GIP 37"(MST7327N) GPIO[18] H4 E16 LVC0M 0.1uF URSA_C0M
PWM_DIM 42
GPIO[19] J4 E14 LVC1P URSA_C1P 43

GPIO[20] K4 F14 LVC1M URSA_C1M 44

+3.3V_MEMC
45
L902 GPIO[21] L4 F16 LVC2P URSA_C2P
0 R955 46
/3D_FPGA_RESET

32"_OPC2_OFF
C929 VDDP_2 LVC2M URSA_C2M

OPT

OPT

OPT

OPT

OPT
0 R958

OPT

OPT

OPT
J6 F15 3D_SCL 47

0 OPT

0 OPT
10uF

C957
10uF
10V

0 R961

C958
GND_7 LVCCKP URSA_CCKP

C964

C963

C961

C960

C959
C962
48
BLM18PG121SN1D H9 G15 3D_SDA
49
0.1uF 0.1uF GND_15 LVCCKM URSA_CCKM 3D_POWER_EN

R937 0

0
K9 G16

0.1uF
0.1uF

0.1uF
0.1uF

0.1uF
50

0.1uF

0.1uF

0.1uF
+1.8V_FRC_DDR G14 LVC3P URSA_C3P

R971

R973

R979
51
C916

C917

URSA_DQ[0-31]

VDDC_2 F6 H14 LVC3M URSA_C3M 52

C926
URSA_DQ[20] MDATA[20] H1 H16 LVC4P URSA_C4P
Placed on SMD-TOP URSA_DQ[19] MDATA[19] H2 H15 LVC4M URSA_C4M
J15 LVD0P URSA_D0P

IC900
22uF
16V

URSA_DQ[17] MDATA[17] H3 J16 LVD0M URSA_D0M

URSA_DQ[22] MDATA[22] J1 J14 LVD1P URSA_D1P
K14 LVD1M URSA_D1M
URSA_DQ[27] MDATA[27] J2
C909

URSA_DQ[28] MDATA[28] J3

URSA_DQ[25]
C919 0.1uF
MDATA[25] K1
LGE7329A G9
L14
GND_3
LVD2P
C950

URSA_D2P
URSA_DQ[30] MDATA[30] K2 L15 LVD2M 0.1uF URSA_D2M
AVDD_DDR_2 K6 L16 LVDCKP URSA_DCKP
DQM[3] K3 M16 LVDCKM URSA_DCKM
URSA_DQM3
DQM[2] L1 F8 AVDD_33_1
URSA_DQM2
C920 0.1uF GND_10 J8 M15 LVD3P URSA_D3P P901
TF05-41S
DQS[2] L2 M14 LVD3M URSA_D3M
URSA_DQS2
DQSB[2] L3 N16 LVD4P URSA_D4P 1
URSA_DQSB2
AVDD_DDR_4 L6 N15 LVD4M C947 URSA_D4M 2
URSA_D4M 3
VDDP_3 L8 URSA_D4P 4
GND_8 H10 H6 VDDC_5 URSA_D3M 5

DQS[3] GPIO[24] 0.1uF +3.3V_MEMC URSA_D3P

C927 0.1uF M1 N6 6
URSA_DQS3 7
DQSB[3] M2 E12 GPIO[7]
URSA_DQSB3 URSA_DCKM 8
AVDD_DDR_5 L7 D14 GPIO[6] URSA_DCKP 9

URSA_DQ[31] MDATA[31] M3 F12 GPIO[5] 10

URSA_D2M 11
URSA_DQ[24] MDATA[24] N1 E13 GPIO[4]
URSA_D2P 12
C921 0.1uF GND_11 J9 F13 GPIO[3] URSA_D1M

R959
13

R963
1K

1K
URSA_DQ[26] MDATA[26] GPIO[2] URSA_D1P 14
N2 G13
URSA_D0M 15
URSA_DQ[29] MDATA[29] N3 H13 GPIO[1]
URSA_D0P 16
AVDD_DDR_6 L10 J13 GPIO[0] 17

URSA_DQ[23] MDATA[23] P1 K12 PWM0 18

URSA_C4M 19
URSA_DQ[16] MDATA[16] R1 N13 [N13] L12 PWM1
URSA_C4P 20
URSA_DQ[18] MDATA[18] T1 L9 K13 CSZ URSA_C3M
+3.3V_MEMC [L9] N12 [N12] M_SPI_CZ 21

URSA_DQ[21] MDATA[21] SDO URSA_C3P 22

T2 N5 [N5] M12 M_SPI_DO

R960

R964
OPT

OPT
23
MCLK[0] SDI

1K

1K
URSA_MCLK R2 N4 [N4] M13 M_SPI_DI URSA_CCKM 24
MCLKZ[0] P2 L13 SCK URSA_CCKP
BLM18PG121SN1D URSA_MCLKZ M_SPI_CK 25
C925 0.1uF GND_1 GPIO[30] 26
G7 N14
URSA_C2M 27
AVDD_MEMPLL GPIO[29]
L903 URSA_C2P 28
MVREF GPIO[28] URSA_C1M 29

ODT URSA_C1P
C913

10uF

30
URSA_ODT OPT URSA_C0M
J10

L11

K10

T10
K11
R10
P10

T11
R11
J11
P11
T12

R12
P12

H11

T13
R13

P13
T14

R14
P14

T15
R15
P15
T16
R16
P16

N10
N11
M11
31
0.1uF C922 URSA_C0P
T3
R3
P3
T4
R4

P4
T5
R5
P5
T6
R6
P6
T7

R7
P7
T8
R8
P8
N8

F7
T9
R9
K7
P9

N9

G6
GND_9 J7

R933 32

0 33
PANEL_POWER
WP_FLASH_MEMC
RASZ
CASZ
MADR[0]
MADR[2]
MADR[4]
GND_12
MADR[6]
MADR[8]
MADR[11]
WEZ
BADR[1]
BADR[0]
MADR[1]
MADR[10]
AVDD_DDR_7
MADR[5]
MADR[9]
MADR[12]
MADR[7]
MADR[3]
MCLKE
GND_16
VDDC_3
MDATA[4]
MDATA[3]
GND_13
MDATA[1]
MDATA[6]
AVDD_DDR_3
MDATA[11]
MDATA[12]

MDATA[9]
MDATA[14]
AVDD_DDR_1
DQM[1]
DQM[0]

DQS[0]
DQSB[0]

VDDP_1

DQS[1]
DQSB[1]

MDATA[15]
MDATA[8]

MDATA[10]
MDATA[13]

MDATA[7]
MDATA[0]
MDATA[2]
MDATA[5]
MCLK[1]
MCLKZ[1]
GPIO[26]
GPIO[27]
GND_17
RESET

VDDC_4
34
0.1uF
GPIO8 PWM1 PWM0 35

36

C923 L901 37

I2C HIGH LOW HIGH CB3216PA501E 38

39

40

0.1uF
+3.3V_MEMC
0.1uF

0.1uF

C944
41
C938

EEPROM HIGH HIGH LOW

C965 C966 C967 42

10uF 50V 16V

0.1uF

16V 1000pF 0.1uF

C941

XTAL SPI HIGH HIGH HIGH

R934 1M OPT

R994
C945

10K
C932

C933

C934

C935

C936
R951
10K

M_XTALO M_XTALI
X900 MEMC_RESET
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
R953

C900 12MHz C902

0
URSA_A[11]

URSA_A[10]

URSA_A[12]
URSA_A[0]
URSA_A[2]
URSA_A[4]

URSA_A[6]
URSA_A[8]

URSA_A[1]

URSA_A[5]
URSA_A[9]

URSA_A[7]
URSA_A[3]

15pF 15pF
CONTACT TO MODULE FOR EMI
0.1uF

C918
R952

C924
1uF
10K

M1 OPT
MDS61887706
URSA_DQ[11]
URSA_DQ[12]

URSA_DQ[14]

URSA_DQ[15]

URSA_DQ[10]
URSA_DQ[13]
URSA_DQ[4]
URSA_DQ[3]

URSA_DQ[1]
URSA_DQ[6]

URSA_DQ[9]

URSA_DQ[8]

URSA_DQ[7]
URSA_DQ[0]
URSA_DQ[2]
URSA_DQ[5]

M2 OPT
MDS61887706

URSA_DQ[0-31] OPT
M3
MDS61887706

M4 37"42"47"_EMI
URSA_RASZ
URSA_CASZ

URSA_WEZ
URSA_BA1
URSA_BA0

URSA_MCLKE

URSA_A[0-12]

URSA_DQM1
URSA_DQM0

URSA_DQS0
URSA_DQSB0

URSA_DQS1
URSA_DQSB1

URSA_MCLK1
URSA_MCLKZ1

MDS61887706

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX57644502 2009.05.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MST7329N(FRC) 9 12

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 DDR2 1.8V By CAP - Place these Caps near Memory

+1.8V_FRC_DDR +1.8V_FRC_DDR +1.8V_FRC_DDR +1.8V_FRC_DDR

10V

10V

C1024

C1026

C1028

C1029

C1031

C1033

C1034

C1035

C1036

C1037

C1038

C1039

C1040
C1025

C1027

C1041
C1013

C1023

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
C1002

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
10uF
C1003

C1004

C1005

C1006

C1007

C1009

C1011

C1012

C1014

C1015

C1016

C1017

C1018

C1019

C1020

C1022

0.1uF

0.1uF
C1001

10uF
10uF

10uF
10uF

+1.8V_FRC_DDR +1.8V_FRC_DDR

R1001 R1037
1K

URSA_A[0-12]
1K
1% 1%

010:AL20;009:AB4 URSA_DQ[0-31] URSA_DQ[0-31] 010:E20;009:AB4

C1010 R1002 R1038

1K C1030
AR1000 IC1000 0.1uF 1K
1% 0.1uF IC1001 AR1004
URSA_DQ[27] DDR_DQ[27] 1% DDR_DQ[15] URSA_DQ[15]
URSA_DQ[28] DDR_DQ[28]
H5PS5162FFR-S6C H5PS5162FFR-S6C DDR_DQ[8] 56 URSA_DQ[8]
URSA_DQ[25] 56 DDR_DQ[25] DDR_DQ[10] URSA_DQ[10]
URSA_DQ[30] DDR_DQ[30] DDR_DQ[13] URSA_DQ[13]
DDR_DQ[16] DQ0 G8 J2 VREF VREF J2 G8 DQ0 DDR_DQ[0]
AR1001 DDR_DQ[17] DQ1 G2 G2 DQ1 DDR_DQ[1] AR1005
URSA_DQ[22] DDR_DQ[22] DDR_DQ[7] URSA_DQ[7]
DDR_DQ[18] DQ2 URSA_A[3] AR1010 DDRA_A[3] DQ2 DDR_DQ[2]
URSA_DQ[17] DDR_DQ[17] H7 A0 DDRB_A[0] DDRA_A[0] A0 H7 DDR_DQ[0] URSA_DQ[0]
M8 DDRB_A[10] AR1013 URSA_A[10] URSA_A[1] 22 DDRA_A[1] M8 56
DDR_DQ[19] DQ3 H3 H3 DQ3 DDR_DQ[3]
DDR_DQ[16-31]

URSA_DQ[19] 56 DDR_DQ[19] A1 DDRB_A[1] DDRA_A[1] A1 DDR_DQ[2] URSA_DQ[2]

DDR_DQ[0-15]
DDR_DQ[20] DQ4 M3 DDRB_A[1] 22 URSA_A[1] URSA_A[10] DDRA_A[10] M3 DQ4 DDR_DQ[4]
H1 H1
DDRB_A[0-12]

URSA_DQ[20] DDR_DQ[20] M7 A2 DDRB_A[2] DDRA_A[2] A2 M7 DDR_DQ[5] URSA_DQ[5]

DDRA_A[0-12]
DDR_DQ[21] DQ5 H9 DDRB_A[3] URSA_A[3] H9 DQ5 DDR_DQ[5]
N2 A3 DDRB_A[3] DDRA_A[3] A3 N2
AR1002 DDR_DQ[22] DQ6 DDRB_A[9] URSA_A[9] URSA_A[9] DDRA_A[9] DQ6 DDR_DQ[6] AR1006
URSA_DQ[31] DDR_DQ[31] F1 A4 DDRB_A[4] DDRA_A[4] A4 F1 DDR_DQ[11] URSA_DQ[11]
DDR_DQ[23] DQ7 N8 DDRB_A[12] AR1014 URSA_A[12] URSA_A[12] AR1011 DDRA_A[12] N8 DQ7 DDR_DQ[7]
URSA_DQ[24] DDR_DQ[24] F9 A5 DDRB_A[5] DDRA_A[5] A5 F9 DDR_DQ[12] 56 URSA_DQ[12]
DDR_DQ[24] DQ8 N3 DDRB_A[7] 22 URSA_A[7] URSA_A[7] 22 DDRA_A[7] N3 DQ8 DDR_DQ[8]
URSA_DQ[26] 56 DDR_DQ[26] C8 A6 DDRB_A[6] DDRA_A[6] A6 C8 DDR_DQ[9] URSA_DQ[9]
DDR_DQ[25] DQ9 N7 DDRB_A[5] URSA_A[5] URSA_A[5] DDRA_A[5] N7 DQ9 DDR_DQ[9]
URSA_DQ[29] DDR_DQ[29] C2 A7 DDRB_A[7] DDRA_A[7] A7 C2 DDR_DQ[14] URSA_DQ[14]
DDR_DQ[26] DQ10 P2 DDRB_A[0] URSA_A[0] URSA_A[2] DDRA_A[2] P2 DQ10 DDR_DQ[10]
D7 A8 DDRB_A[8] DDRA_A[8] A8 D7
AR1003 DDR_DQ[27] DQ11 P8 DDRB_A[2] AR1015 URSA_A[2] URSA_A[0] AR1012 DDRA_A[0] P8 DQ11 DDR_DQ[11] AR1007
URSA_DQ[23] DDR_DQ[23] D3 A9 DDRB_A[9] DDRA_A[9] A9 D3 DDR_DQ[6] URSA_DQ[6]
DDR_DQ[28] DQ12 P3 DDRB_A[4] 22 URSA_A[4] URSA_A[6] 22 DDRA_A[6] P3 DQ12 DDR_DQ[12]
URSA_DQ[16] DDR_DQ[16] D1 A10/AP DDRB_A[10] DDRA_A[10] A10/AP D1 DDR_DQ[1] 56 URSA_DQ[1]
DDR_DQ[29] DQ13 M2 DDRB_A[6] URSA_A[6] URSA_A[4] DDRA_A[4] M2 DQ13 DDR_DQ[13]
URSA_DQ[18] 56 DDR_DQ[18] D9 A11 DDRB_A[11] DDRA_A[11] A11 D9 DDR_DQ[3] URSA_DQ[3]
DDR_DQ[30] DQ14 P7 AR1017 AR1019 P7 DQ14 DDR_DQ[14]
URSA_DQ[21] DDR_DQ[21] B1 A12 DDRB_A[12] B_URSA_RASZ URSA_RASZ URSA_RASZ A_URSA_RASZ DDRA_A[12] A12 B1 DDR_DQ[4] URSA_DQ[4]
DDR_DQ[31] DQ15 R2 R2 DQ15 DDR_DQ[15]
B9 B_URSA_CASZ URSA_CASZ URSA_CASZ A_URSA_CASZ B9
DDRB_A[11] URSA_A[11] URSA_A[8] 22 DDRA_A[8]
+1.8V_FRC_DDR L2 BA0 DDRB_A[8] URSA_A[8] URSA_A[11] DDRA_A[11] BA0 L2
B_URSA_BA0 A_URSA_BA0 +1.8V_FRC_DDR
L3 BA1 22 BA1 L3
VDD5 B_URSA_BA1 A_URSA_BA1 VDD5
A1 R1005 22 R1024 22 A1
VDD4 URSA_MCLK 009:J11 009:AB4 URSA_MCLK1 VDD4
R1000

E1 E1

R1039
OPT

OPT
150

150
VDD3 J9 J8 CK CK J8 J9 VDD3
VDD2 M9 K8 CK R1006 22 R1025 22 CK K8 M9 VDD2
URSA_MCLKZ 009:J10 009:AB4 URSA_MCLKZ1
VDD1 R1 K2 CKE CKE K2 R1 VDD1
B_URSA_MCLKE 010:T10 010:V9 A_URSA_MCLKE

K9 ODT R1008 22 R1027 22 ODT K9

URSA_ODT 010:Y14;009:J10 010:Q14;009:J10 URSA_ODT
VDDQ10 A9 L8 CS CS L8 A9 VDDQ10
VDDQ9 C1 K7 RAS RAS K7 C1 VDDQ9
B_URSA_RASZ 010:R16 010:X16 A_URSA_RASZ
VDDQ8 C3 L7 CAS CAS L7 C3 VDDQ8
B_URSA_CASZ 010:R16 010:X16 A_URSA_CASZ
VDDQ7 C7 K3 WE WE K3 C7 VDDQ7
B_URSA_WEZ 010:T10 010:V8 A_URSA_WEZ
VDDQ6 C9 C9 VDDQ6
VDDQ5 E9 E9 VDDQ5
F7 LDQS R1012 56 R1031 56 LDQS F7
VDDQ4 URSA_DQS2 009:J14 009:X4 URSA_DQS0 VDDQ4
G1 UDQS R1013 56 R1032 56 UDQS G1
VDDQ3 B7 URSA_DQS3 URSA_DQS1 B7 VDDQ3
G3 009:J13 009:Y4 G3
VDDQ2 G7 G7 VDDQ2
VDDQ1 G9 F3 LDM R1014 56 R1033 56 LDM F3 G9 VDDQ1
URSA_DQM2 009:J15 009:X4 URSA_DQM0
B3 UDM R1015 56 R1034 56 UDM B3
URSA_DQM3 009:J15 009:W4 URSA_DQM1

VSS5 A3 E8 LDQS R1016 56 R1035 56 LDQS E8 A3 VSS5

URSA_DQSB2 009:J14 009:X4 URSA_DQSB0
VSS4 E3 A8 UDQS R1017 56 R1036 56 UDQS A8 E3 VSS4
URSA_DQSB3 009:J13 009:Y4 URSA_DQSB1
VSS3 J3 J3 VSS3
VSS2 N1 N1 VSS2
L1 NC4 AR1016 NC4 L1
VSS1 P9 P9 VSS1
NC5 B_URSA_BA0 URSA_BA0 010:T9;009:S4 NC5
R3 R3
NC6 B_URSA_BA1 URSA_BA1 010:T9;009:R4 NC6
R7 R7
010:Q14 B_URSA_MCLKE URSA_MCLKE 010:T9;009:T4
VSSQ10 010:Q13 B_URSA_WEZ URSA_WEZ 010:T8;009:R4 VSSQ10
B2 NC1 22 NC1 B2
VSSQ9 A2 A2 VSSQ9
B8 NC2 AR1018 NC2 B8
VSSQ8 E2 E2 VSSQ8
A7 NC3 010:V10;009:S4 URSA_BA0 A_URSA_BA0 010:AA15 NC3 A7
VSSQ7 R8 R8 VSSQ7
D2 +1.8V_FRC_DDR 010:V10;009:R4 URSA_BA1 A_URSA_BA1 010:AA15 +1.8V_FRC_DDR D2
VSSQ6 D8 D8 VSSQ6
010:V10;009:T4 URSA_MCLKE A_URSA_MCLKE 010:Z14
VSSQ5 E7 VSSDL VSSDL E7 VSSQ5
J7 010:V10;009:R4 URSA_WEZ A_URSA_WEZ 010:Y13 J7
VSSQ4 22 VSSQ4
F2 F2
VSSQ3 F8 F8 VSSQ3
VSSQ2 H2 H2 VSSQ2
VSSQ1 H8 J1 VDDL VDDL J1 H8 VSSQ1

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX57644502 2009.05.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MST7327N DDR2 10 12

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 +3.3V

R1124
4.7K

SCART1_DET +3.3V
R1126 +12V
1K
D1110 C1113 L1104 +12V
5.6V 0.1uF BLM18PG121SN1D

4.7K
OPT 16V

R1122
L1109
BLM18PG121SN1D
E C1143 C1144 C1145
ISA1530AC1 R1140 SCART2_DET
470 10uF 0.1uF 0.1uF
Q1119 50V R1159
35V 50V 1K C1104 C1139 C1141
SC1_CVBS_IN @optio B C1105 0.1uF
23 10uF 0.1uF
R1117 C1108 0.1uF 35V 50V 50V
C1106 0 C
R1109 220pF R1174 16V
23 47pF
75 50V 47K E
50V R1162
OPT C1142 @optio 470
23
22
D1101 Q1120 C 47uF
R1182 R1133 ISA1530AC1
22 16V Q1109 B
30V GND 2SC3052 B 0
21 23 SC2_CVBS_IN
FE_VSCART_OUT C
21 OPT 0 C1125
C1119 R1166
20 R1113 R1139 220pF 47K
20 390 E 22 47pF Q1111
22 D1112 75 50V C1109
R1175 50V OPT
19 R1107 15K 30V 2SC3052 C 47uF
19 21 16V
D1106 75 C1107 R1138 21 OPT
18 B
D1102 30V 100uF 120 20 DTV/MNT_VOUT
18
30V OPT 16V 20
17 R1136 R1131
17 OPT 22 19 75 390 E
R1114 19 R1167
16 SC1_FB 15K
16 18
18 D1115 C1122
15 SC1_R R1161
17 30V 100uF 120
15 D1103 R1106 17 16V
14 30V R1104 75 OPT
14 16
OPT 75 16
13
13 15
15
12 R1105 R1134
12 0 14 0
14 REC_8
11 SC1_G
11 D1104 13
R1101 13 R1125
30V
. 10 75 62K
OPT 12
12 SC2_ID
. 9
11 R1132
11 11K
SC1_ID 2:E16
SC_ID 8 R1118 . 10
D1111 62K R1123
B 7 SC1_B
30V 11K . 9 R1137
D1109 R1102 75
6 OPT
LIN 30V 75 SC2_ID 8
OPT D1118
L1105
GND 5 30V R1121
. 7 120-ohm
OPT 10K
GND 4 SC2_L_IN
L_IN 6

R1127
L_OUT 3 C1120

12K
R1110 GND 5 D1116R1116 C1123
10K 5.6V OPT 330pF
R_IN 2 SC1_L_IN 470K 50V
GND 4 OPT
R1112

L1101 C1103
R_OUT 1 120-ohm
12K

R1103 330pF
D1108
470K C1101 L_OUT 3
5.6V 50V L1106
OPT
OPT R_IN 2 120-ohm R1128
10K
JK1100 R_OUT 1 SC2_R_IN

R1129
12K
R1108 C1121 C1124
10K D1117 R1115 OPT 330pF
SC1_R_IN 2:S14 5.6V
L1100
JK1101 470K 50V
R1111

C1102 OPT
D1107 120-ohm
12K

R1100 C1100 330pF

5.6V OPT L1108
OPT 470K 50V BLM18PG121SN1D R1164
0
DTV/MNT_L_OUT
C1112
L1102 1000pF
BLM18PG121SN1D R1135 D1114 50V C1117
0 5.6V 4700pF
TV_L_OUT 002:P7 OPT
C1110
1000pF C1116
D1105 50V 4700pF L1107
5.6V BLM18PG121SN1D R1163
OPT 0
DTV/MNT_R_OUT
L1103
BLM18PG121SN1D R1160
0 C1114
TV_R_OUT 002:P7 C1118
1000pF
4700pF
D1113 50V
D1100 C1111 C1115 5.6V
5.6V 1000pF 4700pF
OPT
OPT 50V

IC1103
LM324D
R1191 R1196
2.2K 1 14 2.2K
1 14
TV_L_OUT
R1194
DTV/MNT_R_OUT
CONTROL
R1193

470K

OPT
R1145 R1155
470K

P1304
OPT

C1133 2 13 C1135
10uF 33K 33K 10uF
2 13 12507WS-12L
IR & LED
R1147

R1153

[SCART2 PIN 8] 16V 16V R1321

10K

10K

C1127 100
+12V 33pF 3 12 C1129 33pF SCL_SUB/AMP ZD1300
R1143 3 12 CDS3C05HDMI1
R1157 +3.3V_ST
5.6K 5.6V
+12V SCART1_Lout SCART2_Rout 1 SCL
4 11 5.6K
4 11 R1322
100
C1126
R1144 R1158 SDA_SUB/AMP 2 SDA
0.1uF 5.6K 5 10 5.6K
50V SCART1_Rout 5 10 SCART2_Lout R1319 ZD1301
4.7K R1320 CDS3C05HDMI1
R1184 4.7K 5.6V 3 GND
R1146 R1156
15K R1185 R1187 C 33K 6 9 33K R1318 L1301
6 9 BLM18PG121SN1D
R1148

R1154

0 0 100
R1176 B Q1118 KEY1 KEY1
10K

10K

R1178 4
2SC3052 R1130 33pF ZD1304
2K 10K C1128 33pF 7 8
R1186 7 8 R1317 L1303 5.6V
OPT E R1190 R1197 100
12K R1188 2.2K 2.2K BLM18PG121SN1D AMOTECH
51K TV_R_OUT DTV/MNT_L_OUT
KEY2 5 KEY2
OPT
R1195
R1192

C
470K

C1134
OPT
470K

C1136
OPT

10uF ZD1302
B Q1117 10uF C1305 C1307 5.6V 6 5V_ST
1:AJ19 SC_RE1 16V 0.1uF 0.1uF
2SC3052 16V AMOTECH
R1177 R1180 L1313
1K E +5V_ST
BLM18PG121SN1D
560 7 GND
OPT
C
R1325 4.7K
B Q1116 8 WARM_ST
1:AJ19 SC_RE2 C1314 C1315
2SC3052 REC_8 AI8 TV_L_OUT +3.3V +3.3V_ST 0.1uF 1000pF
R1181 16V 50V R1305 WARM_LED_ON
R1179 1K E 100 IR
IR 9
680 Q1126 R1149
R1141 C1302
OPT 2SC3052 R1119 R1120 C1309
2K 10K
10K 10K
100pF ZD1303 0.1uF 10 GND
50V 5.6V
D1120 +5V_ST AMOTECH
Q1130 ENKMC2838-T112
RT1P141C-T112
A1 11 3.3V
SB_MUTE
TV_R_OUT C +3.3V L1314
+5V_ST
R1301 BLM18PG121SN1D
A2
3 1 SCART1_MUTE 10K 12 PWR_ON
R1151 OPT
C1131 22 R1300
Q1127 2 IR_OUT R1303
2K 0.1uF OPT 10K C1311 13
C1310
2SC3052 OPT 1000pF
0.1uF
Q1300 C 10KR1302 16V 50V
2SC3052 B
OPT E OPT
C 47K R1304
DTV/MNT_L_OUT B R1323 100
Q1301 E OPT
2SC3052 LED_ON

R1306
Q1128 R1150 OPT

10K
2SC3052
2K
D1119
RT1P141C-T112 ENKMC2838-T112
Q1131 A1
SB_MUTE
DTV/MNT_R_OUT C
A2
3 1 SCART2_MUTE
R1152 C1132
Q1129
2SC3052
2K
2
0.1uF Zener Diode is
close to wafer
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX57644502 2009.05.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART 11 12
11_SCART

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 +5V_GENERAL

L1204
MLB-201209-0120P-N2

R1229
10
Analog Tuner : 0x86

R1231
10K
TU1200 Q1202
TDFW-G235D E ISA1530AC1
R1230
C1200
0.1uF
Tuner PLL : 0xC2

2.2K
16V

ANT[5V] B
1 C
+5V_GENERAL C R1232
BB[CTR] Q1203 B 10K
2 L1201 FE_BOOSTER_CTL
MLB-201209-0120P-N2 2SC3052
GND_1
3 C1222 E
+B[5V] 0.01uF
4 C1207 C1208 C1209 25V
NC_1 100pF 0.1uF 68uF OPTION : RF AGC USE ONLY FOR SECAM
5 50V 16V 10V
RF_AGC OPT
6
TP[VT] C1212
7 C1210 47uF
NC_2 0.1uF 16V OPT
8 R1207 47 16V
OPT FE_TUNER_SDA OPT
GND_2 C
9 R1209 +5V_GENERAL
C1205
Q1200 B 10K
SDA_T 47pF FE_AGC_SPEED_CTL
10 50V 2SC3052
SCL_T OPT OPT
11 OPT R1208 47 E
FE_TUNER_SCL R1240 R1241
AIF_1 C1206 200 200
12 47pF
NC_3 50V
13
GND FE_VMAIN
14 E
VIDEO R1205 0 0
15 R1238
NC_4 R1239 B Q1205
16 1K
C ISA1530AC1
SIF C1216 OPT
TUNER 17
R1221
Digital Tuner : 0x1E

SDA 100pF 50V 33

18 FE_DEMOD_SDA
SCL
19 FE_DEMOD_SCL +5V_GENERAL
RST R1222
20 C1217 C1218 33
3.3V 47pF 47pF R1227
21 C1214 50V 470 R1228
0.1uF 50V
82
1.2V 16V FE_SIF
22 E
+3.3V_TUNER
ERR
23 C1215
0.1uF
MCL R1210 47 FE_TS_CLK B ISA1530AC1
24 16V
R1226 Q1201
DVB-T/C : 1.2V(MICRONAS demod)

R1225 C
D7 R1211 47 FE_TS_DATA[7] R1224 100K 4.7K
25
100
DVB-T : 1.8V(INTEL demod)

D6 R1212 47 FE_TS_DATA[6] /FE_RESET

26 C1219
D5 R1213 47 FE_TS_DATA[5] 0.1uF
27 16V
D4 R1214 47 FE_TS_DATA[4]
28
D3 R1215 47 FE_TS_DATA[3]
29
D2 R1216 47 FE_TS_DATA[2]
30
D1 R1217 47 FE_TS_DATA[1]
31
D0 R1218 47 FE_TS_DATA[0]
32
VAL R1219 47 FE_TS_VAL FE_TS_VAL
33
SYNC R1220 47 FE_TS_SYN
34
FE_TS_DATA[0-7],FE_TS_CLK,FE_TS_VAL,FE_TS_SYN DVB-CI DETECT
35 L1202
+3.3V_TUNER
MLB-201209-0120P-N2 +3.3V_TUNER

SHIELD C1221
0.1uF
16V IC1201
NL17SZ08DFT2G

+1.2V_TUNER FE_TS_VAL 1 5

FE_TS_ERR 2 C1227
0.1uF
3 4 16V
C1220
0.1uF GND R1245
16V FE_TS_VAL_ERR
47
R1223 0
FE_TS_ERR

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX57644502 2009.05.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TUNER 12 12
12_TUNER

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 P100 3V3
TF05-51S

P101
1 TF05-41S
+12V_FORMATTER
R100 R101
2
IC100 R102 22
4.7K 4.7K
EP3C55F484C8N 3 READY READY
3D_POWER_EN 1
R103 0
4 SDA 2
A11 Y2 R104 22
RD4+ 5 SCL
NC_1 NC_127 3
A12 Y1 RD4- IC100 R105 22 C109 C110 C111
NC_2 NC_126 6 10uF 0.1uF 100pF
A20 W2 EP3C55F484C8N /3D_FPGA_RESET 4 16V 50V 50V
IC100 RE4- AA1
NC_3 NC_125
W1 7
R106 22 C104 C105
EP3C55F484C8N NC_4 NC_124 LVDS_SELECT 10pF 10pF 5
RE4+ AA2 V7 R107 22
NC_5 NC_123 8 50V 50V
AA11 V6 TP[5] D13 M20 TCLK2- PWM_DIM READY READY 6
NC_6 NC_122 LVDS_OUT_R1[9] LVDS_OUT_R2[9] R108 22
AA12 V4 A10 M21 TC2+ 9
RD1+ N2 B2 NC_7 NC_121 LVDS_OUT_R1[8] LVDS_OUT_R2[8] OPC_OUT1 7
RXA0 RXB0 AA20 V3 B10 M22 TC2- R109 22
RD1- N1 B1 NC_8 NC_120 LVDS_OUT_R1[7] LVDS_OUT_R2[7] 10
RXA0(N) RXB0(N) AB5 U19 TA4+ D10 L21 TB2+ OPC_ENABLE 8
RE1+ P2 C2 NC_9 NC_119 LVDS_OUT_R1[6] LVDS_OUT_R2[6] R110 22
RXA1 RXB1 AB6 U13 E10 L22 TB2- 11
RE1- P1 C1 NC_10 NC_118 LVDS_OUT_R1[5] LVDS_OUT_R2[5] OPC_OUT2 9
RXA1(N) RXB1(N) AB11 U8 TP[3] A9 K17 TA2-
RA4+ R2 F2 RC2+ NC_11 NC_117 LVDS_OUT_R1[4] LVDS_OUT_R2[4] 12
RXA2 RXB2 AB12 U7 TP[4] B9 K18 TA2+ R155 RA2+ 10
RA4- R1 F1 RC2- NC_12 NC_116 LVDS_OUT_R1[3] LVDS_OUT_R2[3] 100 R168 RA3+
RXA2(N) RXB2(N) B4 T22 A8 K21 TE1+ 13 100
RB4+ U2 H2 NC_13 NC_115 LVDS_OUT_R1[2] LVDS_OUT_R2[2] RA2- 11
RXA3 RXB3 B11 T21 B8 K22 TE1- RA3-
RB4- U1 H1 NC_14 NC_114 LVDS_OUT_R1[1] LVDS_OUT_R2[1] 14
RXA3(N) RXB3(N) B12 T14 C8 J22 TC1- R156 RB2+ 12
RC4+ V2 J2 RA1+ NC_15 NC_113 LVDS_OUT_R1[0] LVDS_OUT_R2[0] 100 R169 RB3+
RXA4 RXB4 B21 T11 TP[1] 15 100
RC4- V1 J1 RA1- NC_16 NC_112 RB2- 13
RXA4(N) RXB4(N) B22 T10 TP[2] A16 P17 TC3+ RB3-
RCLK4+ T2 G2 RCLK1+ NC_17 NC_111 LVDS_OUT_G1[9] LVDS_OUT_G2[9] 16
RXACLK RXBCLK C3 T5 RE3+ B16 P21 TB3+ R157 RC2+ 14
RCLK4- T1 G1 RCLK1- NC_18 NC_110 LVDS_OUT_G1[8] LVDS_OUT_G2[8] 100 R170 RC3+
RXACLK(N) RXBCLK(N) C4 T4 A15 P22 TB3- 17 100
NC_19 NC_109 LVDS_OUT_G1[7] LVDS_OUT_G2[7] RC2- 15
C10 T3 B15 N18 TE2+ RC3-
NC_20 NC_108 LVDS_OUT_G1[6] LVDS_OUT_G2[6] 18
C15 R15 TP[0] D15 N19 TD2+ 16
NC_21 NC_107 LVDS_OUT_G1[5] LVDS_OUT_G2[5]
C20 R6 RE3- A14 N20 TD2- 19 RCLK2+ RCLK3-
NC_22 NC_106 LVDS_OUT_G1[4] LVDS_OUT_G2[4] RCLK2+ 17
C21 R5 B14 N21 TA3+ R158 RCLK3+ R171
NC_23 NC_105 LVDS_OUT_G1[3] LVDS_OUT_G2[3] 20 100 100
C22 R4 RD3+ A13 N22 TA3- RCLK2- 18
NC_24 NC_104 LVDS_OUT_G1[2] LVDS_OUT_G2[2] RCLK2- RCLK3- RCLK3+
D2 R3 RD3- B13 M16 21
NC_25 NC_103 LVDS_OUT_G1[1] LVDS_OUT_G2[1] 19
D6 P20 C13 M19 TCLK2+
NC_26 NC_102 LVDS_OUT_G1[0] LVDS_OUT_G2[0] 22
D17 P7 RA3- R159 RD2+ 20
NC_27 NC_101 100 R172 RD3+
D20 P6 C19 T17 23 100
NC_28 NC_100 LVDS_OUT_B1[9] LVDS_OUT_B2[9] RD2- 21
D21 P5 RB3+ D19 T18 RD3-
NC_29 NC_99 LVDS_OUT_B1[8] LVDS_OUT_B2[8] 24
D22 P4 RC3+ A18 T19 TE3+ R160 RE2+ 22
NC_30 NC_98 LVDS_OUT_B1[7] LVDS_OUT_B2[7] 100 R173 RE3+
E1 P3 RC3- B18 T20 TE3- 25 100
NC_31 NC_97 LVDS_OUT_B1[6] LVDS_OUT_B2[6] RE2- 23
E3 N17 TE2- C18 R17 TC3- RE3-
NC_32 NC_96 LVDS_OUT_B1[5] LVDS_OUT_B2[5] 26
E4 N16 D18 R18 TCLK3- R161 24
NC_33 NC_95 LVDS_OUT_B1[4] LVDS_OUT_B2[4] 22
E5 N7 RA3+ A17 R19 TCLK3+ 27
NC_34 NC_94 LVDS_OUT_B1[3] LVDS_OUT_B2[3] BIT_SELECT 25
E6 N6 RB3- B17 R20
NC_35 NC_93 LVDS_OUT_B1[2] LVDS_OUT_B2[2] 28
E7 N5 C17 R21 TD3+ R162 RA1+ 26
NC_36 NC_92 LVDS_OUT_B1[1] LVDS_OUT_B2[1] 100 R174 RA4+
E8 M6 RB1- E16 R22 TD3- 29 100
NC_37 NC_91 LVDS_OUT_B1[0] LVDS_OUT_B2[0] RA1- 27
E9 M5 RA4-
NC_38 NC_90 30
E11 M4 RC1+ A4 H22 TCLK1- R163 RB1+ 28
NC_39 NC_89 LVDS_OUT_PIXCLK1 LVDS_OUT_PIXCLK2 100 R175 RB4+
E12 M3 RC1- B20 U20 TA4- 31 100
NC_40 NC_88 LVDS_OUT_DE1 LVDS_OUT_DE2 RB1- 29
E13 M2 SCL2V5 A19 U22 TB4- RB4-
NC_41 NC_87 LVDS_OUT_HS1 LVDS_OUT_HS2 32
E14 M1 SDA2V5 B19 U21 TB4+ R164 RC1+ 30
IC100 NC_42 NC_86 LVDS_OUT_VS1 LVDS_OUT_VS2 100 R176 RC4+
E15 L6 RB1+ 33 100
EP3C55F484C8N NC_43 NC_85 RC1- 31
F7 K19 D8 V21 TC4+ RC4-
NC_44 NC_84 GPIO_0 GPIO_10 34
F8 K7 RA2- A7 V22 TC4- 32
NC_45 NC_83 GPIO_1 GPIO_11
F9 J17 B7 AA21 TE4+ 35
/STATUS K6 G21 SYSCLK NC_46 NC_82 GPIO_2 GPIO_12 R165 RCLK1+ 33
NSTATUS SYSCLK54 F10 J7 RA2+ C7 W21 TCLK4+ 100 R177 RCLK4+
/CONFIG K5 G22 NC_47 NC_81 GPIO_3 GPIO_13 36 100
NCONFIG RST_N /RESET2V5 F11 J6 RB2- D7 W22 TCLK4- RCLK1- 34
CONFIG_DONE M18 A3 NC_48 NC_80 GPIO_4 GPIO_14 RCLK4-
CONFIG_DONE SCL F13 J5 A6 AA22 TE4- 37
DCLK K2 B3 NC_49 NC_79 GPIO_5 GPIO_15 35
DCLK SDA F14 J4 B6 W20
TCK L2 NC_50 NC_78 GPIO_6 GPIO_16 38
TCK F15 J3 C6 Y21 TD4+ R166 RD1+ 36
TDO L4 J21 TC1+ NC_51 NC_77 GPIO_7 GPIO_17 100 R178 RD4+
TDO TEST7 F16 H17 A5 W19 39 100
TMS L1 J20 TD1- NC_52 NC_76 GPIO_8 GPIO_18 RD1- 37
TMS TEST6 F17 H16 B5 Y22 TD4- RD4-
TDI L5 J19 TD1+ NC_53 NC_75 GPIO_9 GPIO_19 40
TDI TEST5 F21 H7 R167 RE1+ 38
DATA0 K1 J18 NC_54 NC_74 100 R179 RE4+
DATA0 TEST4 F22 H6 RB2+ 41 100
MSEL[0] M17 H21 TCLK1+ NC_55 NC_73 RE1- 39
MSEL0 TEST3 RD2- G3 H5 RE4-
MSEL[1] L18 H20 TB1- NC_56 NC_72 42
MSEL1 TEST2 RD2+ G4 H4 RE2+ 40
MSEL[2] L17 H19 TB1+ NC_57 NC_71
MSEL2 TEST1 G5 H3 RE2- 43
MSEL[3] K20 H18 NC_58 NC_70 41
MSEL3 TEST0 G7 G18
/CE L3 NC_59 NC_69 44
NCE G8 G17
ASDO D1 E21 NC_60 NC_68 42
ASDO LED3 G9 G16 45 12V_TCON
/CSO E2 E22 NC_61 NC_67
NCSO LED2 G10 G15
F19 TA1+ NC_62 NC_66 46
LED1 G11 G14
F20 TA1- NC_63 NC_65
LED0 G13 47
NC_64
48

49

50

51 C106 C107 C108

10uF 0.1uF 100pF
16V 50V 50V
52

2V5

52 L101
BLM18PG121SN1D
51 2V5
C116 C117 C118
50
10uF 0.1uF 100pF
16V 16V 50V
49 42
R130
48
41 10K
X100
47 54.0000MHz
40 TRISTATE/OPEN VDD
1 4 R117
46
R111 22 39 IC101 GND OUTPUT 22
LVDS_SELECT EPCS16SI8N_ 2 3 SYSCLK
45
R112 22 38
PWM_DIM C121
44
R113 22 37 R119 0.1uF
OPC_OUT1 22 NCS VCC_2 16V
43 1 8
R114 22 36 /CSO
OPC_ENABLE R120
42
R115 22 35 27 DATA VCC_1
OPC_OUT2 2 7
41 DATA0
34
TA1- R121
40 VCC DCLK 22
33 3 6 DCLK
TA1+ OPT OPT
39 TA3-
32 R122 SAM2333
TB1- GND ASDI 22 R144
38 TA3+ 4 5 ASDO D100 22
31 OPT TP[0]
TB1+ A2[RD]
37 TB3- C
30 C119 R143
1K A1[GN]
TC1- 10pF
36 TB3+
29
TC1+
35 TC3- OPT OPT
28
SAM2333 R146
34 TC3+
27 D101 22
TCLK1- OPT TP[1]
33 A2[RD]
26 C
TCLK1+ R145
32 1K A1[GN]
TCLK3- 2V5
25
31 TCLK3+ OPT OPT
24
TD1- SAM2333 R148
30
23 D102 22
TD1+ R131 OPT TP[2]
29 TD3- A2[RD]
22 10K C
TE1- CONFIG_DONE R147
28 1K A1[GN]
TD3+
21
TE1+ R132
27 TE3-
20 10K OPT OPT
/STATUS
26 TE3+ SAM2333
R116 22 19 R150
BIT_SELECT D103 22
25 OPT TP[3]
18 R133
10K A2[RD]
TA2- /CONFIG R149 C
24 A1[GN]
17 1K
TA2+
23 TA4-
16 OPT OPT
TB2-
22 TA4+ SAM2333
15 R152
TB2+ R134 D104 22
21 TB4- 1K OPT TP[4]
14 /CE
A2[RD]
TC2- R151 C
20 TB4+ A1[GN]
13 1K
TC2+ P104
19 TC4-
12 YFDW254-10S OPT OPT
18 TC4+ SAM2333
11 R154
TCLK2- D105 22
17 R123 TP[5]
10 22 OPT
1 TCK A2[RD]
TCLK2+ R153 C
16 TCLK4- A1[GN]
9 R124 1K 2V5 1K
15 TCLK4+
8 2
TD2-
14
7 R125
TD2+ 22
13 TD4- 3 TDO
6
TE2-
12 TD4+
5 R127 R128
TE2+ 4
11 TE4- 1K 1K
4
R126 2V5
10 TE4+ 22
3 5 TMS
9
12V_TCON 2
8 6
1
7
C120
7
6 0.1uF
L100 16V R135 R136 R137 R138
CB3216PA501E TF05-41S
5
8 0 0 4.7K 4.7K
P103 AR100 READY READY
4
R129 MSEL[3]
22
C112 C113 C114 C115 3 9 TDI MSEL[2]
READY

READY
0

22uF 10uF 0.1uF 100pF MSEL[1]

2
R180

R118

16V 50V 50V MSEL[0]

10
1 22
R139 R140 R141 R142
1K 1K 0 0
READY READY
TF05-51S
P102

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS Europe_3D 2009/10/22
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LVDS 1 4

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 DDR_VREF0 DDR_VREF1

IC100
EP3C55F484C8N
C200 C201 IC200 C203 C204 IC201
0.1uF 470pF 0.1uF 470pF
16V 50V H5PS5162FFR-S6C 16V 50V H5PS5162FFR-S6C L10 P16
SDDR_DQ[15-0] SDDR_DQ[31-16] GND_1 GND_36
L11 L8
GND_2 GND_37
DDR_A[12-0] AR204 33 M10 M7
DDR_A[12-0] VREF J2 G8 DQ0 DDR_DQ[0] VREF J2 G8 DQ0 DDR_DQ[16] DDR_DQ[21] SDDR_DQ[21] GND_3 GND_38
AR200 33 M11 A1
G2 DQ1 DDR_DQ[1] DDR_DQ[5] SDDR_DQ[5] G2 DQ1 DDR_DQ[17] DDR_DQ[18] SDDR_DQ[18] GND_4 GND_39
L12 C5
DDR_A[0] H7 DQ2 DDR_DQ[2] DDR_DQ[2] SDDR_DQ[2] H7 DQ2 DDR_DQ[18] DDR_DQ[16] SDDR_DQ[16] GND_5 GND_40
A0 M8 DDR_A[0] A0 M8 L13 C9
DDR_A[1] H3 DQ3 DDR_DQ[3] DDR_DQ[0] SDDR_DQ[0] H3 DQ3 DDR_DQ[19] DDR_DQ[23] SDDR_DQ[23] GND_6 GND_41
A1 M3 DDR_A[1] A1 M3 M12 C11
DDR_A[2] H1 DQ4 DDR_DQ[4] DDR_DQ[7] SDDR_DQ[7] H1 DQ4 DDR_DQ[20] GND_7 GND_42
A2 M7 DDR_A[2] A2 M7 AR205 33 M13 C12
DDR_A[3] H9 DQ5 DDR_DQ[5] H9 DQ5 DDR_DQ[21] DDR_DQ[29] SDDR_DQ[29] GND_8 GND_43
A3 N2 AR201 33 DDR_A[3] A3 N2 N11 C14
DDR_A[4] F1 DQ6 DDR_DQ[6] DDR_DQ[13] SDDR_DQ[13] F1 DQ6 DDR_DQ[22] DDR_DQ[26] SDDR_DQ[26] GND_9 GND_44
A4 N8 DDR_A[4] A4 N8 K11 C16
DDR_A[5] F9 DQ7 DDR_DQ[7] DDR_DQ[10] SDDR_DQ[10] F9 DQ7 DDR_DQ[23] DDR_DQ[24] SDDR_DQ[24] GND_10 GND_45
A5 N3 DDR_A[5] A5 N3 N12 A22
DDR_A[6] C8 DQ8 DDR_DQ[8] DDR_DQ[8] SDDR_DQ[8] C8 DQ8 DDR_DQ[24] DDR_DQ[31] SDDR_DQ[31] GND_11 GND_46
A6 N7 DDR_A[6] A6 N7 K12 E20
DDR_A[7] C2 DQ9 DDR_DQ[9] DDR_DQ[15] SDDR_DQ[15] C2 DQ9 DDR_DQ[25] GND_12 GND_47
A7 P2 DDR_A[7] A7 P2 AR206 33 K13 G20
DDR_A[8] D7 DQ10 DDR_DQ[10] D7 DQ10 DDR_DQ[26] DDR_DQ[30] SDDR_DQ[30] GND_13 GND_48
A8 P8 AR202 33 DDR_A[8] A8 P8 N13 L20
DDR_A[9] D3 DQ11 DDR_DQ[11] DDR_DQ[14] SDDR_DQ[14] D3 DQ11 DDR_DQ[27] DDR_DQ[25] SDDR_DQ[25] GND_14 GND_49
A9 P3 DDR_A[9] A9 P3 N10 P19
DDR_A[10] D1 DQ12 DDR_DQ[12] DDR_DQ[9] SDDR_DQ[9] D1 DQ12 DDR_DQ[28] DDR_DQ[28] SDDR_DQ[28] GND_15 GND_50
A10/AP M2 DDR_A[10] A10/AP M2 K10 V20
DDR_A[11] D9 DQ13 DDR_DQ[13] DDR_DQ[12] SDDR_DQ[12] D9 DQ13 DDR_DQ[29] DDR_DQ[27] SDDR_DQ[27] GND_16 GND_51
A11 P7 DDR_A[11] A11 P7 J9 Y20
DDR_A[12] B1 DQ14 DDR_DQ[14] DDR_DQ[11] SDDR_DQ[11] B1 DQ14 DDR_DQ[30] GND_17 GND_52
A12 R2 DDR_A[12] A12 R2 AR207 33 F12 AB22
B9 DQ15 DDR_DQ[15] 1V8 B9 DQ15 DDR_DQ[31] 1V8 DDR_DQ[22] SDDR_DQ[22] GND_18 GND_53
AR203 33 H12 Y18
DDR_DQ[6] SDDR_DQ[6] DDR_DQ[17] SDDR_DQ[17] GND_19 GND_54
H13 Y16
DDR_BA[0] BA0 L2 DDR_DQ[1] SDDR_DQ[1] DDR_BA[0] BA0 L2 DDR_DQ[19] SDDR_DQ[19] GND_20 GND_55
J15 Y12
DDR_BA[1] BA1 L3 DDR_DQ[3] SDDR_DQ[3] DDR_BA[1] BA1 L3 DDR_DQ[20] SDDR_DQ[20] GND_21 GND_56
A1 VDD5 A1 VDD5 K16 Y11
DDR_DQ[4] SDDR_DQ[4] DDR_CLK GND_22 GND_57
DDR_CLK E1 VDD4 E1 VDD4 L15 Y9
C202 C205 GND_23 GND_58

R205
100
CK VDD3 CK VDD3 N15 Y5
R200

J8 J9 100pF J8 J9 100pF
100

GND_24 GND_59
CK K8 M9 VDD2 50V CK K8 M9 VDD2 50V R13 AB1
/DDR_CLK /DDR_CLK GND_25 GND_60
CKE K2 R1 VDD1 CKE K2 R1 VDD1 R11 N3
DDR_CKE DDR_CKE GND_26 GND_61
R9 U3
GND_27 GND_62
P8 W3
DDR_ODT ODT K9 DDR_ODT ODT K9 GND_28 GND_63
H14 D3
/DDR_CS CS L8 A9 VDDQ10 /DDR_CS CS L8 A9 VDDQ10 GND_29 GND_64
H10 F3
/DDR_RAS RAS K7 C1 VDDQ9 /DDR_RAS RAS K7 C1 VDDQ9 GND_30 GND_65
H8 K3
/DDR_CAS CAS L7 C3 VDDQ8 /DDR_CAS CAS L7 C3 VDDQ8 GND_31 GND_66
N8 U5
/DDR_WE WE K3 C7 VDDQ7 /DDR_WE WE K3 C7 VDDQ7 GND_32 GNDA1
R7 E18
C9 VDDQ6 C9 VDDQ6 GND_33 GNDA2
T8 F5
R201 33 E9 VDDQ5 R206 33 E9 VDDQ5 GND_34 GNDA3
DDR_LDQS[0] LDQS F7 DDR_LDQS[1] LDQS F7 T12 V18
G1 VDDQ4 G1 VDDQ4 GND_35 GNDA4
DDR_UDQS[0] UDQS B7 DDR_UDQS[1] UDQS B7
G3 VDDQ3 G3 VDDQ3
R202 33 VDDQ2 R207 33 VDDQ2
G7 G7
DDR_LDM[0] LDM F3 G9 VDDQ1 DDR_LDM[1] LDM F3 G9 VDDQ1
DDR_UDM[0] UDM B3 DDR_UDM[1] UDM B3

R203 1K LDQS VSS5 R208 1K LDQS VSS5

E8 A3 E8 A3
UDQS A8 E3 VSS4 UDQS A8 E3 VSS4
R204 1K J3 VSS3 R209 1K J3 VSS3
N1 VSS2 N1 VSS2
NC4 L1 NC4 L1
P9 VSS1 P9 VSS1
NC5 R3 NC5 R3
NC6 R7 NC6 R7
IC100
1V2
EP3C55F484C8N
1V2 2V5
B2 VSSQ10 B2 VSSQ10
NC1 A2 NC1 A2
B8 VSSQ9 B8 VSSQ9
NC2 E2 NC2 E2 T6 J11
A7 VSSQ8 A7 VSSQ8 VCCA1 VCCINT_1
NC3 R8 NC3 R8 F18 J12
D2 VSSQ7 D2 VSSQ7 C206 C207 C208 C209 VCCA2 VCCINT_2 C220 C221 C222
0.1uF 0.1uF 0.1uF 0.1uF G6 L14
D8 VSSQ6 D8 VSSQ6 VCCA3 VCCINT_3 100pF 0.1uF 10uF
16V 16V 16V 16V U18 M14 50V 16V 16V
VSSDL E7 VSSQ5 VSSDL E7 VSSQ5 VCCA4 VCCINT_4
J7 J7 P11
F2 VSSQ4 F2 VSSQ4 VCCINT_5
U6 P12
F8 VSSQ3 F8 VSSQ3 VCCD_PLL1 VCCINT_6
E17 L9
H2 VSSQ2 H2 VSSQ2 C210 C211 C212 C213 VCCD_PLL2 VCCINT_7
2V5 0.1uF 0.1uF 0.1uF 0.1uF F6 M9
VDDL J1 H8 VSSQ1 VDDL J1 H8 VSSQ1 VCCD_PLL3 VCCINT_8
16V 16V 16V 16V V17 J13
VCCD_PLL4 VCCINT_9
J14
VCCINT_10
D4 K14
VCCIO1_1 VCCINT_11
F4 J10
VCCIO1_2 VCCINT_12
C214 C215 C216 K4 K9
10uF 0.1uF 100pF VCCIO1_3 VCCINT_13
1V8 N4 N9
16V 16V 50V VCCIO2_1 VCCINT_14
U4 P9
VCCIO2_2 VCCINT_15
W4 P10
VCCIO2_3 VCCINT_16
1V8 AB2 P13
VCCIO3_1 VCCINT_17
1V8 W5 P14
VCCIO3_2 VCCINT_18
C217 C218 C219 W9 N14
10uF 0.1uF 100pF VCCIO3_3 VCCINT_19
W11 J16
16V 16V 50V VCCIO3_4 VCCINT_20
AB21 K15
VCCIO4_1 VCCINT_21
C404 C405 C406 C407 C408 C409 C410 C411 C412 C413 C414 C415 C416 C417 C418 C419 C420 C421 C288 C289 C290 C291 C292 C293 C294 C295 C296 C297 C298 C299 C400 C401 C402 C403 2V5 W12 L16
10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF VCCIO4_2 VCCINT_22
W16 M15
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V VCCIO4_3 VCCINT_23
W18 R12
VCCIO4_4 VCCINT_24
P18 R10
VCCIO5_1 VCCINT_25
V19 R8
VCCIO5_2 VCCINT_26
DDR_VREF0 Y19 H9
VCCIO5_3 VCCINT_27
E19 G12
VCCIO6_1 VCCINT_28
G19 J8
VCCIO6_2 VCCINT_29
L19 M8
VCCIO6_3 VCCINT_30
A21 T7
C422 C423 VCCIO7_1 VCCINT_31
D12 T9
DDR_VTT 0.1uF 470pF VCCIO7_2 VCCINT_32
IC100 D14 T13
16V 50V VCCIO7_3 VCCINT_33
EP3C55F484C8N SDDR_DQ[31-16] D16 P15
DDR_VTT VCCIO7_4 VCCINT_34
A2 H15
VCCIO8_1 VCCINT_35
D5 H11
VCCIO8_2 VCCINT_36
DDR_A[12] W10 AA9 SDDR_DQ[31] D9 K8
RAM_ADDR[12] RAM_DATA[31] VCCIO8_3 VCCINT_37
DDR_A[11] Y15 AA8 SDDR_DQ[30] AR208 56 AR213 56 DDR_VREF1 D11 L7
RAM_ADDR[11] RAM_DATA[30] C223 C224 C225 C226 C227 C228 C229 C230 C231 C232 VCCIO8_4 VCCINT_38
DDR_A[10] AA6 V11 SDDR_DQ[29] DDR_ODT DDR_ODT 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RAM_ADDR[10] RAM_DATA[29]
DDR_A[9] U14 AB8 SDDR_DQ[28] /DDR_CS /DDR_CS 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V AA18
RAM_ADDR[9] RAM_DATA[28] DDR_VREF_1
DDR_A[8] T16 AB7 SDDR_DQ[27] DDR_A[0] DDR_A[0] AB4
RAM_ADDR[8] RAM_DATA[27] DDR_VREF_2
DDR_A[7] AB10 U10 SDDR_DQ[26] DDR_A[2] DDR_A[2] U11
RAM_ADDR[7] RAM_DATA[26] DDR_VREF_3
DDR_A[6] R16 Y8 SDDR_DQ[25] C424 C425 V9
RAM_ADDR[6] RAM_DATA[25] 0.1uF 470pF DDR_VREF_4
DDR_A[5] R14 Y10 SDDR_DQ[24] AR209 56 AR214 56 V12
RAM_ADDR[5] RAM_DATA[24] DDR_VTT 16V 50V DDR_VREF_5
DDR_A[4] Y17 V8 SDDR_DQ[23] DDR_A[4] DDR_A[4] V16
RAM_ADDR[4] RAM_DATA[23] DDR_VREF_6
DDR_A[3] U9 W6 SDDR_DQ[22] DDR_A[6] DDR_A[6]
RAM_ADDR[3] RAM_DATA[22]
DDR_A[2] AB17 W7 SDDR_DQ[21] DDR_A[8] DDR_A[8] 2V5
RAM_ADDR[2] RAM_DATA[21]
DDR_A[1] W14 Y3 SDDR_DQ[20] DDR_A[11] DDR_A[11]
RAM_ADDR[1] RAM_DATA[20] C233 C234 C235 C236 C237 C238 C239 C240
DDR_A[0] AA17 AA4 SDDR_DQ[19] 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RAM_ADDR[0] RAM_DATA[19]
Y7 SDDR_DQ[18] SDDR_DQ[15-0] AR210 56 AR215 56 16V 16V 16V 16V 16V 16V 16V 16V
RAM_DATA[18]
DDR_LDQS[1] V10 AA5 SDDR_DQ[17] /DDR_CAS /DDR_CAS
RAM_LDQS_2 RAM_DATA[17] C241 C242 C243 C244 C245 C246 C247 C248 C249 C250
DDR_LDQS[0] V13 W8 SDDR_DQ[16] /DDR_RAS /DDR_RAS 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RAM_LDQS_1 RAM_DATA[16]
DDR_UDQS[1] AB9 AB14 SDDR_DQ[15] DDR_A[1] DDR_A[1] 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
RAM_UDQS_2 RAM_DATA[15]
DDR_UDQS[0] Y13 AA13 SDDR_DQ[14] DDR_A[5] DDR_A[5]
RAM_UDQS_1 RAM_DATA[14]
DDR_CLK U16 AA15 SDDR_DQ[13]
RAM_CLK RAM_DATA[13]
/DDR_CLK U17 W13 SDDR_DQ[12] AR211 56 AR216 56
RAM_CLKN RAM_DATA[12]
U12 SDDR_DQ[11] DDR_A[9] DDR_A[9] 2V5
RAM_DATA[11] 1V2
DDR_CKE AA3 AB15 SDDR_DQ[10] DDR_A[12] DDR_A[12]
RAM_CKE RAM_DATA[10]
/DDR_CS AB19 AB13 SDDR_DQ[9] DDR_A[7] DDR_A[7]
RAM_CSN RAM_DATA[9]
/DDR_RAS U15 AA14 SDDR_DQ[8] DDR_A[3] DDR_A[3]
RAM_RASN RAM_DATA[8]
/DDR_CAS Y14 T15 SDDR_DQ[7]
RAM_CASN RAM_DATA[7] C251 C252 C253 C254 C255 C256 C257 C258 C259 C260
/DDR_WE Y4 W15 SDDR_DQ[6] C269 C270 C271 C272 C273 C274 C275 C276 C277 C278 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RAM_WEN RAM_DATA[6] AR212 56 AR217 56 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
AB20 SDDR_DQ[5] 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
RAM_DATA[5] DDR_BA[0] DDR_BA[0] 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
DDR_BA[1] AB3 AB16 SDDR_DQ[4]
RAM_BA[1] RAM_DATA[4] DDR_BA[1] DDR_BA[1]
DDR_BA[0] Y6 V15 SDDR_DQ[3]
RAM_BA[0] RAM_DATA[3] DDR_CKE DDR_CKE
AB18 SDDR_DQ[2]
RAM_DATA[2] /DDR_WE /DDR_WE
DDR_ODT AA19 V14 SDDR_DQ[1] 1V2
RAM_ODT RAM_DATA[1]
DDR_LDM[1] V5 W17 SDDR_DQ[0] 1V8
RAM_LDM_2 RAM_DATA[0] R210 R211
DDR_UDM[1] AA7
RAM_UDM_2 56 56
AA16 DDR_A[10] DDR_A[10]
DDR_LDM[0]
RAM_LDM_1
DDR_UDM[0] AA10
RAM_UDM_1 C279 C280 C281 C282 C283 C284 C285 C286 C287
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C261 C262 C263 C264 C265 C266 C267 C268
16V 16V 16V 16V 16V 16V 16V 16V 16V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V 16V 16V 16V 16V 16V 16V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS Europe_3D 2009/10/22
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MEMORY 2 3

Copyright 2010 LG Electronics. Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 +12V_FORMATTER

R300
5V_GENERAL
100K
2V5 3V3
IC300
MP2305DS READY
R327
C302 10K L310
0.1uF
50V MLB-201209-0120P-N2
BS SS
1 8 C316 100pF
R307
0.01uF C348 C349 OPT
25V IN EN 3D_POWER_EN 0.1uF 22uF
2 7 R308 R309 R310 C347 16V 16V
C303 10K 0 5.1K
5600pF R325 0.1uF
IC307 OPT OPT
SW COMP 50V 9.1K 16V
C300 C301 3 6 IC302 R311 MAX3372EEKA-T
22uF 0.47uF 100 OPT
25V 25V MP2212DN READY
5V_GENERAL

CB3216PA501E
GND FB R333 R336
4 5 22 I/O_VCC2 I/O_VCC1 22
1V2 SDA 1 8 SCL
R2 R302 FB EN/SYNC

L304
12.4K 1 8
R301 OPT OPT
R1 1% L309 GND VCC
56K 2 7
1% L301 GND SW_2 3.6uH OPT
2 7
Vout=0.923*(1+R1/R2) BLM18PG121SN1D

R312
100K
VL THREE-STATE
C322 3 6
L300 IN SW_1 C321 C323
22UH C304 C306 3 6 22uF 0.1uF 22uF
22uF 16V 50V 16V R334 R337
0.1uF C318 22 I/O_VL2 I/O_VL1 22
16V C317 C319 4 5
16V 22uF 0.1uF 22uF BS VCC READY SDA2V5 SCL2V5
16V 50V 16V 4 5 OPT OPT
READY

R348
0
D300 R313 C320
100V 10 0.1uF

1N4148W_DIODES
READY R314
10
C324
1uF
25V

+12V_FORMATTER
2V5 3V3 2V5 3V3

R303

100K

IC301
3V3
MP2305DS

R339
4.7K

R340

R341
5.6K

R344
4.7K

R345

R346
5.6K
OPT

OPT
C311

2K

2K
0.1uF
BS SS 50V
1 8 DDR_VTT

G
C310
0.01uF R338 R342 R343 R347
25V IN EN SDA SCL
2 7

D
C312 22 22 22 22
5600pF R304
50V FDV301N FDV301N
C308 C309 SW COMP 9.1K IC303 Q302 Q303
3 6 C326 C327
22uF 0.47uF C325 BD35331F-E2
25V 25V 100uF 10uF 0.1uF
16V 16V 16V 1V8
GND FB
4 5
3V3 GND VTT
R2 R306 1 8
R326

12.4K
10K

R305 1%
R1 33K EN VTT_IN
2 7
1% DDR_VREF0
L303
Vout=0.923*(1+R1/R2) BLM18PG121SN1D VTTS VCC
3 6
L302 L305
22UH C313 C315 BLM18PG121SN1D R316
22uF VREF VDDQ 220
0.1uF 4 5
16V 16V
C334 C335 C336
C330 R315 C331 10uF 2.2uF 0.1uF
C328 C329 0.1uF 0.1uF
0.1uF 0.1uF 1M 25V 10V 16V
16V 16V
DDR_VREF1 16V 16V READY READY

L306 3V3
BLM18PG121SN1D

C332 C333
0.1uF 0.1uF
16V 16V R324
R323 FPGA_RESET
1K 4.7K
IC306
FPGA_RESET
SW300 FPGA_RESET KIA7029AF
JTP-1127WEM R322
1 2 330 I O
1 3 /3D_FPGA_RESET
2V5 FPGA_RESET 2
3 4
C345 G C346
FPGA_RESET 0.1uF 0.1uF
3V3 16V 16V
IC304 FPGA_RESET
FPGA_RESET
AZ2940D-2.5TRE1
L307
MLB-201209-0120P-N2
VIN 1 3 VOUT

C337 C338
2
GND
GAS1 GAS2 GAS3
22uF 0.1uF R317
25V 16V 1
M300 M301 M302
MDS61887701 MDS61887701 MDS61887701
C339 C350 C340
10uF 10uF 0.1uF
10V 10V 16V
READY

3V3 2V5

GAS5 GAS4
M303 M304
R329 10K R331 10K
3V3
IC305
1V8 MDS61887701 MDS61887701 R332
22
AZ1085S-ADJTR/E1 /RESET2V5
L308 C
MLB-201209-0120P-N2
INPUT OUTPUT R330 B Q301
3 2
2SC3052
C342 1 C344 10K
C341 C343
22uF 0.1uF 22uF 0.1uF E
ADJ/GND C
25V 16V 16V 16V
R328 B Q300
R320 R321
/3D_FPGA_RESET 2SC3052
10K
62 82
E
R319
62

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS Europe_3D 2009/10/22
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER 2 3

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