// ELD LAB 2

// Shaurya Goel

// 2016194

Q1

Data flow Model

`timescale 1ns / 1ps

module q1(h,v,a,t,p);

input [1:0]t,p;

output h,v,a;

assign h=((~t[1])&(~t[0]))&(~(p[1]&p[0]));

assign v=((~p[1])&(~p[0]))&(~((~t[1])&(~t[0])));

assign a=(((~p[1])&(~p[0]))&((~t[1])&(~t[0])))|((p[1]&p[0])&(t[1]&t[0]));

endmodule

Behavioural model

`timescale 1ns / 1ps

module q1_behav(h,a,v,t,p);

input [1:0]t,p;

output reg h,a,v;

always @(*)

begin

if(t[1]==0 && t[0]==0 && ~(p[1]==1 && p[0]==1))

h=1'b1;

else

h=1'b0;

end

always @(*)

begin

if(p[1]==0 && p[0]==0 && ~(t[1]==0 && t[0]==0))

v=1'b1;

else
 v=1'b0;

end

always @(*)

begin

if((p[1]==0 && p[0]==0 && t[1]==0 && t[0]==0 )||(p[1]==1 &&p[0]==1 && t[1]==1 && t[0]==1))

a=1'b1;

else

a=1'b0;

end

endmodule

Constraint File

set_property PACKAGE_PIN T21 [get_ports {h}];

set_property IOSTANDARD LVCMOS33 [get_ports {h}];

set_property PACKAGE_PIN T22 [get_ports {v}];

set_property IOSTANDARD LVCMOS33 [get_ports {v}];

set_property PACKAGE_PIN U22 [get_ports {a}];

set_property IOSTANDARD LVCMOS33 [get_ports {a}];

set_property PACKAGE_PIN F22 [get_ports {t[1]}];

set_property IOSTANDARD LVCMOS33 [get_ports {t[1]}];

set_property PACKAGE_PIN G22 [get_ports {t[0]}];

set_property IOSTANDARD LVCMOS33 [get_ports {t[0]}];

set_property PACKAGE_PIN H22 [get_ports {p[1]}];

set_property IOSTANDARD LVCMOS33 [get_ports {p[1]}];

set_property PACKAGE_PIN F21 [get_ports {p[0]}];

set_property IOSTANDARD LVCMOS33 [get_ports {p[0]}];

Q2

Behavioural model

`timescale 1ns / 1ps

module lab_2_q2_behav(y,z,cost,t,useful,lec);

input [1:0] cost,t;

input useful,lec;

output reg y,z;

always @(*)

begin

if((t[1]==0) && (t[0]==0) && (useful==1))

z=1'b1;

else if((useful==1) && ((cost[1]|cost[0])==1))

z=1'b1;

else

z=1'b0;

end

always @(*)

begin

if(z==1'b1)

y=1'b0;

else if((cost[1]==0) && (cost[0]==0) && (t[1]==0) && (t[0]==0) && (useful==0))

y=1'b1;

else if((cost[1]==1) && (cost[0]==1) && (lec==1) && ((t[1]|t[0])==1))

y=1'b1;

else

y=1'b0;

end

endmodule
Data Flow Model

`timescale 1ns / 1ps

module lab_2_q_2_data_flow(y,z,cost,t,useful,lec );

input [1:0] cost,t;

input useful,lec;

output y,z;

assign z=((~cost[1])&(~cost[0])&(useful))|(useful&(cost[1]|cost[0]));

assign y=(~z)&(((~cost[1])&(~cost[0])&(t[1])&(t[0])&(~useful))|((cost[1])&(cost[0])&(lec)&(t[1]|t[0])));

endmodule

Constraint File

set_property PACKAGE_PIN F22 [get_ports {cost[0]}];

set_property IOSTANDARD LVCMOS33 [get_ports {cost[0]}];

set_property PACKAGE_PIN G22 [get_ports {cost[1]}];

set_property IOSTANDARD LVCMOS33 [get_ports {cost[1]}];

set_property PACKAGE_PIN H22 [get_ports {t[0]}];

set_property IOSTANDARD LVCMOS33 [get_ports {t[0]}];

set_property PACKAGE_PIN F21 [get_ports {t[1]}];

set_property IOSTANDARD LVCMOS33 [get_ports {t[1]}];

set_property PACKAGE_PIN H19 [get_ports {useful}];

set_property IOSTANDARD LVCMOS33 [get_ports {useful}];

set_property PACKAGE_PIN H18 [get_ports {lec}];

set_property IOSTANDARD LVCMOS33 [get_ports {lec}];

set_property PACKAGE_PIN T22 [get_ports {y}];

set_property IOSTANDARD LVCMOS33 [get_ports {y}];

set_property PACKAGE_PIN T21 [get_ports {z}];

set_property IOSTANDARD LVCMOS33 [get_ports {z}];