A. IEEE 1346
B. IEEE 1364
C. IEEE 1394
D. IEEE 1349
A. Behavioral level
B. Dataflow level
C. Gate level
D. Switch level
4. In verilog `h1234 is a
D. It is invalid notation
A. U
B. X
C. Z
A. 0
B. X
C. Z
D. U
A. 0
B. X
C. Z
D. U
A. End simulation
B. Suspend simulation
C. Exit simulator
A. net only
B. a reg only
A. 6
B. 9
C. 27
D. Invalid expression
A. 110x
B. 1100
C. xxxx
A. 1
B. X
C. Z
D. 0
A. 4
B. 4.5
C. -1
D. +1
14. Initial value of a=1 and b=2, then what will be final value if
a=b;
b=a;
A. a= 2, b=1
B. a= 1, b=2
15. Initial value of a=1 and b=2, then what will be final value if
a<=b;
b<=a;
A. a= 2, b=1
B. a= 1, b=2
16. Given the following Verilog code, what value of "a" is displayed?
always @ (clock) begin
a = 0;
a <= 1;
$display(a);
end
A. 0
B. 1
17. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity list?
A. No
B. Yes
D. None of these
Q1<=d;
Q2<=q1;
Q3<=q2;
end
A. 1
B. 2
C. 3
A. 1ns/1ps
B. 10ns/1ps
C. 100ns/100ps
D. 100ns/110ps
20. If time scale is defined as `timescale 10ns/1ns and #1.55 a = b; then 'a' gets 'b' after
A. 10ns
B. 11 ns
C. 15.5ns
D. 16ns
A. Input only
B. Output only
A. Unary
B. Multiplication
C. Addition
D. Conditional
initial
begin
#5 x= 1b0; // statement 1
# 15 y= 1b1; //statement 2
End
A. 15
B. 20
C. 5
A. Variable
B. Signal
C. Cant say