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1, JANUARY 2012

Thickness and Capacitance to Multigate

MOSFETs Modeling

Nicolas Chevillon, Jean-Michel Sallese, Christophe Lallement, Member, IEEE, Fabien Prgaldiny,

Morgan Madec, Josef Sedlmeir, and Jasmin Aghassi

AbstractIn this letter, we propose to introduce the notion of which technology is quite challenging and not yet adopted by

equivalent capacitance and to generalize the so-called equivalent- the industry.

thickness concept to model arbitrary shapes of lightly doped Conversely, multigate MOSFETs such as FinFETs and -

nonplanar multigate MOSFETs, without the need to introduce

any unphysical parameter. These definitions, which merely map FETs [3] have proven their compatibility with standard CMOS

a multigate geometry into the symmetric double-gate (DG) MOS- technology and lithography techniques, leading to basic circuits

FET topology, have been validated by extensive comparison with [4]. Today, FinFETs are foreseen as next-generation devices for

3-D numerical simulations of quadruple-gate, triple-gate (TG), microprocessors [5]. But, modeling multigate architectures is

triangular gate, cylindrical gate-all-around, and DG Fin Field Ef- quite complex, the main reason being that the structure is 2-D,

fect Transistors (FinFETs). Based on this modeling approach, any

multigate architecture inherits of the fundamental relationships

and hence, no simple solution exists for the BoltzmannPoisson

that have been developed for planar DG MOSFETs, including equation. An empirical approach was proposed by Yu et al.

the normalization of all electrical quantities that considerably [6], who introduced some arbitrary smoothing functions and

simplifies its analysis. In addition, considering a constant mobility, fitting parameters in order to fit the charges and the current in

we find that the model can predict electrical characteristics of nonplanar multigate topologies. In their approach, the authors

FinFETs from 275 to 425 K, without the need for any additional

extended their cylindrical surrounding-gate (SG) MOSFETs

parameters. Finally, we were able to predict electrical measure-

ments of a TG MOSFET, making of this generic model an interest- model to quadruple-gate (QG) MOSFETs. They noted that,

ing candidate for a design-oriented compact model for arbitrary when volume inversion occurs, the subthreshold current is

multigate MOSFETs geometries. proportional to the area of the cross section of the silicon

Index TermsMOS devices, semiconductor device modeling, body. On the other hand, well above threshold, the current

semiconductor devices. becomes proportional to the perimeter of the cross section of

the silicon body. In their approach, the QG was modeled as

I. I NTRODUCTION an SG, but the transition between subthreshold and above-

threshold regimes requires an empirical function depending

A S FAR as compact modeling is concerned, the simplest

multigate MOSFET device to model is undoubtedly the

fully depleted symmetric double-gate (DG) MOSFET. Dif-

on the gate voltage. Hence, the authors proposed a model for

partially surrounding rectangular multiple-gate MOSFETs as

ferent approaches have been proposed. Yu et al. [1] initially a linear combination of a DG and a QG model. For instance,

developed an exact solution that is still difficult to use in the the triple-gate (TG) MOSFET was considered as an average of

context of compact modeling, where more simple relationships a DG and a QG having the same cross section and the same

are preferred. Next, a more compact formulation was proposed gate oxide thickness as for the TG. To model -FET or Pi-FET,

by Sallese et al. [2], where an approximate solution was sought other empirical functions are required, together with empirical

and led to a more compact but still accurate formulation. parameters extracted from Technology Computer Aided Design

However, these models concern the symmetric DG MOSFET, (TCAD) simulations that could not be predicted from simple

analysis.

Next, an interesting and complete analytical modeling of

Manuscript received July 28, 2011; revised September 9, 2011; accepted multiple-gate MOSFETs in subthreshold was proposed by

October 3, 2011. Date of publication October 27, 2011; date of current version

December 23, 2011. This work was supported by the European Compact Ritzenthaler et al. [7]. The potential in the volume of the

Modelling Network (COMON), Industry Academia Partnerships and Pathways channel was obtained by solving the 3-D Laplaces equation,

research project under Grant FP7-IAPP-218255. The review of this letter was where the electrostatic potential along the most leaky path

arranged by Editor S. Deleonibus.

N. Chevillon, C. Lallement, F. Prgaldiny, and M. Madec are with the Institut from source to drain was used to get an analytical subthreshold

dlectronique du Solide et des Systmes, Centre National de la Recherche current expression. As for [6], the draincurrent characteristics

Scientifique, Universit de Strasbourg, 67412 Illkirch, France. from weak to strong inversion were obtained by means of

J.-M. Sallese is with cole Polytechnique Fdrale de Lausanne, 1015

Lausanne, Switzerland (e-mail: jean-michel.sallese@epfl.ch). smoothing functions.

J. Sedlmeir and J. Aghassi are with Intel Mobile Communications GmbH, In addition to these approaches is the solution proposed

85579 Neubiberg, Germany. in [2] that consists in calculating the potential of the silicon

Color versions of one or more of the figures in this letter are available online

at http://ieeexplore.ieee.org. layer in weak inversion, without the need for any empiri-

Digital Object Identifier 10.1109/TED.2011.2171347 cal parameter. Recently, this approach has been extended to

CHEVILLON et al.: EQUIVALENT THICKNESS AND CAPACITANCE TO MOSFETs MODELING 61

sumptions. Likewise for the DG MOSFET, in strong inversion

mobile charges will locate at the Si/SiO2 interfaces, the volume

of silicon having little impact on the global charge density. This

means that the device reverts to a quasi 1-D system, which

suggests that the solution obtained for the long-channel DG

MOSFET may still be accurate enough to estimate the charge

density in strong inversion for the rectangular FET.

Now, considering weak inversion (although subthreshold

would be more adopted when considering undoped devices, we

propose to still use weak inversion for simplicity), the right-

hand side term in (1) cancels, and we note that setting (x, y)

to constant value 0 is a viable solution. Therefore, the charge

density is uniform in the silicon, and the current only depends

on the area of the cross section of the body. The device is in

volume inversion.

To some extent, these arguments justify that the rectangular

multigate MOSFET can be planarized and considered as a

DG MOSFET having the same Si/SiO2 interface perimeter,

ensuring consistency with strong inversion, and also the same

volume of silicon to match subthreshold characteristics. In this

attempt, we simply ignore corner effects, which are known to

be negligible in a lightly doped channel [9].

Based on these considerations, we propose to show how the

QG MOSFET can be modeled as a simple DG MOSFET. In [2],

Fig. 1. Schematic of multigate MOSFET cross sections. (a) DG MOSFET.

(b) QG MOSFET. (c) TG MOSFET. (d) GAA MOSFET. (e) Triangular we have shown that, in a symmetric DG MOSFET, the charge

MOSFET. (f) DG FinFET. potential relationship is given by

QG QG 2

VG Vch = + UT ln C1

simulate doped symmetric DG MOSFETs by introducing the Cox 2 Si q UT ni

so-called equivalent-thickness concept [8]. Based on this work, 0 V

ch

we propose to discuss how this concept can be extended to with C1 = e UT (2)

account for nonplanar geometries, ending with a generic com-

pact model with neither empirical relationships nor empirical where QG is the gate charge density, Cox is the gate oxide

parameters. capacitance, C1 is an integration constant that plays a role

mainly in weak inversion and which was approximated in [2],

and is the work function difference between the gate and

II. D EFINITION OF THE E QUIVALENT S ILICON T HICKNESS the silicon.

FOR THE R ECTANGULAR FET

Here is the point that is worth to be discussed: C1 is re-

In order to introduce the idea of the equivalent-silicon- lated to the potential at the center of the DG MOSFET, i.e.,

thickness concept of a DG MOSFET [see Fig. 1(a)] for SG 0 , and therefore, its value is closely linked to the mobile

geometries, we propose to illustrate such a definition on a charge density. In our QG MOSFET case, since the potential

rectangular FET (QG) as the one depicted in Fig. 1(b). is uniform across the silicon in weak inversion, the electron

concentration in the channel is ni e(0 Vch )/UT , involving a

quantity of charges in the cross section of the channel that

A. Derivation of the Mobile Charge Density is equal to q ni e(0 Vch )/UT (HSi WSi ). This leads to

Unlike planar DG MOSFETs, strictly speaking, the a gate charge density per unit surface for the QG that is

BoltzmannPoisson equation has to be solved in two dimen- given by

sions, leading to 0 Vch

(x,y)V q ni e UT

(H Si WSi ) .

d2 (x, y) d2 (x, y) q ni ch QG =

QG WI (3)

+ = e UT

(1) 2 (HSi + WSi )

dx2 dy 2 Si

where is the electrostatic potential, q is the elementary Then, for the QG MOSFET, a relationship exists between

electronic charge, ni is the silicon intrinsic concentration, Si the integration constant and the gate charge density evaluated

is the dielectric constant of the silicon, Vch is the quasi-Fermi in weak inversion, i.e.,

potential for electrons, and UT is the thermodynamic voltage.

QG WI

QG

Unlike its 1-D counterpart, this nonlinear differential equation C1 QG WI

QG = HSi WSi

. (4)

has no exact analytical solution. At this point, it is interesting to q ni 2(HSi +WSi )

62 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012

the QG MOSFET becomes

QG

VG Vch = + UT

Cox

QG 2 QG

ln + (5)

2 Si q UT ni T

q ni 2eq

HSi WSi

Teq = . (6)

HSi + WSi

Likewise in [8], we propose to introduce some normalization

that will be very useful for the model coherence and for circuit

design purposes. Therefore, voltages and charges are normal- Fig. 2. Drain current of a QG MOSFET with a square cross section as

ized as v = V /UT and q = Q/Qsp , where Qsp = 4 Cox UT , a function of gate voltage in linear and saturation regimes. (Symbols) 3-D

leading to a dimensionless fundamental relationship simulations. (Lines) Model.

cox

vg vto vch = 4 qg + ln(qg ) + ln 1 + qg .

CSi_eq

(7)

Here, vto is the normalized long-channel threshold voltage

defined as

8 Cox UT

vto = ln (8)

q ni Teq

Since relation (7) is formally the same as (10) in [2], we

can use the same current expression as in [2] and the same

convention for the equivalent DG width, which is here half of

the silicon perimeter, i.e., Weq = HSi + WSi . Fig. 3. Drain current of a QG MOSFET with a square cross section as a

function of drain voltage in linear and saturation regimes. (Symbols) 3-D

Therefore, these equivalent geometrical parameters simulations. (Lines) Model.

(Teq and Weq ) will now replace their DG counterparts in

the current normalization factor.

The specific current for the QG MOSFET is then defined as 1000 cm2 /V s was used. Physical and equivalent parameters

were obtained from the same set of geometrical and technolog-

IS = 4 Cox UT 2 (Weq /L) (9)

ical parameters.

where L is the channel length; and the corresponding normal- Simulations have been carried out in a QG MOSFET having

ized current becomes a square cross section of 40 nm 40 nm. The channel length

was set to 1 m. In this case, the equivalent silicon thickness

CSi_eq Cox and channel width are 20 and 80 nm, respectively. Figs. 2

i = qm + 2 qm + 2

2

ln 1 qm

Cox 2 CSi_eq and 3 show the current versus the gate voltage at low and

Si high drain voltages, as well as the current versus the drain

with CSi_eq = (10) voltage for different gate voltages. For both characteristics, a

Teq

comparison of the model [see relations (9) and (10)] with 3-

where the physical silicon capacitance is replaced by its equiv- D simulations confirms the validity of the modeling approach

alent value CSi_eq (note that qm = 2 qg ). presented so far. With regard to the drain current dependence

on the gate voltage (see Fig. 2), the accuracy is pretty good,

both in linear and log scales, and without the need to introduce

C. Comparison With 3-D Numerical Simulations

any empirical parameter. Similarly, the matching is very good

In this section, we propose to assess the analytical model for the output characteristics, as shown in Fig. 3. Therefore, the

for QG MOSFETs based upon the equivalent thickness and transformation of the QG MOSFET into a DG MOSFET based

width versus full 3-D numerical simulations [10]. In order to on the equivalent geometrical parameter definitions seems to be

minimize the number of parameters, a constant mobility of totally justified.

CHEVILLON et al.: EQUIVALENT THICKNESS AND CAPACITANCE TO MOSFETs MODELING 63

TO A RBITRARY SG G EOMETRIES

in square-shaped MOSFETs relying on a generic relationship

while defining an equivalent silicon thickness. Assuming a

constant oxide capacitance along the silicon channel perimeter,

we can go one step further and propose a generalization of this

approach to arbitrary SG geometries (not only square).

Starting from a device having a silicon channel with section

S and perimeter P , when the potential is uniform inside the de-

vice (i.e., weak inversion), (x, y) = 0 . Therefore, following

the same approach as in Section II, we get a generic relationship

between charges and potentials that is simply (6) including the

equivalent thickness defined as

2S Fig. 4. Drain current of a triangular gate MOSFET as a function of gate

Teq = . (11) voltage in linear and saturation regimes. (Symbols) 3-D simulations. (Lines)

p Model.

current as solution for the charge and current versus potential relation-

ships has been proposed in [12].

CSi_eq Cox The BoltzmannPoisson differential equation is now ex-

i = qm 2 + 2 qm + 2 ln 1 qm

Cox 2 CSi_eq pressed in cylindrical coordinates, i.e.,

(12)

with CSi_eq = Si /Teq and Weq = P/2, and the specific cur- d2 (r) 1 d(r) q ni (r)V ch

+ = e UT (13)

rent is still given by Isp = 4 Cox UT 2 (Weq /L). dr 2 r dr Si

Note that, when the curvature radius of the silicon channel

becomes comparable to the oxide thickness, it is mandatory to where r is the radius. Contrary to the planar DG MOSFET, this

rely on a more accurate expression for the gate oxide capaci- equation has an exact solution [13] given by

tance as this is no longer obtained by considering the shortest

distance between the gate and the silicon. This was illustrated 8 B UT Si

(r) = Vch + UT ln . (14)

in the case of the gate-all-around (GAA) MOSFET. Such a (1 + B r )

2 2 q ni

gate capacitance should be carefully evaluated, particularly in

strong inversion, where this parameter has a strong impact on Here, the term B is related to the surface potential condition.

the charge versus potential dependence (although it also affects By considering the charge expression of the gate oxide capac-

weak inversion through the threshold voltage). itance, i.e., QG = Cox (VG (RSi )), and applying

Ultimately, we propose to verify the validity of the equivalent the Gauss theorem at the Si/SiO2 interface, i.e., QG = Si

thickness for a triangular cross section SG MOSFET [see (d(r)/dr)|r=RSi , we can show that we obtain an implicit

Fig. 1(e)], as studied in [11]. The choice for this geometry is relationship between the potentials and the gate charge density

motivated by the fact that it combines both 2-D geometry and given by

sharp corners, which could complicate its modeling.

The device of interest consists in an equilateral triangu- VG Vch 8 QG QG

ln = + ln

lar silicon MOSFET, with all sides WSi equal to 10 nm. UT RSi

2 Cox UT Q0

From relation (11), the equivalent thickness is then Teq = QG 4 Si UT

1/3 WSi 2 (WSi /2)2 , and the equivalent width for the spe- + ln 1 + with Q0 = (15)

Q0 RSi

cific current is Weq = 3/2(WSi ).

Fig. 4 shows 3-D simulations of the drain current versus the where RSi is the radius of the nanowire silicon, = (q

gate voltage for this triangular MOSFET. We still observe a ni )/(Si UT ) is a parameter depending on the semiconductor

very good agreement with the DG model using the equivalent- properties, and Cox is the gate oxide capacitance per unit

thickness concept, supporting that this approach is robust even surface for the GAA, which is given by

if angles between the gates become acute.

ox

Cox = (16)

IV. C ASE S TUDY: T HE GAA FET RSi ln 1 + Tox

RSi

Tox being the oxide thickness.

The ultimate nonplanar multigate architecture is undoubtedly Equation (15) has strong similarities with the generic relation

the GAA MOSFET [see Fig. 1(d)]. Interestingly, an analytical (2) that we have used so far to model DG MOSFETs. Indeed,

64 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012

DG MOSFET is

q

int Cox

vg v + ln = 4 qg + ln(qg )+ln 1+qg

2 CSi

(17)

where qg is the gate charge density normalized to specific

charge Qsp .

Now, using the same charge normalization factor as for the

DG MOSFET, the normalized GAA chargepotential relation-

ship takes the form

Cox

vg v vto = 4 qg + ln(qg ) + ln 1 + qg

CSi

(18)

Fig. 5. Drain current of a GAA MOSFET as a function of gate voltage

where the normalized gate charge density is qg = Qg /Qsp , the in linear and saturation regimes for different silicon radius. (Symbols) 3-D

simulations. (Lines) Model.

normalized threshold voltage is vto = ln((8 Cox UT )/(q

ni RSi )), and the silicon capacitance is defined as CSi =

Si /RSi .

From (18), we get a normalized chargepotential relationship

that is strictly identical to the planar DG approximate solution

[see (17)]. Given that (18) is an exact solution, we can wonder

if the equivalent silicon thickness still applies.

According to the definition, such an equivalent thickness

would be given by the surface divided by half of the wire

perimeter. Then, the equivalent thickness would be Teq =

( RSi 2 )/((2 RSi )/2) = RSi , which is indeed what was

obtained in (18).

Therefore, the definition of the equivalent thickness is fully

consistent with the exact solution of the PoissonBoltzmann

equation for the GAA. This is a remarkable property that was

somehow unexpected.

Next, we can adopt the same procedure as for the DG Fig. 6. Drain current of a GAA MOSFET as function of drain voltage in linear

and saturation regimes for different silicon radius. (Symbols) 3-D simulations.

MOSFET and calculate the current versus applied potentials (Lines) Model.

directly from relation (12). In this case, the equivalent width

will be half the silicon wire perimeter, i.e., Weq = RSi , B. Comparison With 3-D TCAD Simulations

implying that the normalizing factor for the current becomes As for the QG MOSFET, we ran TCAD simulations for the

RSi current versus gate and drain voltages. Since the solution used

ISP = 4 Cox UT 2 . (19) in (20) is now exact, we expect to have very good predictions of

L

the model. This is indeed the case for the wire radius of 10, 20,

Moreover, the normalized current is still given by and 30 nm, where the model is very accurate (see Figs. 5 and 6).

A slight underestimation of the current at relatively high VDS

ID CSi Cox is reported.

i= = qm + 2 qm + 2

2

ln 1 qm

ISP Cox 2 CSi In conclusion, as far as the gate oxide thickness is uniform,

(20) the equivalent thickness has proven to be able to simulate

nonplanar multigate geometries with great accuracy. The case

and still, qm = 2 qg .

of nonconstant oxide capacitance is however important and

These strong similarities between DG and GAA MOS-

merit some attention. We propose to address this nonideal case

FETs lead to a unique formalism for both chargevoltage and

in the next section

currentvoltage relationships. Then, considering the correct

definition of the gate oxide capacitance, it comes out that the

V. L IMITS OF THE E QUIVALENT-T HICKNESS C ONCEPT

electrical characteristics of a GAA with radius RSi can be

AND N EED FOR AN E QUIVALENT C APACITANCE : T HE

predicted from a planar DG model using equivalent geometrical

C ASE OF PARTIALLY SG FETS

parameters Teq = RSi and Weq = RSi .

It is worth noticing that this apparently worst case in terms A. Nonuniform Gate Oxide Thickness

of departure to an ideal 1-D system can be exactly solved by

When the gate is not uniform all around the channel, as for

adopting the generic formalism when relying on the equivalent

DG FinFETs [see Fig. 1(f)] or TG MOSFETs [see Fig. 1(c)],

thickness definition.

CHEVILLON et al.: EQUIVALENT THICKNESS AND CAPACITANCE TO MOSFETs MODELING 65

interface will appear for the same gate voltage.

Besides, in strong inversion, since qm is assumed not to

depend on the gate oxide thickness, so will be the normal-

ized current iSI ,which, in strong inversion, is approximated

by qm 2 + 2 qm . This means that the total current in strong

inversion ID SI for the DG FinFET can be expressed via the sum

of specific current ISP for each channel, i.e.,

Fig. 7. Equivalent oxide capacitance network of the DG FinFET. Since the specific current for a given interface is ISP = 4

Coxinterface UT 2 (Winterface /L), from relation (21a), we

care must be taken since the gate capacitance is no longer obtain

constant. In the weak inversion regime, if we assume that

4 UT 2 HSi

flatband happens in the whole volume of the silicon (we will ID SI = iSI 2 Cox + Cox_top_eq

see to what extent this is justified), this topology is expected to L 2

give the same current as for the QG since it only depends upon WSi WSi

the cross-section area of the silicon channel. + Cox_bottom . (21b)

2 2

However, in strong inversion, the smaller gate perimeter

around the channel implies that the ON-state current will be Or equivalently

decreased in regard to the QG. If we assume that the nongated

Weq

Si/SiO2 interfaces will not experience inversion, the equivalent ID SI = iSI 4 Cox_eq UT 2 (22)

L

thickness and the equivalent width can be defined by taking the

silicon perimeter covered by the thin gate oxide layer instead of where Weq = HSi + WSi , and Cox_eq is an equivalent gate

using the entire perimeter in (3). oxide capacitance given by

TG MOSFET: Therefore, a TG model can be derived from

the generic SG model introduced in Section III, by considering Cox HSi +Cox_top_eq WSi /2+Cox_bottom WSi /2

Cox_eq = .

that geometrical parameter P is the perimeter of the silicon HSi + WSi

(23)

covered by the thin gate. From their definitions, the equiv-

alent width and equivalent thickness are Weq = HSi + WSi /2 Now, let us define Cox_bottom and Cox_top_eq as the equivalent

and Teq = (2 HSi WSi )/(2 HSi + WSi ), respectively. oxide capacitance values per unit surface for the bottom and

DG FinFET: Contrary to the TG MOSFET, the DG FinFET top interfaces and Cox (= ox /Tox ) as the oxide capacitance for

has a thicker top oxide thickness called Tox_top . When this the lateral interfaces.

thickness is large enough, we can consider this device as a Therefore, adopting these new definitions, we can consider

planar DG MOSFET and model it as such. the DG FinFET as a QG with a specific current given by ISP =

However, even for an oxide layer thicker than its nominal 4 Cox_eq UT 2 ((HSi + WSi )/L).

value, the related interface could still be a conducting channel The equivalent gate oxide capacitance has been derived

when the gate bias exceeds some threshold voltage. This is under the strong inversion condition, but since the subthreshold

indeed supported by 3-D simulations. Therefore, additional charge density is almost independent of the capacitance, we can

currents located at thick oxide interfaces should also be taken still adopt the equivalent capacitance regardless of the mode of

into account when accurate modeling of non-SG architectures operation.

is carried out. The normalized current is still given by

CSi_eq Cox_eq

i = qm 2 + 2 qm + 2 ln 1 qm

B. Definition of the Equivalent Oxide Capacitance Cox_eq 2 CSi_eq

(24)

Case of the DG FinFET: Basically, if we consider that, in

strong inversion, each channel is independent, meaning that with equivalent thickness Teq = (HSi WSi )/(HSi + WSi ) and

the normal electric field at the Si/SiO2 interfaces dominates, the equivalent silicon capacitance CSi_eq = Si /Teq .

total current of the DG FinFET (see Fig. 7) can be considered Finally, the problem reverts to finding an analytical expres-

as the sum of all Si/SiO2 channel currents. sion for the individual capacitance values that come into play.

In addition, if the oxide thickness is different at each inter- Generalization: The aforementioned result can be general-

face, it will affect both the related threshold voltage and the ized to any type of FET device having a common gate with n

normalized current [see (12)]. body/oxide interfaces of length Li and capacitance Ci .

At this point, it is interesting to introduce a basic assumption In that case, if we assume that the device can be planarized so

that consists in considering that the threshold voltages for thin as to revert to a DG MOSFET, each side length will represent

and thick gate oxide interfaces will be almost the same. The half of its counterpart in DG topology (since the width of a

validity of this approximation will be discussed later. This DG is expected to be twice its geometrical size), and if we still

66 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012

C ORRESPONDENCE B ETWEEN THE G ATE S IDEWALL AND T OP OXIDE

G EOMETRIES trode) related to the buried oxide (BOX) (see Fig. 7), an expres-

sion for the position-dependent fringing capacitance between

the body and the gate, at the body/BOX interface, was proposed

by Ernst et al. [15], i.e.,

ox 1

CBG (x) = WSi . (29)

TBOX exp

TBOX x 2 1

assume a common threshold voltage, then the corresponding

from 0 to WSi /2, leading to a bottom oxide capacitance per

specific current will be the sum of all specific currents ISP_i ,

unit area given by

i.e.,

WSi

n

n

Li /2 Cox_bottom = ox

ISP = ISP_i = 4 UT 2

Ci 2

L

i=1 i=1 (WSi +2Tox )

WSi 1 exp 2tBOX 1

= 4 UT 2 Cox_eq Weq /L (25) + ln . (30)

2 TBOX exp Tox

1

TBOX

where the equivalent thickness is given by Weq = ni=1 Li /2,

i.e., consistent with the definition introduced before, and the Having defined all these terms, the total equivalent gate oxide

equivalent gate oxide capacitance per unit surface (in a DG capacitance for the DG FinFET Cox_eqDG_FinFET can be calcu-

sense) is defined as lated according to (23).

n n In the special case of a TG MOSFET, since the top gate has

Ci Li /2 i=1 Ci Li

Cox_eq = n i=1

= n . the same oxide thickness than the lateral gates, from (26) the

L

i=1 i /2 i=1 Li equivalent oxide capacitance becomes

Note that from (26), the equivalent oxide capacitance reverts to (HSi + WSi /2) Cox + (WSi /2) Cox_bottom

the mean value of the capacitance per unit surface in the context Cox_eqTG = .

HSi + WSi

of a DG formalism. (31)

Accurate Evaluation of Top and Bottom Capacitance Values

Here, it is worth noticing that, when the top and the bottom

in DG FinFETs: Whereas thin gate oxide capacitance values

capacitance are negligible, the equivalent capacitance reverts to

are well depicted by the semi-infinite capacitor model, this

oxide capacitance Cox of a planar DG MOSFET, thus proving

ideal view breaks down when the capacitor thickness becomes

the consistency of equivalent capacitance definition.

comparable to its length. This is what happens when modeling

the top gate capacitance in a DG FinFET-like device. In that

case, some special treatment is needed. For this purpose, we C. Three-Dimensional TCAD Simulations of a DG FinFET

attempted to evaluate this capacitance following the work of

Roy et al. [14] who modeled gate sidewall capacitance, given Fig. 8 shows the current of a DG FinFET versus the gate

that the actual configuration of the sidewall oxide capacitance voltage, at low (0.1 V) and high (1 V) drain voltages, for

is almost the same. The correspondences with [14] are listed in channel length L = 1 m, silicon height HSi of 60 nm, silicon

Table I. width WSi of 20 nm, top oxide thickness Tox_top of 50 nm,

Following [14], the scaling factor becomes lateral oxide thicknesses Tox of 1.5 nm, and BOX thickness

TBOX of 30 nm.

2

Tox_top 2 W4SI + Tox WSI For this structure, we find the following equivalent quantities:

= . (26)

2

Tox 2 Tox_top 2 + Tox 2 + W4SI + Tox WSI Teq = 15 nm, Weq = 80 nm, Tox_eq = 1.88 nm, and

ISP = 4 ox /Tox_eq UT 2 Weq /L.

Moreover, the approximated sidewall oxide capacitance per unit

area, which takes into account only the normal electric field, is Two different models are compared with the 3-D simulations

given by of the current. If we consider the DG FinFET as a purely

DG MOSFET, i.e., we ignore the thick oxide interfaces, we

1 1 2

Cox_top_lateral = ox ln (27) observed that the current density is slightly underestimated

k WSI by the model in strong inversion. This mismatch comes from

the current originating from the top and bottom interfaces that

with k = 1 + 2 ( 2 + ). should indeed be taken into account.

Based on this analysis, the equivalent gate oxide capacitance On the other hand, the model including an equivalent oxide

for the top interface can be calculated as capacitance in a QG topology (which is closer to that of the

WSi Cox_top + WSi Cox_top_lateral FinFET) does not show this deviation and is found to be

Cox_top_eq = . (28) in very good agreement with 3-D TCAD simulations. This

WSi

CHEVILLON et al.: EQUIVALENT THICKNESS AND CAPACITANCE TO MOSFETs MODELING 67

Fig. 8. Drain current of a DG FinFET as a function of gate voltage in Fig. 10. Drain current of a TG MOSFET as a function of gate voltage in linear

linear and saturation regimes with a 50-nm top oxide thickness. (Symbols) and saturation regimes. (Symbols) 3-D simulations. (Dashed lines) TG model.

3-D simulations. (Dashed lines) DG model. (Solid lines) QG model with the (Solid lines) QG model with the equivalent oxide capacitance.

equivalent oxide capacitance.

Fig. 9. Drain current of a DG FinFET as a function of gate voltage in linear linear and saturation regimes. (Symbols) 3-D simulations. (Lines) Model.

and saturation regimes for different silicon width WSi with a 50-nm top oxide

thickness. (Symbols) 3-D simulations. (Lines) QG model with the equivalent to predict the electrical behavior of a long-channel bulk FinFET

oxide capacitance. without the need for any additional parameters.

VI. VALIDITY OF THE M ODEL FOR

interfaces, which are taken into account without introducing

H IGH -T EMPERATURE O PERATION

any empirical parameter or smoothing function, must be part of

the model. At this point, it is worth noticing that the equivalent In this section, we propose an extension to the temperature

oxide thickness is involved in all operating regime of the device dependence for the multigate model. To the initial DG model

but does not affect the weak inversion operation in regard to the [2], we add a mobility model depending on the transverse

DG model, which is indeed what we would expect. electric field and on the temperature. We present a validation

Fig. 9 shows the results obtained with the DG FinFET model of the model with 3-D TCAD simulations of DG FinFET,

for whether a thin silicon body or a large one, i.e., having a TG, and GAA MOSFETs, for temperatures varying from 275

value close to the silicon height. For the TG MOSFET, the to 425 K. Finally, the model will be assessed with electrical

current that arises from the thick oxide thickness interfaces measurements of a TG MOSFET for temperatures between

is well accounted by the fringing gate capacitance proposed 273.15 and 373.15 K.

so far (see Figs. 10 and 11). For both DG FinFETs and TG

MOSFETs, combining the planar and the fringe capacitance is

A. Modeling

thus fully justified and validates the concept of an equivalent

oxide capacitance for multigate MOSFETs compact modeling According to the long-channel DG model defined in [2],

with arbitrary geometries. Finally, without entering into the de- if we assume a constant mobility (and independent of the

tails, the model was also able to correctly predict bulk FinFET temperature), the effect of the temperature should already be

characteristics, i.e., DG FinFET without bottom oxide. Indeed, part of the model through intrinsic concentration ni and thermo-

we found that the TG model (presented in Section V-A) is able dynamic voltage UT , which are included in the normalization

68 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012

TABLE II

D ESCRIPTION OF THE M ODEL PARAMETERS

voltage. On the other hand, also the energy gap of the silicon

(used to calculate the intrinsic carrier concentration) and the

dielectric constants depend on the temperature. However, these

contributions can be considered as second-order effects, and

therefore, these will be set to their values at 300 K.

The mobility model that we propose is adapted from the

model of Jeon and Burk [16]. This model is based on the recip-

rocal sum (Matthiessen rule) of three scattering mechanisms,

i.e., the phonon, Coulomb, and surface roughness scattering.

It explicitly depends on temperature T through the phonon

and Coulomb scattering and on transverse electric field Ee

through the phonon and surface roughness scattering. Since

at high temperature Coulomb scattering is negligible [16], we

keep only the phonon and roughness scattering terms, leading

Fig. 12. Drain current of a GAA MOSFET as a function of gate voltage

to [16] in linear and saturation regimes for different temperatures. (Crosses) 3-D

simulations. (Lines) Model.

1

= . (32)

a2 Tn Ee 1/

+ a3 Ee 2 phonon scattering coefficients are n = 1.3 and = 2, and the

low-field mobility extracted at 300 K is 0 = 1350 cm2 /V s.

Furthermore, in weak inversion, the electric field tends to

Fig. 12 compares 3-D TCAD simulations with the model for

zero and mobility would diverge, whereas we expect it to reach

the drain current versus the gate voltage in a 20-nm silicon

an asymptotic low field value. To remove this inconsistency, a

radius GAA MOSFET (both for VD = 0.1 and 1 V). The degra-

new parameter, i.e., a0 , was introduced. After transformation,

dation of the subthreshold slope, threshold voltage, and low-

we get

field mobility when the temperature is increased are accurately

a0 1 T n predicted. In strong inversion, the mobility degradation with

= (33) temperature is well taken into account both for high and low

1 + E0 Ee 1/ + E1 Ee 2 T n

drain voltages. Fig. 13 confirms that the model is still in good

where Ee is the transverse electric field calculated as in [17], agreement with full 3-D simulations at 400 K.

E0 and E1 are empirical parameters, and the low-field mobility The model accuracy for different geometries, i.e., DG Fin-

is 0 = a0 1 T n , with = 3 6 and n = 1 1.5 according FET, TG, and GAA MOSFETs, is summarized in Table III. In

to [16] (note that these are not intrinsic model parameters). addition, it is worth mentioning that Io (= ID (VGS = 0 V))

Concerning saturation effect, we adopt the model we intro- and Ion (= ID (VGS = 1 V)) are well estimated by the model.

duced in [17], which depends on the channel charge density,

mobility, and saturation velocity. In order to have a complete

temperature-dependent model, we followed the approach of

C. Model Validation With Measurements

Quay et al. [18], which also gives temperature dependence for

the saturation velocity. Table II shows all the parameters that Measurements were done in framework of the COMON

need to be extracted for long-channel devices. project on TG MOSFETs having gate lengths ranging from

70 nm to 1 m, Fin width WSi of 30 nm, and Fin height HSi

of 60 nm. The devices were processed with a SiON gate stack

B. Validation by 3-D TCAD Simulations

and TiN midgap gate electrode [14]. The oxide thickness was

We have studied the behavior of multigate devices for tem- approximately 1.9 nm. The results shown in this letter are for a

peratures ranging from 275 to 425 K. In the mobility model, the 1-m device length. Following the method developed in [19],

CHEVILLON et al.: EQUIVALENT THICKNESS AND CAPACITANCE TO MOSFETs MODELING 69

Fig. 13. Drain current of a GAA MOSFET as a function of drain voltage in Fig. 14. Drain current of a TG MOSFET as a function of gate voltage in linear

linear and saturation regimes. (Circles) 3-D simulations. (Lines) Model. and saturation regimes. (Crosses) Measurements. (Lines) Model.

TABLE III

M EAN VALUE FOR THE R ELATIVE E RROR IN P ERCENT B ETWEEN 3-D

TCAD S IMULATIONS AND THE M ODEL OF Ion AND Io C URRENTS ON A

275- TO -425-K T EMPERATURE R ANGE . T HESE R ESULTS A RE G IVEN FOR

D IFFERENT G EOMETRY OF DG F IN FET, TG, AND GAA MOSFET S

we have extracted effective channel length Le = 0.9 m Fig. 15. Drain current of a TG MOSFET as a function of drain voltage in lin-

and series resistance RSD298.15 K = 1300 at room temper- ear and saturation regimes for different temperatures. (Circles) Measurements.

ature. By extracting the series resistance for different tem- (Lines) Model.

peratures, we obtained a linear variation given by RSD (T ) =

RSD298.15 K [1 + aT (T 298.15)] with aT = 0.0108. age mechanisms exist such as the gate induced drain leakage

Comparisons Between Model and Measurements: Since the (GIDL) [20], the gate leakage, and the trap-assisted tunneling

model presented so far focuses on the intrinsic device prop- process [21]. In strong inversion, the good predictions of the

erties, additional extrinsic parameters related to the mobility model for low and high drain voltages justify the temperature-

dependence and access resistances should be taken into account dependent mobility relationship adopted here.

to simulate a real device. Without entering into the details, Fig. 15 shows the drain current versus the drain voltage

we give hereafter the main values that were obtained. For for Vg = 1 V at different temperatures. The saturation regime

the mobility coefficients and low-field mobility 0 at room is well modeled, as is the current in the linear region, also

temperature, we found n = 1.3, = 2, and 1350 cm2 /V s. meaning that the series resistance variation with temperature

Fig. 14 compares the measurements and the multigate model seems reasonable.

for the drain current versus the gate voltage at VD = 0.05 So far, the core model was mainly validated for long-channel

and 1 V and for temperatures between 273.15 and 373.15 K. multigates. Concerning short-channel devices, we expect that,

The subthreshold slope and the threshold voltage predicted by to some extent, the present model can inherit from some

the model are in good agreement with the measurements in the developments done for DG FinFETs [17], i.e., by using the

whole temperature range. For gate voltages close to 0 V, we potential minimum approach. However, for certain geometries

observe some mismatch between the model and the measure- such as TG and QG FETs, a more physical approach might be

ments, which is attributed to current leakage mechanisms that needed by considering corner effects and real 3-D topologies,

are not included in the model. as recently addressed in [22]. It is very likely that merging the

Most likely, at high temperature, the Io current is dominated work done in [22] with our core model will allow including

by channel leakage (in this case, the leakage current at the drain short channel effects while keeping a physically based model

is the same than the one at the source). However, several leak- with a minimum number of parameters.

70 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 1, JANUARY 2012

VII. C ONCLUSION [16] D. S. Jeon and D. E. Burk, MOSFET electron inversion layer

mobilitiesA physically based semi-empirical model for a wide tempera-

In this letter, we demonstrated how a multigate FET topology ture range, IEEE Trans. Electron Devices, vol. 36, no. 8, pp. 14561463,

having a common gate electrode could be merely considered as Aug. 1989.

[17] A. Yesayan, F. Prgaldiny, N. Chevillon, C. Lallement, and J.-M. Sallese,

a symmetric DG MOSFET through the definition of an equiv- Physics-based compact model for ultra-scaled FinFETs, Solid State

alent silicon thickness, an equivalent gate oxide capacitance, Electron., vol. 62, no. 1, pp. 165173, Aug. 2011.

and an equivalent channel width. All these transformations are [18] R. Quay, C. Moglestu, V. Palankovski, and S. Selberherr, A temperature

dependent model for the saturation velocity in semiconductor materials,

explicit and only rely on physical and technological parameters, Mater. Sci. Semicond. Process., vol. 3, no. 1/2, pp. 149155, Mar. 2000.

with no empirical relationships. The ability of the model to [19] G. Niu, J. D. Cressler, S. J. Mathew, and S. Subbanna, A channel resis-

predict charge densities and current up to 425 K confirms tance derivative method for effective channel length extraction in LDD

MOSFETs, IEEE Trans. Electron Devices, vol. 47, no. 3, pp. 648650,

the quite strong physical roots of this approach. In addition, Mar. 2000.

provided a temperature-dependent mobility was introduced, [20] J.-H. Chen, S.-C. Wong, and Y.-H. Wang, An analytic three-terminal

which is anyway required for real devices, the model was also band-to-band tunneling model on GIDL in MOSFET, IEEE Trans. Elec-

tron Devices, vol. 48, no. 7, pp. 14001405, Jul. 2001.

able to simulate measurements of a TG MOSFET at various [21] T.-E. Chang, C. Huang, and T. Wang, Mechanisms of interface trap-

temperatures. Based on these equivalence between planar DG induced drain leakage current in off-state n-MOSFETs, IEEE Trans.

and multigate FETs, any geometry can now be modeled with Electron Devices, vol. 42, no. 4, pp. 738743, Apr. 1995.

[22] R. Ritzenthaler, F. Lime, B. Iiguez, O. Faynot, and S. Cristoloveanu, 3-

a common formalism. Additional work is needed to take into D analytical modelling of subthreshold characteristics in Pi-gate FinFET

account short-channel effects and quantum corrections. transistors, in Proc. Solid-State Device Res. Conf., 2010, pp. 448451.

R EFERENCES

Nicolas Chevillon was born in Dijon, France, in

[1] B. Yu, H. Lu, M. Liu, and Y. Taur, Explicit continuous models for double- 1982. He received the M.S. degree in micro- and

gate and surrounding-gate MOSFETs, IEEE Trans. Electron Devices, nanoelectronics from the University of Strasbourg,

vol. 54, no. 10, pp. 27152722, Oct. 2007. Strasbourg, France, in 2008. He is currently working

[2] J.-M. Sallese, F. Krummenacher, F. Prgaldiny, C. Lallement, A. Roy, and toward the Ph.D. degree at the Institut dlectronique

C. Enz, A design oriented charge-based current model for symmetric du Solide et des Systmes, Centre National de la

DG MOSFET and its correlation with the EKV formalism, Solid State Recherche Scientifique, University of Strasbourg.

Electron., vol. 49, no. 3, pp. 485489, Mar. 2005. His current research interests include FinFET

[3] J.-P. Colinge, Multiple-gate SOI MOSFETs, Solid State Electron., compact modeling, 3-D simulations, and parameter

vol. 48, no. 6, pp. 897905, Jun. 2004. extraction.

[4] K. von Arnim, E. Augendre, A. C. Pacha, T. Schulz, K. T. San, F. Bauer,

A. Nackaerts, R. Rooyackers, T. Vandeweyer, B. Degroote, N. Collaert,

A. Dixit, R. Singanamalla, W. Xiong, A. Marshall, C. R. Cleavelin,

K. Schrufer, and M. Jurczak, Low-power multi-gate FET CMOS technol-

ogy with 13.9 ps inverter delay, large-scaled integrated high performance Jean-Michel Sallese received the M.Sc. degree from

digital circuits and SRAM, in VLSI Symp. Tech. Dig., 2007, pp. 106107. the Institut National des Sciences Appliques, Lyon,

[5] Intel Announcement for Microprocessor Production With 22 nm France, and the Ph.D. degree in physics from the

FinFET Technology. [Online]. Available: http://newsroom.intel.com/ University/CNRS of Nice Sophia Antipolis, Nice,

community/intel_newsroom/blog/2011/05/04/intel-reinvents-transistors- France, where he worked on deep levels character-

using-new-3-d-structure ization in semiconductors.

[6] B. Yu, J. Song, Y. Yuan, W.-Y. Lu, and Y. Taur, A unified analytic In 1991, he joined the Swiss Federal Institute of

drain-current model for multiple-gate MOSFETs, IEEE Trans. Electron Technology (cole Polytechnique Fdrale de Lau-

Devices, vol. 55, no. 8, pp. 21572163, Aug. 2008. sanne), Lausanne, Switzerland, where he was en-

[7] R. Ritzenthaler, F. Lime, B. Iiguez, E. Miranda, F. Martinez, F. Pascal, gaged in semiconductor laser diodes characterization

M. Valenza, O. Faynot, and S. Cristoloveanu, Analytical modeling of and modeling. He is currently giving lectures on

multiple-gate MOSFETs, in Proc. Spanish Conf. Electron Devices, 2011, advanced semiconductor devices as and his research activities focus on compact

pp. 14. modeling of multigate MOSFETs and modeling of microelectromechanical

[8] J.-M. Sallese, N. Chevillon, F. Prgaldiny, C. Lallement, and B. Iiguez, systems.

The equivalent-thickness concept for doped symmetric DG MOSFETs,

IEEE Trans. Electron Devices, vol. 57, no. 11, pp. 29172924, Nov. 2010.

[9] W. Xiong, J. W. Park, and J. P. Colinge, Corner effect in multiple-gate Christophe Lallement (M96) received the M.S.

SOI MOSFETs, in Proc. SOI Conf., 2003, pp. 111113. degree in engineering from Science University of

[10] Atlas/Silvaco Manual. [Online]. Available: www.silvaco.com Nancy I, Nancy, France, and the Ph.D. degree in

[11] K. E. Moselund, D. Bouvet, L. Tschuor, V. Pott, P. Dainesi, and engineering from cole Nationale Suprieure des

A. Ionescu, Local volume inversion and corner effects in triangular gate- Tlcommunications, Paris, France.

all-around MOSFETs, in Proc. Solid-State Device Res. Conf., 2006, From November 1994 to September 1997, he

pp. 359362. was a Postdoctoral Research Scientist with the Lab-

[12] B. Iguez, D. Jimnez, J. Roig, H. A. Hamid, L. F. Marsal, and J. Pallars, oratory of Electronics, Swiss Federal Institute of

Explicit continuous model for long-channel undoped surrounding gate Technology, Lausanne, Switzerland, working on the

MOSFETs, IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 18681873, characterization and modeling of the MOSFET tran-

Aug. 2005. sistor in the development team of the EKV MOST

[13] P. L. Chambr, On the solution of the PoissonBoltzmann equation with model. In September 1997, he was an Associate Professor with the University

application to the theory of thermal explosions, J. Chem. Phys., vol. 20, of Strasbourg, Strasbourg, France, and the CNRS Laboratory for Physics and

no. 11, pp. 17951797, Nov. 1952. Applications of Semiconductors. Since September 2003, he has been a Profes-

[14] A. S. Roy, C. Enz, and J.-M. Sallese, Compact modeling of gate sidewall sor with the cole Nationale Suprieure de Physique de Strasbourg, Illkirch,

capacitance of DG-MOSFET, IEEE Trans. Electron Devices, vol. 53, France. His current research works, currently at the Institut dlectronique du

no. 10, pp. 26552657, Oct. 2006. Solide et des Systmes (InESS), focus on the study and modeling of advanced

[15] T. Ernst, R. Ritzenthaler, O. Faynot, and S. Cristoloveanu, A model of devices, mixed-signal systems with VHDL-AMS, and biosynthetic systems.

fringing fields in short-channel planar and triple-gate SOI MOSFETs, He is responsible for the group Heterogeneous systems and microsystems

IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 13661375, Jun. 2007. at InESS.

CHEVILLON et al.: EQUIVALENT THICKNESS AND CAPACITANCE TO MOSFETs MODELING 71

Fabien Prgaldiny was born in France, in 1977. Josef Sedlmeir studied physics at the Technical Uni-

He received the M.S. and Ph.D. degrees in micro- versity, Munich, Germany, and received the Ph.D.

electronics from the University of Strasbourg (UdS), degree in condensed matter physics with nuclear

Strasbourg, France, in 2001 and 2003, respectively. methods, in 1992.

His doctoral research pertained to the modeling He worked in high energy physics (silicon de-

and simulation of deep-submicrometer MOSFETs. tectors) at Max-Planck-Institute, Munich/CERN, and

Since 2004, he has been an Associate Professor at Brookhaven National Laboratory, Upton, NY. In

with the cole Nationale Suprieure de Physique 1999, he joined Infineon Technologies, Munich, as

de Strasbourg, Illkirch, France, and the UdS, where a Device Characterization Engineer, working on the

he also joined the Institut dlectronique du Solide electrical characterization and compact modeling of

et des Systmes, Strasbourg, in 2005. His research advanced CMOS technologies. In February 2011, he

interests focus on compact modeling and simulation of a double-gate MOSFET, moved to Intel Mobile Communications, Neubiberg, Germany.

FinFET, and CNTFET. He is also interested in the use of the VHDL-AMS

hardware description language in compact modeling.

Morgan Madec was born in 1980. He received the Jasmin Aghassi received the diploma degree in

M.S. and Ph.D. degrees in microelectronics from the physics from Technical University of Aachen,

University Louis Pasteur (ULP), Strasbourg, France, Aachen, Germany, in 2004 and the Ph.D. degree in

in 2003 and 2006, respectively. theoretical condensed matter physics from the Uni-

From 2003 to 2006, he was with the Laboratoire versity of Karlsruhe, Karlsruhe, Germany, in 2007,

de Physique et Application des Semi-Conducteurs, where she worked on electronic transport in semi-

ULP Centre National de la Recherche Scientifique, conductor quantum dots.

Strasbourg, where he prepared a Ph.D. thesis on In November 2007, she joined Infineon Technolo-

the design and characterization of optical processors gies AG as a Research and Development Engineer,

in order to speed up image reconstruction in the working on advanced CMOS technologies. Her main

medical ?eld. He is currently an Associate Profes- fields of interests include compact modeling and

sor with the cole Nationale Suprieure de Physique de Strasbourg, Institut electrical characterization of submicron MOSFETs and quantum effects. Since

dlectronique du Solide et des Systmes, Universit de Strasbourg, Strasbourg, February 2011, she joined Intel Mobile Communications GmbH, Neubiberg,

where he teaches electronics. His research interests include compact modeling Germany, where she is now a Project Manager for CMOS technology platform

of integrated microsensors. development.

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