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Differential Protection in
Low-Voltage Buses
AN EXPLORATION OF PRINCIPLES AND MODELS

photocredit

By Lubomir Sevov Current-differential principles are well known

and Marcelo Valdes and commonly used for the protection of medium and large
transformers, large motors, medium-voltage (MV) generators,
MV and high-voltage buses, and any type of important power
equipment with measurable input and output currents. How-
ever, is it practical to protect low-voltage (LV) distribution buses
using differential protection? This article describes bus differ-
Digital Object Identifier 10.1109/MIAS.2016.2600688
Date of publication: 27 June 2017 ential protection principles as well as interlocking principles

2 IEEE Industry Applications Magazine september/october 2017 1077-2618/172017IEEE

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for overcurrent protection. We discuss specific issues in
applying differential protection in LV systems. Addition-
ally, we present a concept of partial differential (PD)
protection, which can be used in conjunction with zone-
selective interlocking (ZSI) or as backup to traditional
overcurrent protection to achieve high-speed and selective
fault clearance. Additional concepts for the implementa-
tion of bus differential protection using networked data in
LV systems are introduced.
Overview of Bus Protection
Buses in LV power systems are the location where sources
and distribution loads converge. Short circuits located
on or near the bus tend to have very high magnitude
currents that require a high-speed protection operation
to limit equipment damage and mitigate the arc-flash
hazard. However, high-speed clearing must be balanced
against the need for security. Tripping incorrectly at a
main bus can cause costly interruptions. High fault cur-
rent increases the possibility of current transformer (CT)
saturation during external or internal faults close to the
bus and, consequently, the possibility of incorrect bus-
protection operation.
Optimum bus protection may be complex and need to
accommodate multiple topologies. In LV systems, there
may be multiple connected sources and ties as well as
feeders that may open or conduct in either direction.
Sources that may or may not be energized simultaneously,
motor loads that can regenerate under fault conditions,
temporary sources during emergency situations, or trans-
formers with insufficient primary protection also present
protection challenges.
Modern protection and communication technology
provides various protection alternatives, such as differ-
ential protection, PD protection, blocking schemes, and
combinations of these. Economic, application, mainte-
nance, reliability, safety, and logistical factors affect the
suitability of any one solution in any given situation. The
following sections review the various bus differential and
blocking schemes that are commonly used as well as a
hybrid scheme specifically suggested by the authors for
LV buses.
Protection requirements combined with electrical sys-
tem characteristics require different levels of sensitivity
and speed. Different system missions require or accept
varying levels of reliability. Safety, equipment size, and
cost must also be considered.
Review of Bus Differential Protection Principles
To improve upon selectively set nested timecurrent
curves, there are various types of overcurrent protection
enhancements available to improve protection and main-
tain good system selectivity. Differential protection and
zone interlocking (also known as the blocking technique)
are the two types of overcurrent protection enhancements
commonly used.
Kirchhoffs First Law
A differential scheme relies on a fundamental principle
of electrical engineering, i.e., Kirchhoffs first law, which
states that the sum of currents in a network of conduc-
tors meeting at a point (or node) is zero. Any net nonzero
current measured by the scheme represents one of three
things or the combination of these three things:
1) a measurement error that results in a false nonzero
current
2) a load or normal current not being measured, such as
a bus-connected control power transformer
3) a fault current exiting the node that is not being directly
measured and, hence, being identified by the summa-
tion through the exclusion of the measurement.
The error in modern measurement systems may not
be significant, or it is easily accommodated by desensi-
tizing the threshold by a fixed amount. CT saturation,
when currents are large due to a normal inrush or dc
offset during fault conditions outside the protected zone,
may present a more complex challenge. If not addressed,
an error can cause false fault detection. The complex-
ity of differential relaying is exacerbated by the need to
minimize and account for measurement error caused by
CT saturation when large currents flow into or through
the protected zone or for a variety of reasons intrinsic to
iron-core CTs.
ZSI Schemes
A simple chronometrically coordinated (coordinated via
time measurement and current threshold, i.e., nested
timecurrent curves) protection scheme for a distribu-
tion bus can be improved by the addition of a blocking
scheme to remove the effect of the required coordination
delays from the protection time. ZSI, as it is normally
called in LV applications, or blocking, as it is called in MV
applications, operates very similarly in LV and MV sys-
tems, whether implemented in discrete relays or integral
LV trip units. Discrete overcurrent relays or integral trip
units (which are standard in LV applications) are placed
on incoming circuits, including ties, and at all outgo-
ing feeders. The feeder protection overcurrent thresh-
olds are set to sustain expected loads, coordinate with
downstream circuits, and detect faults. The overcurrent
thresholds on the incoming circuit are set as sensitively
as possible but are coordinated with downstream thresh-
old and busload needs. In-zone protection delays (unre-
strained) are set as fast as the blocking scheme allows
to protect the main bus quickly, unless it is blocked
(restrained) by any of the feeder overcurrent devices.
The signal from lower-tier devices (e.g., downstream
feeders) is communicated to upper-tier devices (e.g.,
upstream mains or ties); see Figure 1. The signal (which
is called a blocking or restraint signal) is used to arbitrate
the delays and, in some cases, the threshold or shape of
the curve implemented in the upper-tier protection. When
a blocking signal is received by the upper-tier device, this
september/october 2017 IEEE Industry Applications Magazine 3
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50
50 50 50 50
FIGURE 1. The ZSI scheme. A lower-tier device sends a blocking
signal to an upper-tier device.
upper-tier device is told that the fault is detected and is
being interrupted by a lower-tier device, hence it need
not operate at its in-zone protection speed. The upper-tier
device then applies a delay, which is usually user set, to
allow the lower-tier device to respond and clear the fault.
The upper-tier device is not usually made to be totally
unresponsive to the fault, it is just slowed enough to allow
the lower tier to interrupt first. The upper-tier device
remains poised to provide backup protection should
the lower-tier devices fail to clear the fault. In protec-
tion relays typically used for MV system protection, the
slower alternate protection in the upper-tier device may be
enabled via an alternate setting group. The signal may be
a simple hardwired contact closure or a voltage provided
by the downstream device, as is the case in some LV trip
units. Different manufacturers will use different signals
between their devices; and, hence, devices from different
manufacturers are rarely compatible. Some devices may
implement differentiated signals for different protection
functions, such as ground-fault protection and overcur-
rent protection. In some applications, especially with
modern digital relays, serial communications may be used
to transmit a signal over longer distances. A requirement
for this type of scheme to function is that the lower-tier
(downstream) device issues the blocking signal before
the upper-tier (upstream) device commits to tripping.
In some cases, that may mean that the upstream device is
not able to operate at its fastest protection mode to allow
time to receive the blocking signal.
When using microprocessor-based multifunctional
relays, it may become possible to integrate all of the
required overcurrent functions for one or more cir-
cuits in one relay. This not only allows a reduction in
wiring but also shortens the coordination time and
speeds up the operation of the scheme. When using
one relay for multiple protection modes or multiple
circuits, consideration should be given to reliabil-
4 IEEE Industry Applications Magazine september/october 2017
ity implications and the value of having redundant or
backup protection.
One microprocessor-based relay can have multiple
current inputs and can be connected to the CTs from
multiple circuits. These relays have more than one over-
current function and can implement multiple protection
functions simultaneously using the same current signals
Block
in multiple ways. One relay can implement overcurrent
functions 50and 51 as well as differential functions with
50 the various circuits and an interlocking scheme simultane-
ously. Such implementations can provide improved speed
and wiring simplicity.
Modern relays also provide fast peer-to-peer commu-
nications using protocols such as the Distributed Network
Protocol, Utility Communications Architecture, or Inter-
national Electrotechnical Commission 61850. Such com-
munications facilitate implementing schemes over longer
distances and may further simplify wiring [4], [5].
Blocking schemes, although economical and seem-
ingly easy to apply, are usually limited to simple busbar
configurations. It is complicated to implement blocking
schemes in complex systems with two or more incomers,
tie breakers, and varying topology.
Types of Differential Protection
Differential protection can be divided into the following
five types:
1) overcurrent differential that operates based on the sum
of the various currents using overcurrent relays
2) percent-slope overcurrent differential, which is differ-
ential protection that calculates a restraint value that is
dependent on the magnitude of input currents
3) low-impedance overcurrent differential with dual per-
centage differential slope plus additional mechanisms
to improve operational reliability that is relative to
sensor inaccuracy and saturation
4) high-impedance overcurrent-differential function that
routes the summed current from the circuit CTs through
a resistor network to develop a voltage.
5) networked differential relays that receive synchro-
nized, digitized information over communication lines.
The following sections of the article will describe these
relay types in more detail.
Simple Unrestrained Differential
In a simple differential-relay implementation using an
overcurrent protection element, the differential current
may be created externally to the relay by summation
of all the circuit currents via parallel interconnection
of the various CTs (Figure 2). The external CTs should
be of the same ratio and type. If they are not, a scal-
ing (matching) CT (or several) is needed. This, in turn,
may increase the burden for the main CTs and increase
saturation concerns.
CT saturation and inaccuracy are handled via a
high operational threshold and time delay. This
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implementation can also be accomplished with multiple

CT inputs into a digital relay (Figure 3). An instanta-
neous overcurrent (IOC) function 50 may be too sensi- Main Fdr 1 Fdr 2 Fdr N
...
tive to the measurement error if there are many CTs or CB CB CB CB
if excessive error due to saturation is expected.
Simple differential protection may also be imple- 51 IAM + IAF1 + IAF2 + + IAFN
IAM IAF1 IAF2 IAFN
mented via microprocessor-based electronic relays that
allow multiple CT sets to be connected to the same relay.
These relays may accommodate different CT ratios and
may or may not implement additional logic, such as a FIGURE 2. A simple differential function implemented with overload
relay. Each phase current is summed independently. CB: circuit
percentage differential restraint slope to address CT
breaker; Fdr: feeder.
error caused by a high current or to implement delayed
instantaneous algorithms.
In the case of an unrestrained differential function, the
differential element should be set above the maximum
differential currents that may exist due to control power Main Fdr 1 Fdr 2 Fdr N
...
loads or expected false differential measurement caused CB CB CB CB
50/51
by sensor mismatching or error. This simple differential
function may provide adequate, fast differential protection Overcurrent with
if there are not too many CTs contributing to the potential Multiple CT Inputs
Used for
error simultaneously. For buses with a limited number IAM
Differential
of CTs that are able to implement them with a lower IAF1
Protection
IAF2 I
maximum fault current/CT ratio, it may be possible to AFN

use an electronic overcurrent relay in lieu of a dedicated

differential relay.
Low-Impedance-Percentage Differential Relay
The percentage differential relay creates a restraining
and differential signal to provide a variable threshold
(restrained threshold) characteristic. It can be thought of
as changing the protection threshold to insulate it against
possible errors caused by sensing distortion under high
currents. This variable restraint signal is not the logical
blocking signal used in ZSI schemes, which is also called
a restraint signal. Differential percentage restraint signals
may be based on the sum, average, or maximum of the
measured bus currents. As measured currents get larger,
the restraint signal increases and is used to desensitize
the differential threshold to prevent nuisance opera-
tion due to CT saturation or error. The restraint transfer
function may be represented by a slope characteristic,
proportional to some function of measured bus currents.
Equation (1) is the sum that represents the calculated
differential current. Equations (2) and (3) are alternative
methods to change the threshold to which the result of
(1) is compared to determine if a fault exists.
I diferential = I 1 + I 2 + g + I n (1)
I restraint = max ^ I 1 , I 2 , ..., I n h(2)
FIGURE 3. A differential function with electronic multi-CT
overcurrent relay.
relays. In modern electronic relays, this low-impedance
approach does not require dedicated CTs, it can tolerate
substantial CT saturation, and it provides high-speed trip-
ping. The protection of variable-bus topology is possible
as the CT topology can be varied via software to match
actual circuit topology as varying sources, varying loads,
and ties with an opened or closed status during systems
operation.
Modern Low-Impedance Bus Differential Relays
The low-impedance approach used to be perceived as
less secure when compared with high-impedance protec-
tion (see Figure 4). This is no longer true as sophisticated
algorithms in microprocessor-based relays match high-
impedance performance, and, simultaneously, cost consid-
erations make the high-impedance scheme less attractive.
Also, complex buses cannot be handled well by high-
impedance schemes.
Modern microprocessor-based, low-impedance busbar
relays are developed with two architectures, i.e., distribut-
ed or centralized. They provide the following advantages:
no need for dedicated CTs
automatic CT ratio compensation

I restraint = I 1 + I 2 + g + I n .(3) advanced algorithms supplement the percentage differ-

ential protection function, making the relay very secure

Relays that process current inputs and implement able to protect reconfigurable busbars, as the dynam-

increasing levels of sophistication to increase opera- ic bus replica (bus image) can be accomplished in
tional reliability, such as percentage differential slopes, software without physically switching secondary
may be called low-impedance-percentage differential current circuits

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in Figure 5. The slope creates two regions: the upper

region defines operation, and the lower region defines
Main Fdr 1 Fdr 2 Fdr N no operation. The differential pickup setting should be
...
CB CB CB CB 87 high enough to ride through differential signals caused
Static Differential by measurement errors, unmeasured loads such as con-
Relay with trol power transformers, and other errors that may arise
Percentage Restraint when the bus carries a light load and there is no effective
IAM and Additional
IAF1 differential-restraining signal.
Directional,
IAF2 IAFN Saturation, and The first breakpoint (i.e., the low breakpoint in Fig-
Time-Based Logic ure5) is provided to specify the limit of guaranteed linear
operation of the CTs in the most unfavorable conditions,
FIGURE 4. A low-impedance-percentage differential relay. such as high residual magnetism left in the magnetic cores
or multiple autoreclosure operations. This value defines
the upper limit for the application of the first, lower
|ID| slope (low slope). The second breakpoint (i.e., the high
Region 2 (Differential 2) breakpoint), farther to the right in Figure 5, is provided to
(High-Differential specify the limits of operation of the CTs with substantial
Currents) saturation. This point defines the lower limit for the appli-
Differential

High cation of the second slope (i.e., the high slope).

te
ra

Slope The higher slope acts as a percentage restraint when

pe
O

restraint currents are higher than the high breakpoint.

Region 1 (Differential 1)
The boundary of the operating characteristic in the
k

(Low-Differential
oc

higher slope region is a straight line intersecting the

Bl

Currents)
Low IR origin of the differential-restraining plane. The advan-
Slope
Pickup
Restraining tage of having a constant percentage restraint speci-
Low Breakpoint

High Breakpoint

fied by the high slope setting creates a discontinuity

FIGURE 5. A percentage differential characteristic.
integrated breaker-fail function for backup protection
distributed communication-based system architec-
tures replaces CT wires with fiber or Ethernet-type
wiring.
Algorithms for busbar protection [1] are implement-
ed by sample-by-sample comparison or the comparison
of calculated current phasors. The main difficulty in
bus differential protection is that significant differential
current may appear to be due to the saturation of CTs
on large external faults. When a CT saturates, its sec-
ondary current is not a proper replica of the primary
current. Therefore, the sum of CT secondary currents
is not equal to the sum of the primary currents, even
though the primary CT currents may sum to zero. This
can cause a differential relay to operate on external
through faults, leading to improper operation. While
the percentage differential can provide security against
normal CT errors due to a mismatch of CT turns ratio
and magnetization current, it may not be enough to
handle the severe CT saturation problem.
Dual-Slope-Percentage Differential Restraint
This bus differential protection scheme uses the double-
slope, double-breakpoint operating characteristic shown
between the first and second slopes. This is overcome
by using a smooth (cubic spline) approximation of the
characteristic between the lower and higher break-
points. The shape allows for a more precise setting of
the differential element to accommodate the expected
CT performance.
Trip/No-Trip Security Logic
To enhance security, the relays operating region is divid-
ed into two areas (Figure 5) with diverse operating modes.
The bottom portion of the characteristic applies to com-
paratively low-differential currents and has been intro-
duced to deal with CT saturation on low-current external
faults. Certain distant external faults may cause CT satura-
tion due to extremely long time constants of the dc com-
ponents or due to multiple autoreclosure operations. The
saturation, however, is difficult to detect in such cases.
Additional security is provided within this region without
the need for dedicated saturation detection.
The top region includes the remaining differen-
tial characteristic and applies to comparatively high-
differential currents. If, during an external fault, the
temporary differential measurement caused by measure-
ment error, also known as spurious differential current,
is high enough so the differential-restraining current ratio
enters the top region, then such CT saturation should be
detected by the saturation detector.
The waveforms in Figure 6 depict an external feeder
fault fed from a bus with five circuits, where two circuits
(i 1 and i 2 ) feed the fault, two other circuits are radial

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feeders that do not provide contribution, and i 5 is the

faulted circuit. This is a fault for which the relay should
i1
not operate. I d is the differential sum signal, and I r is the
restraining signal calculated by the algorithm based on i2
the maximum phase current in the zone. There are three
important time milestones shown in the figure that are i3
addressed by the algorithm to build the security required i4
i5
by the bus differential protection: the time t 0 is the nor-
mal condition at the start of fault, the time from t 0 to t 1
is the fault saturation free time, and the time from t 1 to Id
t 2 is the CT-saturation-affected time. Following the dif- Ir
ferential restraint ratio from the normal condition until
t0 t1 t2
CT saturation, the ratio trajectory (i.e., the change over
time) would be mapped on the characteristic, as shown
FIGURE 6. An external fault, CT saturation, and differential and
in Figure 7. The trajectory is the ratio of the values of restraint currents.
differential current (vertical axis) over the restraint cur-
rent (horizontal axis) from t 0 to t 2, called a trajectory
because it is a changing ratio during the first fault cycle. |ID|
The external fault trajectory pattern is used to trigger 4
(DIF2 =1 and SAT =1) High Slope

Differential Current
flags and develop security logic. In addition, the secu- Check Directional
rity and dependability of the bus differential protection 3 Flag: DIR = ? t2 DIF2 = 1
is improved by implementing fast and robust saturation
2 Operate Block
detection as well as current directional sensing.
Figure 8 depicts the adaptive logic for detecting inter- 1 Low SAT = 1
nal faults versus external through faults using the various t0 Slope IR
t1
sensing and logic mechanisms. Two internal logical flags Pickup
1 2 3 4 5 6

Low Breakpoint

High Breakpoint
are generated and used as differential supervisory logic,
Restraining Current
i.e., a saturation detection flag and a directional flag. The
directional flag indicates if all the currents are flowing
toward the bus or if at least one is not. The saturation flag
is based on the detection of a time difference between the
onset of large currents, reflected in the restraint signal, FIGURE 7. A typical differential/restraint trajectory during external
and the onset of a differential current. If the two arise fault. DIF: differential; DIR: direction; SAT: saturation.
simultaneously, the differential is assumed to be real, but,
if the differential follows the restrained by several mil-
liseconds, it is probable that the differential differences DIF1
AND

arise from one or more of the sensors being saturated.

The protection uses the directional principle to super- DIR
OR

vise the current differential function. The directional TRIP

OR

comparison is used constantly for low-differential currents SAT

AND

(region 1 in Figure 5) and is switched on dynamically

for large differential currents (region 2 in Figure5) upon
detection of CT saturation (Figure 6). Following the exter-
nal fault trajectory (Figure 7) and the logic from Figure 8,
the saturation flag is set when the restraint current, the
largest of the measured currents, crosses the high break-
point (saturation = 1) while in the safe region (the block
region). This happens right after the fault inception dur-
ing the saturation free time. During the saturation of the
CT, the differential current builds up, and, depending on
the severity of saturation, the trajectory may cross slope 2
(differential = 1) into the operating region.
In this region, if the saturation flag is high, the trip
will not be initiated unless the directional flag is high
(direction = 0 or 1). Note that, during an external fault, the
directional flag would be zero, because at least one of the
DIF2
FIGURE 8. An adaptive logic.
currents with significant magnitude is either flowing in
the opposite direction of the bus circuits or is within the
angle between the fault currents. Additionally, the resul-
tant current from the summation of the rest of the currents
is larger than 90, indicating that it is exiting the zone, not
contributing to the mentionedfault. During CT saturation,
the angle of the saturated CT phasor is still a correct rep-
resentation of the primary current angle; hence, it can be
used to make current directional comparisons to differen-
tiate between currents that enter and leave the zone.

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During internal fault (i.e., fault within the differential tion. Different manufacturers may implement various
zone), the currents from the circuits feeding the fault ersions of this logic and other algorithms that improve
v
(i 1 and i 2 ) will be more or less in phase (Figure 9). Feeder relay reliability. It is beyond the scope of this article to
currents i 3, i 4, and i 5 drop. The differential/restraint trajec- cover them all in detail.
tory is shown in Figure 10. In such internal fault cases,
the saturation flag is not set, and no directional check is High-Impedance Bus Differential
needed. The algorithm makes a fast decision for opera- High-impedance differential protection responds to a volt-
age across the differential junction point that is usually a
calibrated resistor (see Figure 11). The CTs are required to
i1 have low secondary leakage impedance (completely dis-
tributed windings or toroidal coils). During external faults,
i2 even with severe saturation of some of the CTs, the volt-
i3 age does not rise above a certain level because the other
i4 CTs will provide a lower-impedance path relative to the
i5 relay input impedance.
Id = i1 + i2 + i3 + i4 + i5 The technique, however, is not free from disadvantag-
Id es, the most important of which are the following:
Ir = max(i1, i2, i3, i4, i5) The high-impedance approach requires dedicated CTs,
Ir
which can add cost when implemented at any volt-
t0 t1
age and is of special concern in LV application where
switchgear or switchboard space is more limited.
FIGURE 9. An internal fault and differential and restraint currents.
The technique cannot be easily applied to re-

configurable buses because the CTs are hardwired in

a specific circuit to the sensing burden. Switching CT
|ID| signals using auxiliary relays decreases reliability and
(DIF2 = 1, SAT = 0) adds an extra cost.
4
No Need to Check It requires overvoltage protection, usually in the form
Differential Current

3 Directional Flag! of a voltage-limiting varistor capable of absorbing sig-

High nificant energy during high-magnitude busbar faults.
2 Operate Slope This approach has been very successful because it har-
Block nesses CT saturation rather than sacrificing sensitivity
1 Low or speed to work around it. When a CT core saturates,
Slope
IR it behaves more like an air core device. The magnetic
Pickup
coupling between the primary and secondary winding
1 2 3 4 5 6
Low Breakpoint

High Breakpoint

is negligible. The impedance now offered by the CT as

seen from the CT secondary terminals is very low, and
it equals the impedance of the CT secondary winding.
The CT is no longer a current source with a high imped-
ance. Rather, it is a simple low-impedance current path.
FIGURE 10. A typical differential/restraint trajectory during internal Hence, if the impedance of the relay element is high,
fault. the sum of the currents from the unsaturated system
CTs will flow through the low-impedance path provided
by the saturated CT instead of through the high-relay
impedance. Therefore, differential current through the
relay would be negligible, causing the protection system
Main Fdr 1 Fdr 2 ... Fdr N to not operate. The saturated CT prevents the operation
CB CB CB CB
of the relay.
87
CT saturation is primarily a consequence of dc offset
V
current. The time for CT core saturation also depends
a R on the inductanceresistance time constant of the line.
r
IAM IAF1 IAF2 IAFN If the protection system can reach a trip decision before
High Z
the onset of CT core saturation, then it would be reliable.
Differential Hence, numerical-relay-based busbar protection is expect-
ed to operate in a quarter of a cycle. The development of
FIGURE 11. A high-impedance bus protection with varistor to such a protection scheme requires ingenuity because of
prevent overvoltage due to excessive fault currents. Var: varistor. the familiar speed-versus-accuracy conflict.

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LV Distribution System Specifics
LV distribution systems present particular complexities for
implementing differential schemes.
LV circuit breakers (CBs) include integral tripping sys-
tems (trip units) that use sensors embedded in the CBs
for all protection functions [2]. The measured current
signal is not generally available to external relays or
protection logic.
Adding traditional CTs within LV equipment is costly
and may require extra equipment sections.
LV systems need to consider a wide range of fault
currents and fault characteristics. LV secondary sub-
station transformers can have impedances that range
in excess of 7.5% or may be below 4% and have
extended ratings that reach up to 40% or more above
base kilovoltamperes. In addition, fault currents can
be arcing and intermittent. Hence, a secondary fault
current could be a low multiple of the largest sensors
associated with a main device. Ignoring the impact
of arcing fault intermittency, an in-zone fault could
be smaller than four times the source-circuit size and
still be a very dangerous and damaging fault that
requires detection and isolation as fast as possible
and as selectively as possible. A slow inverse charac-
teristic is not optimal protection.
Single-phase or phase-to-ground faults can be lower
magnitude. The possibility of LV arcing ground faults
that measure in the hundreds of amperes is the rea-
son for the ground-fault protection requirements in
the National Electrical Code (NEC) [9]. However, the
ground-fault protection requirements in the NEC are not
aggressive in terms of speed. Protection that fulfills NEC
requirements can allow ground faults of several cycles to
grow into serious phase faults before they are cleared.
High-magnitude bolted bus faults are also possible if
there are parallel sources or if very-low-impedance
distribution transformers are used without extended
ratings. Bolted fault currents could exceed 25 times
the sensors in the system when feeder circuit sizes are
considered. Typical maximum arcing fault currents in
a double-ended substation may reach eight to 12 times
the largest sensors in the system.
Intermittent arcing faults in LV systems may present
particular problems for the instantaneous element in
protective relays designed for MV systems. The instan-
taneous algorithm in some relays may reset when the
sensed current drops below the threshold for a half
cycle. Instantaneous algorithms that are delayed for
coordination decrease the reliability of the protection.
The need for selectivity can cause protection systems
to be less sensitive and slower than would be desired to
achieve optimum arcing fault protection. Considering the
significant hazard arcing faults present to equipment and
personnel, insensitive and slow protection is very undesir-
able. The need for fast protection from lower-level arcing
faults while achieving fully selective protection makes
ifferential protection an attractive option, even if the
d
cost is incremental over and above what is available in the
integral trips and regardless of the possible complexity of
the implementation.
LV ZSI
One common scheme used to improve chronometric
protection (nested timecurrent curves) schemes is the
implementation of ZSI. Such schemes usually make use
of a simple hardwired signal that can travel from lower-
tier devices to upper-tier devices, which can enable the
upper-tier device to change from one faster time delay to
a slower delay to allow the lower-tier device to operate.
The scheme may be implemented with serial communi-
cation if the communication is fast enough. This scheme
is well known and has been in use for a number of
decades. Recent enhancements have improved the per-
formance to block from and to the instantaneous range
of both the lower- and upper-tier trip units, allow the
use of overlapping current thresholds, and allow consid-
erations for current direction.
PD Protection Plus Blocking for Multiple-Source Systems
One possible scheme that can combine the benefit of the
differential relay with the blocking capability of LV trip
units may be advantageous in multiple-source systems
with one or more tie CBs. This scheme does not require
dedicated differential CTs in the feeder circuits. In the
PD scheme with LV blocking, the PD relay protection is
used to detect which bus is faulted. Using Figure 12 as
a reference, if the fault is on the parallel-source bus to
the far left or the far right, the PD relay will sense it as a
through fault and not react. If the fault is in the protected
bus or in one of the feeder circuits, the PD scheme will
sense it as an in-zone fault. However, if one of the feeder
trip units senses a fault current in excess of its ZSI-enabled
threshold, then it will issue a blocking signal that can be
interpreted by the logic associated with the differential
Current for 87PD
Source
Parallel
Source
Bus 87B
Trip Signal to
Controlled
CBs
.. To Other PD Zone
Trip Unit
Trip Unit
Trip Unit
ZSI
Blocking
PD Zone Includes Signal
Feeder Circuit But Not
Buses Separated by Ties
FIGURE 12. A PD with an LV CB trip unit feeder blocking input.
september/october 2017 IEEE Industry Applications Magazine 9
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function in the relay. This allows the differential func-
tion to differentiate a fault in the protected zone from a
through fault (externalfault).
The PD protection function guarding the LV bus does
not need dedicated CTs at each feeder circuit. The block-
ing signal from the trip units in the feeder CBs acts like a
directional logic flag in a low-impedance-percentage dif-
ferential relay, which allows a trip if a differential current
is calculated and no feeder issues a blocking signal. How-
ever, the relay will not issue a trip if a feeder provides
a blocking signal, indicating that the fault is external to
the protected bus. Depending on the relay used, it may
be possible to implement the protection with CTs at each
tie device shared between PD zones. This scheme could
be implemented in ring-bus configurations. Since only
the source and ties circuits are monitored, smaller feeder
circuit CTs are not needed. The scheme requires that the
trip units implement a fast ZSI-blocking signal to ensure
the signal reaches the differential function without need
to delay the function artificially.
One risk is if the system is able to step load multiple
feeder circuits simultaneously, causing a transient cur-
rent high enough to cross the differential threshold at
the source circuits but not high enough to cross the
threshold of any one feeder. In this case, none of the
feeders would send a blocking signal to the upstream
devices. The differential threshold would need to be
set above this level of current, or system controls would
need to ensure that too many loads are not step loaded
simultaneously. Modern control systems should mini-
mize this concern. Even if this type of scheme is imple-
mented using separately mounted relays, it is strongly
recommended that the integral trip units be kept in the
CBs set to provide adequate backup protection.
Timing Model for Blocking the Instantaneous
Element 50 of a Microprocessor Overcurrent Relay
For many LV systems, a sufficiently robust PD scheme
could be implemented with an instantaneous multi-
element relay algorithm that can handle the few CT sets
required for a zone. Most systems can be accommodated
with two sets for a double-ended substation. Fault cur-
rents through sources are limited to one source, and cur-
rents through ties are limited to the maximum number
of sources minus one. A fault ahead of a main incomer
would also see the total available fault current minus one.
Based on the small number of CTs and proba-
ble reasonable fault-current-to-CT ratio, a differen-
tial scheme without restraint may be sufficient. If
the instantaneous characteristic can be modeled
(Figure 13) to understand the time window to receive
and process a blocking signal, then the LV blocking
signal and relay response can be coordinated.
The following are the steps to create the model.
1) The IOC 50 algorithm fastest possible timing is identi-
fied. This will vary by brand and type of relay, but, in
10 IEEE Industry Applications Magazine september/october 2017
many modern relays, this is typically a function that is
inversely proportional to the ratio of the fault current
(differential in this case) to the set IOC protection
threshold (a multiple of differential protection thresh-
old). Higher fault current magnitude leads to faster IOC
function operation. (See the bottom diagonal line in
Figure 13.)
2) Identify the additional time that the relay uses to sweep
input/output and process additional logic prior to
asserting a trip. That can be defined as a blocking
window. (See the middle diagonal line in Figure 13.)
3) Identify the additional time required for tolerance con-
siderations and to operate the output contacts. This time
delta will be several milliseconds longer for mechanical
output contacts versus solid-state contacts. If there are
communication delays added by serial communications
or additional mechanical delays added by lockout relays,
that should be added as well. (See the top diagonal line
in Figure 13.)
4) Finally, the CB operation and clearing time is added. For
LV CBs, it is important to consider the operating time of
a shunt trip, which may add several milliseconds. For
modern MV vacuum CBs, three cycles are usually
enough. Five cycles may be needed for older devices.
The top, slightly curved line in Figure 13 represents the
CB clearing time.
Figure 13 shows a timing diagram for a differential
algorithm implemented with the instantaneous protection
of an overcurrent relay superimposed on the LV blocking-
signal timing and the 2,000-A short time and instanta-
neous curve that generates the signal.
A threshold set to 10,000 A as shown in Figure 13 (2.5
times the 4,000-A CT rating) can be blocked from a 2,000-
A feeder. A detailed explanation of this blocking and relay
model can be found in [3]. This threshold could be a sim-
ple IOC or a PD sum operated upon by the IOC algorithm.
As can be seen from this model, the ability to show the
blocking signal from the LV CB and the timing require-
ment for the MV relay allows the ZSI-enabled PD zone to
be set on top of the curve of the LV CB that is blocking
the relay. This could be the largest feeder in the zone.
The question remains of whether this type of PD pro-
tection may be implemented with a simple instantaneous
element without the need for a more sophisticated low-
impedance differential relay with percentage differential
restraint and additional logic. The distortion of the CTs can
be modeled to ascertain if their performance is sufficient.
Figure 14 shows the output of a CT response model that
indicates that differential current caused by CT distortion
with 4,000-A CTs for faults up to 55,000 A is approximate-
ly two times the rated CT output. Models to assess CT per-
formance are readily available from relay manufacturers.
For a more complex application or where fault currents
are larger multipliers of CT ratings, full differential relays
may be implemented. Full differential relays may be very
fast and require limited added delay to provide time for
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

a blocking signal to be processed. Typically, fewer than

10ms should be necessary. Bus differential relays require
a larger capital investment and are more difficult to adjust.
However, they may provide the requisite reliability in sys-
tems with low-impedance transformers, long CT leads, or 1.000
more than two incoming sources.
Figure 15 shows a relay and LV trip unit scheme for
LV CB ST and
a complete substation incoming and main-bus protec- IOC Curve
tion using a multiple-element overcurrent relay. Relays MV CB Clearing
that have the ability to accept up to six sets of CT inputs
0.100

Seconds
and can allocate the CT signals in various ways by using
logical inputs to arbitrate which protection element uses
which CT input and when it is enabled are available. Relay Output
LV CB ZSI Output Signal
Therefore, a scheme as shown in this figure could be Signal Time Model
implemented with one relay. Using two relays would
require two sets of CTs around the tie CB. 0.010
Figure 16 shows a system implemented with a mul-
Relay IOC Blocking
tiple-element relay that is able to provide transformer Window
protection (87T) and several 50 and 51 elements simul- 0.010
Relay IOC Minimum
taneously. The ability to accept various CT inputs and Commit Time
use logical inputs to arbitrate which protection is used 0.001
as the system topology changes allows two relays to 1,000 10,000 100,000
provide transformer differential, bus PD protection, Amperes
timeovercurrent backup protection to the transform- LV CB Pickups; ST = 6,000 A, IOC = 16,000 A
er, and selective instantaneous protection to the LV MV Relay IOC/Differential Pickup = 10,000 A
incoming section simultaneously. CB Operating Time, Three Cycles
No Additional Intentional Delays

Networked Trip Units and Advanced Protection

Modern protocols and communication technology
FIGURE 13. An LV blocking signal timing plotted along with a
protective-relay blocking window to visualize parameters that
allow devices to communicate current information as areneeded to set blocking-scheme thresholds and timing.
phasors or discrete samples of data in a synchronized ST: short time.
manner. Protective relay systems
are able to implement d ifferential
schemes using these communication 160
150 CT Secondary Current
techniques. LV systems that are able 140 CT Secondary Current
130
to implement similar synchronized 120 Differential Current
110
data schemes have been available for 100
90
over a decade. 80
As improved communications 70
60
technology becomes more widely 50
Secondary Amperes

40
available, manufacturers will make 30
20
LV trip systems that are able to pro- 10 Seconds
vide much of the complex protec- 0
0.02 100 0.02 0.04 0.06 0.08 0.10
tion capability now only available 20
30
in MV and high-voltage-type pro- 40
50
tective relays. The ability for trip 60
70
units to communicate information 80
is not necessarily enough to provide 90
100
system-level protection and some 110
120 CT1 (Source) = 4,000:5 (C100) Vsat = 100 V
fast control solutions. The more dif- 130
140 CT Burden = 0.7
ficult requirement is for the infor- CT2 (Tie Breaker) = 4,000:5 (C100) Vsat = 100 V
mation from various sources to be CT Burden = 0.5
adequately synchronized and pro- External Fault = 55 kA. DC Offset = 1. X /R = 5
cessed with sufficient frequency so
that networked devices can replace FIGURE 14. The fault currents from incomer and tie-breaker CTs during external fault on the
quivalents neighboring LV bus.
analog devices or digital e

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to address CT saturation and wide

Implemented with 50 dynamic fault-current ranges.
Element in Simple Low-
Fault Current Systems System designers will need to
51 or Fully Capable 87B 51 continually examine the solutions
Relay in Complex High-
Fault Current Systems available in the market to make sure
52 52 they are availing themselves of the
50PD 50PD
best cost-effective technology. It is
too easy to allow designs to be influ-
enced by technical limitations that
50 Multi-Element 50 existed yesterday but are no longer
Overcurrent Relay
true today due to the constant inno-
vation in the market.

LV Left LV Right
Main Main
LV Tie
LV Fdr LV Fdr
Blocking Signals from LV Trips
FIGURE 15. A PD scheme implemented with overcurrent relays combined with other
overcurrent functions.
Substation and Transformer
51
Protection
MV 51 for Transformer Overcurrent
52 87T Protection (Primary if No
87T, Backup Otherwise)
87T Provides Transformer
50PD Protection and Protection for
Part of Transformer
Secondary LV Bus within
the Zone
50
50PD Provides
Transformer Secondary LV
Bus and Main LV Bus
Protection When the
Incomer and Tie are Closed
LV Main LV 50 Provides Fast
Protection of Transformer
LV Tie Secondary Bus And Main
Bus if Tie is Open
Will Require One Relay for
LV Fdr Each Transformer for 87T
FIGURE 16. A PD implemented with overcurrent relays, other overcurrent functions, and
transformer differential.
that require direct sensor input from multiple circuit understand
points. Furthermore, the increasing use of air-core signals required to implement the system. A work-
sensors that are integral to the CBs provides a way able model of the varying signals and time-versus-fault
Conclusions
Differential and blocking-based
protection are excellent ways to
achieve an improved protection of
main buses for both LV and MV sys-
tems. Thinking that bus differen-
tial protection is only for the most
sophisticated high-voltage bus or
is too complicated to consider by
other than the expert utility-systems
designer is no longer true.
Modern digital relays, particu-
larly low-impedance-percentage dif-
ferential relays, offer an economic
and relatively simple differential
protection option that can be used
in LV buses to supplement typical
protection provided by integral trip
units. This option can even be com-
bined with the blocking capability
of many downstream trip units to
achieve fast sensitive supplemen-
tal protection without the need
for costly and large additional CTs
at each feeder circuit. In simpler
systems with lower fault currents,
multiple-element relays may be
used to implement a simple instan-
taneous PD function that can be
blocked from the LV feeder trips.
Other multifunction relays are able
to offer transformer differential as
well as multiple overcurrent 51 and
instantaneous 50 elements that can
also be used in simple systems to
simultaneously provide transformer
and bus PD protection as well as
selective instantaneous protection
when the bus has a single source.
T he protection engineer must
the timing of the various algorithms and

12 IEEE Industry Applications Magazine september/october 2017

 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
current is required. Implementing networked trip units
or equivalent protocols may also provide a cost-effective
and size-effective way to execute differential protection
for improved protection speed and protection sensitivity
without negatively impacting system selectivity.
It is not the intent of this article to suggest that MV
relays supplant integral trip units that are normally pro-
vided with LV CBs. Integral trip units provide several
advantages, such as being able to operate self-powered
and listed with the CBs so it is known that they cannot be
set beyond the ability of the CB to interrupt or withstand
the fault current. Relays should be used to provide supple-
mental protection that improves the overall protection
provided for the system.
Author Information
Lubomir Sevov is with GE Digital EnergyMultilin,
Markham, Ontario, Canada. Marcelo Valdes (Marcelo.
Valdes@GE.com) is with GE Industrial Solutions, Cary,
North Carolina. Sevov and Valdes are Senior Members
of the IEEE. This article first appeared as Consider-
ation for Differential Protection in LV Buses at the
2015 IEEE Petroleum and Chemical Industry Committee
Conference. This article was reviewed by the IAS Petro-
leum and Chemical Industry Committee.
References
[1] B. Kasztenny, L. Sevov, and G. Brunello, Digital low-impedance bus
differential protectionReview of principles and approaches, in Proc.
51st Annu. Conf. Protective Relay Engineers, College Station, TX, 2001.
[2] Recommended Practice for the Application of Low-Voltage Circuit
Breakers in Industrial and Commercial Power Systems, IEEE 3004.5-2014.
[3] M. E. Valdes and J. J. Dougherty, Advances in protective device inter-
locking for improved protection and selectivity, IEEE Trans. Ind. Appl.,
vol. 50, no. 3, pp. 16391648, 2014.
[4] A. Apostolov, IEC 61850 based bus protectionPrinciples and bene-
fits, in Proc. 2009 IEEE Power & Energy Society General Meeting, pp. 16.
[5] T&D World. (2000, May). Protocol choices for the substation: Trans-
mission and distribution. [Online]. Available: http://tdworld.com/archive/
protocol-choices-substation
[6] National Electrical Code 2014, NFPA 70.
[7] S. Pavavicharn and G. Johnson, A review of high-impedance and low-
impedance differential relaying for bus protection, in Proc. IEEE 67th
Annu. Conf. Protective Relay Engineers, pp. 723737, 2014.
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ance bus differential protection, in Proc. 2009 Power Systems Conf.,
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