Tanner Tools Examples Guide PDF

Tanner Tools v15
Examples Guide
Tanner EDA Division

Tanner Research, Inc.
825 South Myrtle Avenue
Monrovia, CA 91016-3424
Tel: (626) 471-9700
Copyright 2009
Tanner Tools v15 Examples Guide
TABLE OF CONTENTS
Section 1 Designs ..................................................................................... 5
Section 1.1 ADC8 ............................................................................... 5
Section 1.2 ADC Behavioral ............................................................ 5
Section 1.3 Bargraph.......................................................................... 5
Section 1.4 BusesAndArrays .............................................................. 5
Section 1.4.1 Simple Buses ..................................................................... 5
Section 1.4.2 Splitting Buses .................................................................... 5
Section 1.4.3 Port Bundles ....................................................................... 6
Section 1.4.4 1-Dimensional Arrays ......................................................... 6
Section 1.4.5 2-Dimensional Arrays ......................................................... 6
Section 1.5 CCD Imager .................................................................... 6
Section 1.6 Comparator One Bit...................................................... 6
Section 1.7 CPU ................................................................................. 6
Section 1.8 DecayMeasurement-Verilog ............................................ 7
Section 1.9 DLatch ............................................................................. 7
Section 1.10 GaAsAmp ........................................................................ 7
Section 1.11 GlobalNets....................................................................... 7
Section 1.11.1 Simple Global Nets ............................................................. 7
Section 1.11.2 Separate Power Supplies ................................................... 8
Section 1.11.3 Renaming Separate Power Supplies ................................. 9
Section 1.11.4 Renaming Separate Power Supplies Alternate Method 10
Section 1.12 ICResistors .................................................................... 11
Section 1.13 Inverter .......................................................................... 11
Section 1.13.1 DC Operating Point Analysis ............................................ 11
Section 1.13.2 DC Transfer Analysis and Parameter Sweep ................... 16
Section 1.13.3 Transient Analysis ............................................................ 19
Section 1.14 Lights (Traffic Light Controller) ...................................... 22
Section 1.15 LinearFeedbackShiftRegister ........................................ 22
Section 1.16 MonitorVoltageRange-Verilog ....................................... 22
Section 1.17 MOS_Subthreshold ....................................................... 22
Section 1.18 MultipleSymbolViews..................................................... 22
Section 1.18.1 MOSFET with 4- and 3-terminal symbols ......................... 22
Section 1.18.2 NMOS with IEEE and IEC symbols .................................. 23
Section 1.18.3 Adder with 3 different symbols ......................................... 24
Section 1.19 OpAmp .......................................................................... 24
Section 1.19.1 AC Analysis ...................................................................... 24
Section 1.20 Parameterized_NAND ................................................... 28
Section 1.20.1 Using Subcircuits .............................................................. 28
Section 1.21 PLL-Behavioral .............................................................. 32
Section 1.22 Pseudo-random Bit Sequence-Verilog .......................... 32
Section 1.23 ReadTextFile-Verilog ..................................................... 33
Section 1.24 Resonator ...................................................................... 33
Section 1.25 RingOscillator ................................................................ 33
Section 1.26 RingOscillator-Behavioral .............................................. 33
Section 1.27 RingVCO ....................................................................... 33
1
Section 1.28 SpiceOutput................................................................... 33

Section 1.28.1 SPICE Primitives .............................................................. 33
Section 1.28.2 Passing parameters down hierarchy ................................ 35
Section 1.28.3 Subcircuits ........................................................................ 36
Section 1.28.4 SPICE Export Control property ........................................ 39
Section 1.29 Stimuli............................................................................ 40
Section 1.30 XOR............................................................................... 40
Section 2 Process ................................................................................... 40

Section 2.1 Gallium Arsenide (GaAs) ............................................... 40
Section 2.2 Generic 0.25um ............................................................. 40
Section 2.2.1 Analog Symbols Library ................................................... 40
Section 2.2.2 Device Symbols Library .................................................... 40
Section 2.2.3 I/O Pad Symbols Library .................................................. 40
Section 2.2.4 Logic Gate Symbols Library ............................................. 41
Section 2.2.5 Technology Files .............................................................. 41
Section 2.3 MOSIS Scalable AMIS 0.8um ....................................... 41
Section 2.4 MOSIS Scalable AMIS 1.2um ....................................... 41
Section 2.5 MOSIS Scalable HP 0.5um ........................................... 42
Section 2.6 MOSIS Scalable Orbit 1.2um ........................................ 42
Section 2.7 MOSIS Scalable Orbit 2.0um ........................................ 42
Section 2.8 Native Orbit 1.2um ........................................................ 42
Section 2.9 Native Orbit 2.0um ........................................................ 43
Section 2.10 Generic Standard Libraries............................................ 43
Section 2.10.1 Device Symbols Library .................................................... 43
Section 2.10.2 Miscellaneous Symbols Library ........................................ 43
Section 2.10.3 SPICE Command Symbols Library .................................. 43
Section 2.10.4 SPICE Element Symbols Library ...................................... 43
Section 3 Automated Operations .......................................................... 44

Section 3.1 S-Edit TCL Scripts ......................................................... 44
Section 3.1.1 Calculator - TK ................................................................. 44
Section 3.1.2 Change Symbol Property Size ......................................... 44
Section 3.1.3 Change WhenNotEval Property ....................................... 44
Section 3.1.4 Copy Cells ........................................................................ 44
Section 3.1.5 Copy Cells Traverse Hierarchy...................................... 44
Section 3.1.6 Delete Empty Schematic View ......................................... 44
Section 3.1.7 Delete Property ................................................................ 44
Section 3.1.8 Find Property on Instance - TK ........................................ 44
Section 3.1.9 Find and Rename Instance .............................................. 44
Section 3.1.10 Change Port and Netlabels .............................................. 44
Section 3.1.11 Force Callback ................................................................. 45
Section 3.1.12 Hello World - TK ............................................................... 45
Section 3.1.13 Resizing Text - TK ............................................................ 45
Section 3.2 L-Edit UPI Macros ......................................................... 46
Section 3.2.1 Add to Find ....................................................................... 46
Section 3.2.2 Boolean Operations .......................................................... 46
Section 3.2.3 Capacitor .......................................................................... 47
Section 3.2.4 Change Instance Name to Include Rotation Parameter ... 47
2
Section 3.2.5 Change Layer ................................................................... 47

Section 3.2.6 Change Layer and Duplicate ............................................ 47
Section 3.2.7 Change Layer and Grow .................................................. 47
Section 3.2.8 Create Contact ................................................................. 47
Section 3.2.9 Copy Layer Rendering ..................................................... 48
Section 3.2.10 Create Derived Layer ....................................................... 48
Section 3.2.11 Delete Layer ..................................................................... 48
Section 3.2.12 Dialog Examples .............................................................. 48
Section 3.2.13 Gear 48
Section 3.2.14 Generate Derived Layer in Subcell .................................. 49
Section 3.2.15 Goto 49
Section 3.2.16 Grow Via ........................................................................... 49
Section 3.2.17 Hello World ....................................................................... 49
Section 3.2.18 Hide Layer with GDS DataType = 1 ................................. 49
Section 3.2.19 Hierarchical Instance Location ......................................... 49
Section 3.2.20 Import GDS Copy Cell ...................................................... 50
Section 3.2.21 Instance and Rotate a T-Cell ............................................ 50
Section 3.2.22 Instance a Cell .................................................................. 50
Section 3.2.23 Interface ........................................................................... 50
Section 3.2.24 Drawing Mode Keyboard Shortcuts .................................. 50
Section 3.2.25 MFC 51
Section 3.2.26 MOSFET .......................................................................... 51
Section 3.2.27 Move 51
Section 3.2.28 Palette .............................................................................. 51
Section 3.2.29 Perimeter ..........................................................................51
Section 3.2.30 Place Ports ....................................................................... 51
Section 3.2.31 Polar Array ....................................................................... 52
Section 3.2.32 Port List ............................................................................ 52
Section 3.2.33 Properties ......................................................................... 52
Section 3.2.34 Read from Text File and Instance T-Cell .......................... 52
Section 3.2.35 Rename Cell ..................................................................... 52
Section 3.2.36 Resistor ............................................................................ 52
Section 3.2.37 Run L-Edit in Command Mode and Load a Macro ........... 53
Section 3.2.38 Selected Polygon Vertex Summary Report ...................... 53
Section 3.2.39 Set Layer Rendering ........................................................ 53
Section 3.2.40 Spiral 53
Section 3.2.41 Spring ............................................................................... 53
Section 3.3 L-Edit T-Cells ................................................................. 54
Section 3.3.1 Buffer 54
Section 3.3.2 Change T-Cell Name ........................................................ 54
Section 3.3.3 Concentric Tori ................................................................. 54
Section 3.3.4 Decoder ............................................................................ 54
Section 3.3.5 Ellipse ...............................................................................54
Section 3.3.6 Layout Text Generator ..................................................... 54
Section 3.3.7 Matched Dual Capacitor Array ......................................... 55
Section 3.3.8 MOSFET .......................................................................... 55
Section 3.3.9 Rounded Rectangle .......................................................... 55
Section 3.3.10 Segmented Tori ................................................................ 55
Section 3.3.11 Spiral 55
Section 3.3.12 T-Cell Builder .................................................................... 55
Section 3.3.13 T-Cell Calls Another T-Cell ............................................... 55
3
Section 3.3.14 Test Pattern Generator ..................................................... 56

Section 3.4 L-Edit Bindkeys ............................................................. 56
Section 3.4.1 Cadence ........................................................................... 56
Section 4 Additional Examples .............................................................. 56

Section 4.1 T-Spice External C Models ............................................ 56
Section 4.1.1 Diode 56
Section 4.1.2 MOS1 ............................................................................... 56
Section 4.1.3 Resistor ............................................................................ 57
Section 4.1.4 Switch ............................................................................... 57
Section 4.1.5 VCO 57
Section 4.2 L-Edit Layer Setup ......................................................... 57
Section 4.2.1 Black Background ............................................................ 57
Section 4.2.2 Multiple Vias ..................................................................... 57
Section 4.2.3 Pastel Colors .................................................................... 58
Section 4.2.4 Stripes .............................................................................. 58
4
Section 1 Designs
Section 1.1 ADC8
Section 1.2 ADC Behavioral
Section 1.3 Bargraph
Section 1.4 BusesAndArrays
DesignType: Digital
Features: S-Edit
Section 1.4.1 Simple Buses
S-Edit Design: \Designs\BusesAndArrays\BusesAndArrays.tanner

Cell: Top_SimpleBus
This example illustrates the basic syntax and usage of buses and arrays. An 8-bit wide bus,
In<1:8>, is split into two buses, one containing the even numbered bits and the other
containing the odd numbered bits. The third value in the bus specification, indicating a step
value of 2, is used to perform this split. The even numbered bits connect to a 4x array of
inverters, and the odd numbered bits connect to a 4x array of buffers. The inverter and the
buffer each have a single input and output connection, so the 4x arrays of each of these
provides a 4-bit wide input and output connection to match the dimension of the buses that
connect to them. When connecting buses to instances or arrays of instances, it is important
to make sure that the dimensions match. Invoking Tools > Design Checks will issue
warnings for mismatched bus and instance dimensions. The output of the inverters and the
output of the buffers are then combined to form an 8-bit wide output bus, Out<1:8>.
Section 1.4.2 Splitting Buses

Cell: Top_SplitBus
This example illustrates the labeling requirements when splitting buses. An 8-bit wide bus,
In<0:7>, is input to an 8x array of inverters, and an 8-bit wide bus, D<0:7>, is output. The 8-
bit bus D<0:7> is then split into a 5-bit wide bus, D<3:7>, and a 3-bit wide bus, D<0:2>. Note
that whenever there is a T-junction of buses, all branches of the T must be explicitly
labeled in order to unambiguously identify the dimension and components of each branch.
Individual bits D<2>, D<1>, and D<0> are then ripped from the bus and connected to a
buffer, inverter, and another buffer, and output as nets Q, R, and S, respectively.
5
Section 1.4.3 Port Bundles

Cell: Top_PortBundle
This example illustrates the use of port bundles in a symbol. This example is similar to
Top_SplitBus, however here the 8-bit input bus, In<0:7>, is connected to a single instance,
Inv8a, rather than to an array. The symbol of Inv8a contains an 8-bit port bundle, A<0:7>, to
which the input bus is connected, thereby matching dimensions of the bus with the instance
connection. The port bundle can be a single bus, A<0:7>, as is the case in this example, or
it could be a collection of buses and nets, such as A<0:4:2>, B<0:3>, C. The output of the
instance is an 8-bit port bundle, Out<0:7> which connects to an 8-bit wide bus, Qu, Rb, Su,
D<3:7>. The 8-bit bus Qu, Rb, Su, D<3:7> is then split into a 5-bit wide bus, D<3:7>, and a
3-bit wide bus, Qu, Rb, Su. Individual bits Qu, Rb, and Su are then ripped from the bus and
connected to a buffer, inverter, and another buffer, and output as nets Q, R, and S,
respectively.
Section 1.4.4 1-Dimensional Arrays

Cell: Top_1DArrays
This example illustrates how to connect the input and output of an array to form a
connection in series. The input into the 5x array of inverters is In, N<0>, N<1>, N<2>, N<3>,
and the output is N<0>, N<1>, N<2>, N<3>, Out. Notice the offset by one in the position of
N<0:3> in the naming of the input and output buses. This causes the output of one inverter
to be connected to the input of the next inverter. The connection is formed by naming the
output and input labels with the same name. There does not need to be a wire actually
making a connection. In addition, as can be seen for the input, no physical wire connection
is made between the In port and the bus. For the output, a wire connection is made and the
net is labeled Out to match that of the Out port. Either method will produce the same result.
Section 1.4.5 2-Dimensional Arrays

Cell: Top_2DArrays
This example illustrates the usage and syntax of two dimensional arrays. Arrays Left, Top,
Bottom, and Right are 1-D arrays which are connected to around the perimeter of a 2-D
array Cen using a connection by name, similar to that used in Top_1DArrays.
Section 1.5 CCD Imager
Section 1.6 Comparator One Bit
Section 1.7 CPU
6
Section 1.8 DecayMeasurement-Verilog
Section 1.9 DLatch
Section 1.10 GaAsAmp
Section 1.11 GlobalNets
DesignType: Digital
Features: S-Edit
Section 1.11.1 Simple Global Nets
S-Edit Design: \Designs\GlobalNets\GlobalNets.tanner

Cell: Top_GlobalNets
Global nets in S-Edit are connected through the design hierarchy, without explicitly placing
ports for them at every level. In this example there are two cores, CoreHV_Global and
CoreLV_Global instanced in cell Top_GlobalNets. Inside CoreHV_Global, we have
instances of Block2 and Block3, and inside CoreLV_Global we have instances of Block1
and Block2. These can be seen in the .subckt definitions of CoreHV_Global and
CoreLV_Global in the netlist below. Each schematic of Block1, Block2, and Block3 has a
global symbol for Vdd and Gnd.
In this design, Vdd and Gnd are global, and are connected through the entire design
hierarchy.
*************** Subcircuits *****************

.subckt Block1 In Out Gnd Vdd
.ends
.subckt Block2 In1 In2 Out1 Out2 Gnd Vdd

.ends
.subckt Block3 In1 In2 Out Gnd Vdd

.ends
.subckt CoreHV_Global A1 A2 A3 B1 B2 B3 Gnd Vdd

XU1 A1 A2 B1 Gnd Vdd Block3
XU2 A2 A3 B2 B3 Gnd Vdd Block2
.ends
.subckt CoreLV_Global A1 A2 A3 B1 B2 B3 Gnd Vdd

XU1 A1 B1 Gnd Vdd Block1
.ends
7
XCoreHV_Global_1 N_3 N_5 N_2 N_4 N_1 N_6 Gnd Vdd CoreHV_Global
XCoreLV_Global_1 N_10 N_8 N_11 N_9 N_12 N_7 Gnd Vdd CoreLV_Global
.end
Section 1.11.2 Separate Power Supplies

Cell: Top_VddIsolation
This example illustrates how to isolate the global Vdd nets contained inside two cells.
Consider the two core cells in the Top_GlobalNets design. We wish to isolate the global Vdd
in CoreHV_Global from the global Vdd in CoreLV_Global.
The design in Top_VddIsolation has been modified by adding netcaps for Vdd in
CoreHV_VddNetCap and CoreLV_VddNetCap. The name of the netcap must match the
name of the net being capped, including case sensitivity, in order for the net to be properly
capped. Notice now that Vdd no longer appears in the parameter list for the definition of
CoreHV_VddNetCap and CoreLV_VddNetCap in the netlist below, and is correspondingly
absent in the calls to CoreHV_VddNetCap and CoreLV_VddNetCap in the main circuit. The
Vdd inside subcircuit CoreHV_VddNetCap and the Vdd inside subcircuit
CoreLV_VddNetCap are therefore not connected to each other.
*************** Subcircuits *****************

.ends

.ends

.ends
.subckt CoreHV_VddNetCap A1 A2 A3 B1 B2 B3 Gnd

.ends
.subckt CoreLV_VddNetCap A1 A2 A3 B1 B2 B3 Gnd

.ends
XCoreHV_VddNetCap_1 N_2 N_3 N_4 N_1 N_5 N_6 Gnd CoreHV_VddNetCap

XCoreLV_VddNetCap_1 N_12 N_11 N_10 N_7 N_8 N_9 Gnd CoreLV_VddNetCap
.end
8
The Vdd nets in CoreHV_VddNetCap and CoreLV_VddNetCap can be reconnected by

removing the netcaps, or alternatively by placing the following command in the SPICE
netlist:
.global Vdd
The .global command can be automatically put into the netlist in S-Edit, by creating a
symbol with the following property:
SPICE.OUTPUT = .global Vdd
The symbol can then be instanced at the top level of the design. An example of this can be
viewed by opening design example Top_VddReconnectNetCap.
Section 1.11.3 Renaming Separate Power Supplies

Cell: Top_VddIsolationRename
This example illustrates how to isolate the global Vdd nets in two cells from each other, and
to connect to them with unique names. Consider the two core cells in the
Top_VddIsolationRename design. In Top_VddIsolation, we isolated the Vdd in
CoreHV_VddNetCap from the Vdd in CoreLV_VddNetCap. We now wish to connect to
CoreHV_VddNetCap with a net named Vdd_5v and to CoreLV_VddNetCap with a net named
Vdd_3v.
In this example, the design in Top_VddIsolationRename has been modified by adding In

ports Vdd_HV and Vdd_LV to cores CoreHV_VddRename and CoreLV_VddRename
respectively, both on the schematic and symbol views. On the schematic views, the new
ports are connected to the netcaps, thus continuing the propagation of the Vdd net up the
hierarchy, but with a different name. In the calls in the main circuit, you can see nets
Vdd_5v connecting to cores CoreHV_VddRename and Vdd_3v connecting to
CoreLV_VddRename.
*************** Subcircuits *****************

.ends

.ends

.ends
.subckt CoreHV_VddRename A1 A2 A3 B1 B2 B3 Vdd Gnd

.ends
.subckt CoreLV_VddRename A1 A2 A3 B1 B2 B3 Vdd Gnd
9

.ends
XCoreHV_VddRename_1 N_2 N_3 N_4 N_1 N_5 N_6 Vdd_5v Gnd

CoreHV_VddRename
XCoreLV_VddRename_1 N_12 N_11 N_10 N_7 N_8 N_9 Vdd_3v Gnd
CoreLV_VddRename
.end
Section 1.11.4 Renaming Separate Power Supplies Alternate Method

Cell: Top_VddIsolationRenameAlt
This example illustrates another way to isolate the global Vdd nets in two cells from each
other, and to connect to them with unique names. Consider the two core cells in the
Top_VddIsolation design. In Top_VddIsolation, we isolated the Vdd in CoreHV_Global from
the Vdd in CoreLV_Global. We now wish to connect to CoreHV_Global with a net named
Vdd_5v and to CoreLV_Global with a net named Vdd_3v.
In this example, the design in Top_VddIsolation has been modified by adding Global ports
Vdd_5v and Vdd_3v to the schematic views of cores CoreHV_VddRenameGlobal and
CoreLV_VddRenameGlobal respectively. The new ports are connected to the netcaps, thus
continuing the propagation of the Vdd net up the hierarchy, but with a different name. The
name of the Global port takes precedence over the name of the netcap. In the calls in the
main circuit, you can see net Vdd_5v connecting to CoreHV_VddRenameGlobal and
Vdd_3v connecting to CoreLV_VddRenameGlobal.
*************** Subcircuits *****************

.ends

.ends

.ends
.subckt CoreHV_VddRenameGlobal A1 A2 A3 B1 B2 B3 Gnd Vdd

.ends
.subckt CoreLV_VddRenameGlobal A1 A2 A3 B1 B2 B3 Gnd Vdd

.ends
10
XCoreLV_VddRenameGlobal_1 N_12 N_11 N_10 N_7 N_8 N_9 Gnd Vdd_3v

CoreLV_VddRenameGlobal
XCoreHV_VddRenameGlobal_1 N_2 N_3 N_4 N_1 N_5 N_6 Gnd Vdd_5v
CoreHV_VddRenameGlobal
.end
Section 1.12 ICResistors
Section 1.13 Inverter
DesignType: Digital
Features: S-Edit
T-Spice Analysis Examples DC_Op_Point, DC_Sweep,
Monte_Carlo, Parameter_Sweep, Transient
Section 1.13.1 DC Operating Point Analysis
S-Edit Design: \Designs\Inverter\Inverter.tanner

T-Spice Netlist: \Designs\Inverter\SimulationResults\InverterOP.sp
Cell: Inverter_TestBench OperatingPoint Schematic
DC operating point analysis finds a circuits steady-state condition, obtained (in principle)
after the input voltages have been applied for an infinite amount of time.
Each of the components visible in the schematic has properties associated with it.
Properties are textual elements, created in S-Edit, that are attached to an object and
provide key information about its design and simulation commands in T-Spice. If you "push
in" to open a specific instance, you can see that the physical dimensions of the component
M1n in the inverter are defined by the properties:
M=1
W = 1.5u
L = 0.25u
M1n is an instance of the symbol NMOS_2_5v, which represents an n-channel MOSFET

transistor. Properties that describe the operation of a generic n-channel MOSFET are
defined at the symbol level. Properties specific to component M1n, such as length and
width, are defined when M1n is created. Property values defined at the component level
take precedence over default (symbol) values.
1.13.1.1. SPICE Simulation Setup in S-Edit
Prior to running the T-Spice simulation, the analysis commands and all processing options
need to be established. This is accomplished using the Setup SPICE Simulation dialog in S-
Edit.
11
Ensure that you are viewing the top level schematic. For this example, the top level cell is
named Inverter_TestBench. Right-click on Inverter_TestBench in the Libraries window and
use Open View to select the schematic OperatingPoint.
Use Setup > SPICE Simulation to launch the Setup SPICE Simulation dialog. The proper
simulation settings for the Inverter_TestBench example have already been entered for you.
Note that the DC Operating Point Analysis box is checked. Also note the settings in the
General options for File Search Path and Library Files. Export the Netlist to T-Spice.
1.13.1.2. Export Netlist to T-Spice
In the Inverter_Testbench - Operating Point schematic, use Tools > Design Checks >
View and Hierarchy to execute the Design Checker. The Design Checker will display any
violation or errors in the Command window. There should not be any errors in
Inverter_Testbench - Operating Point.
Press the T-Spice icon ( ) to export a T-Spice netlist file named InverterOP.sp. S-Edit will
launch T-Spice with the InverterOP.sp netlist open:
1.13.1.3. T-Spice Input
********* Simulation Settings - General section *********

.option search="\Process\Generic250nm\Generic250nmTech"
12
.lib "Generic_025.lib" TT
*-------- Devices: SPICE.ORDER < 0 --------

* Design: Inverter / Cell: Inverter_TestBench / View: OperatingPoint
/ Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Operating point analysis testbench of an inverter
* Date: 10/15/2008 9:49:36 AM
* Revision: 46
*************** Subcircuits *****************

.subckt INV A Out Gnd Vdd
* Design: Generic250nmLogicGates / Cell: INV / View: Main / Page:
* Info: Inverter
* Date: 5/30/2008 4:06:39 PM
* Revision: 13
*-------- Devices: SPICE.ORDER == 0 --------

MM1n Out A Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f
PD=4.3u
MM2p Out A Vdd Vdd PMOS25 W=3u L=250n M=2 AS=3.9p PS=14.6u AD=2.25p
PD=7.5u
.ends
********* Simulation Settings - Parameters and SPICE Options

*********
.param Vpwr = 3.3v

XX1 N_2 N_1 Gnd Vdd INV
*-------- Devices: SPICE.ORDER > 0 --------
CC1 N_1 Gnd 1p
VVin N_2 Gnd DC 1
VVpower Vdd Gnd DC Vpwr
********* Simulation Settings - Analysis section *********

.op
********* Simulation Settings - Additional SPICE commands *********
.end
Two transistors, MM2p and MM1n, are defined in InverterOP.sp. These are MOSFETs, as
indicated by the key letter M that begins their names. Following each transistor name are
the names of its terminals in the required order: draingatesourcebulk. Then the model
name (PMOS25 or NMOS25 in this example) and physical characteristics, such as length
13
and width, are specified. A capacitor CC1 (signified by the key letter C) connects nodes
N_1 and GND with a capacitance of 1p. Strictly speaking, the capacitor could be omitted
from the circuit for this example, since it does not affect the DC operation of the inverter.
Two DC voltage sources are defined: VVin, which sets node N_2 to 1.0 volt relative to
ground and VVpower, which sets node Vdd to 3.3 volts as defined by the variable Vpwr.
Notice that the simulation settings which were entered in the SPICE Simulation Setup dialog
resulted in .option, .lib, and .op commands being written to the T-Spice input file. The
.lib command causes T-Spice to read the contents of the Generic_025.lib library file for
the evaluation of transistors MM2p and MM1n, and the search option identifies the path to
the library files. In this case, the library file contains two device .model commands,
describing MOSFET models PMOS25 and NMOS25, as shown below for PMOS25:
.MODEL PMOS25 PMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 5.6E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = '-
0.4935548+dVthP'
+K1 = 0.6143278 K2 = 6.804492E-4 K3 = 0
+K3B = 5.8844074 W0 = 1E-6 NLX =
6.938169E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 2.3578746 DVT1 = 0.7014778 DVT2 = -
0.1881376
+U0 = 100 UA = 9.119231E-10 UB = 1E-21
+UC = -1E-10 VSAT = 1.782051E5 A0 =
0.9704347
+AGS = 0.1073973 B0 = 2.773991E-7 B1 =
8.423987E-7
+KETA = 0.0104811 A1 = 0.0193128 A2 = 0.3
+RDSW = 694.5830247 PRWG = 0.3169639 PRWB = -
0.1958978
+WR = 1 WINT = 0 LINT =
2.971337E-8
+XL = 'dxl' XW = '-4E-8+dxw' DWG = -
2.967296E-8
+DWB = -2.31786E-10 VOFF = -0.1152095 NFACTOR =
1.1064678
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.3676411 ETAB = -
0.0915241
+DSUB = 1.1089801 PCLM = 1.3226289 PDIBLC1 =
9.913816E-3
+PDIBLC2 = -1.499968E-6 PDIBLCB = -1E-3 DROUT =
0.1276027
+PSCBE1 = 8E10 PSCBE2 = 5.772776E-10 PVAG =
0.0135936
+DELTA = 0.01 RSH = 3 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
14
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 5.59E-10 CGSO = 5.59E-10 CGBO = 5E-10
+CJ = 1.857995E-3 PB = 0.9771691 MJ =
0.4686434
+CJSW = 3.426642E-10 PBSW = 0.871788 MJSW =
0.3314778
+CJSWG = 2.5E-10 PBSWG = 0.871788 MJSWG =
0.3314778
+CF = 0 PVTH0 = 4.137981E-3 PRDSW =
7.2931065
+PK2 = 2.600307E-3 WKETA = 0.0192532 LKETA = -
5.972879E-3 )
Generic_025.lib assigns values to various Level 49 MOSFET model parameters for both n-
and p-channel devices. T-Spice uses these parameters to evaluate Level 49 MOSFET
model equations. The .op command performs a DC operating point calculation and writes
the results to the file specified in the Simulation > Run Simulation dialog.
1.13.1.4. Run the Simulation in T-Spice
With InverterOP.sp open in T-Spice, use File > Save to save the file. Click the Run
Simulation button ( ) in the T-Spice simulation toolbar. T-Spice will open a new window
displaying the simulation log.
1.13.1.5. Output
The output file lists the DC operating point information for the circuit. You can read this file in
T-Spice or any text editor.
1.13.1.6. Open the Output File
If not already displayed, select View > Simulation Manager from the T-Spice menu to open
the Simulation Manager:
Right-click the InverterOP.out display line in the window, then click Show Output to open
the output file InverterOP.out in a new T-Spice window. If you prefer to view the output in a
text editor, simply open InverterOP.out as a text file. It is located in the same directory as
the input file.
The output file contains the following DC operating point information (in addition to
comments of various kinds, not shown here. (You can also view DC operating voltages,
currents and small-signal parameters in S-Edit.)
15
DC ANALYSIS - temperature=25.0
v(N_1) = 3.1819e+000
v(N_2) = 1.0000e+000
v(Vdd) = 3.3000e+000
i1(VVin) = -0.0000e+000
i2(VVin) = 0.0000e+000
i1(VVpower) = -1.9514e-004
i2(VVpower) = 1.9514e-004
Section 1.13.2 DC Transfer Analysis and Parameter Sweep

T-Spice Netlist: \Designs\Inverter\SimulationResults\InverterDC.sp
Cell: Inverter_TestBench DCAnalysis Schematic
DC transfer analysis is used to study the voltage or current at one set of points in a circuit as
a function of the voltage or current at another set of points. This is done by sweeping the
source variables over specified ranges and recording the output.
This schematic includes a .print command, which measures and records voltages at the
input and output nodes of the circuit. The command is contained within the DC analysis
output cell.
1.13.2.1. Run Simulation from S-Edit
Press the S-Edit icon ( ) to run the simulation from S-Edit. S-Edit will automatically launch
T-Spice and will create and run a T-Spice netlist file named InverterOP.sp. The netlist will
be exported as follows:

.probe
.option probev

* Design: Inverter / Cell: Inverter_TestBench / View: DCAnalysis /
Page:
* Info: DC analysis testbench of an inverter
* Date: 10/15/2008 9:49:36 AM
* Revision: 6
*************** Subcircuits *****************

16

* Info: Inverter
* Date: 5/30/2008 4:06:39 PM
* Revision: 13

PD=4.3u
PD=7.5u
.ends

*********
.param Vpwr = 3.3v

XX1 In Out Gnd Vdd INV
CC1 Out Gnd 1p
VVin In Gnd DC 1
.PRINT DC V(Out)
.PRINT DC V(In)

.dc lin VVin 0.0 Vpwr 0.02
.step lin Vpwr 2.3 4.3 0.5
.end
The .DC command, indicating transfer analysis, is followed by the parameter lin, which
specifies a linear sweep. Next is a list of sources to be swept, and the voltage ranges across
which the sweeps are to take place. In this example, VVin will be swept from 0 to Vpwr
volts in 0.02 volt increments. The .step command then sweeps Vpwr from 2.3 to 4.3 volts in
0.5 volt increments.
The transfer analysis will be performed as follows: Vpwr will be set at 2.3 volts and VVin will
be swept over its specified range; Vpwr will then be incremented to 2.5 volts and VVin will
be reswept over its range; and so on, until Vpwr reaches the upper limit of its range.
The .DC command ignores the values assigned to the voltage sources Vpwr and VVin in
the voltage source statements; however, they must be declared in those statements. The
resulting voltages for nodes In and Out are reported by the .PRINT DC command to the
specified destination.
1.13.2.3. Output
17
When W-Edit launches, simulation results of the same data type, which in this case is
voltage, are automatically plotted on a single chart. In this example, traces were separated
into different charts and reorganized (according to data type) using the commands in Chart
> Expand Chart (page 109) of the W-Edit menu.
The charts below show input and output voltages to the circuit, with separate traces for each
sweep of v(Out). To view detailed information about a trace, double-click on the trace or on
the trace label located in the upper right corner of the chart.
The Trace Properties dialog displays the value of parameter v(Out) corresponding to each
trace, as well as labels and line properties. For more information on trace properties, see
"Properties" on page 100 of the W-Edit User Guide.
18
Section 1.13.3 Transient Analysis

T-Spice Netlist: \Designs\Inverter\SimulationResults\InverterTRAN.sp
Cell: Inverter_TestBench TransientAnalysis Schematic
Transient analysis provides information on how circuit elements vary with time. The basic T-
Spice command for transient analysis has three modes. In the Op mode (default), the DC
operating point is computed, and T-Spice uses this as the starting point for the transient
simulation. This example illustrates this option. The other startup modes, Powerup and
Preview, are shown in the proceeding examples titled Transient Analysis, Powerup Mode
and Transient Analysis, Preview Mode.
1.13.3.1. Run Simulation from S-Edit
Press the S-Edit icon ( ) to run the simulation from S-Edit. S-Edit will automatically launch
T-Spice and will create and run a T-Spice netlist file named InverterTRAN.sp. The netlist
will be exported as follows:
19
.probe
.option probev
.option probei

* Design: Inverter / Cell: Inverter_TestBench / View:
TransientAnalysis / Page:
* Info: Transient analysis testbench of an inverter
* Date: 10/15/2008 9:49:36 AM
* Revision: 8
*************** Subcircuits *****************

* Info: Inverter
* Date: 5/30/2008 4:06:39 PM
* Revision: 13

PD=4.3u
PD=7.5u
.ends

*********
.param Vpwr = 3.3v

XX1 In Out Gnd Vdd INV
CC1 Out Gnd 1p
VVin In Gnd PULSE(0 Vpwr 0 1n 1n 49n 100n)
.PRINT TRAN V(Out)
.PRINT TRAN V(In)
.MEASURE TRAN RiseDelay_MeasureDelay_1 TRIG v(In) VAL='(Vpwr-
0)*50/100+0' TD='0' RISE=1 TARG v(Out) VAL='(Vpwr-0)*50/100+0'
TD='0' FALL=1 OFF
.MEASURE TRAN FallDelay_MeasureDelay_1 TRIG v(In) VAL='(Vpwr-
0)*50/100+0' TD='0' FALL=1 TARG v(Out) VAL='(Vpwr-0)*50/100+0'
TD='0' RISE=1 OFF
.MEASURE TRAN AvgDelay
PARAM='(RiseDelay_MeasureDelay_1+FallDelay_MeasureDelay_1)/2.0' ON
20
.MEASURE TRAN RiseTime TRIG v(Out) VAL='(Vpwr-0)*10/100+0' TD=0

RISE=1 TARG v(Out) VAL='(Vpwr-0)*90/100+0' TD=0 RISE=1 ON
.MEASURE TRAN FallTime TRIG v(Out) VAL='(Vpwr-0)*90/100+0' TD=0
Fall=1 TARG v(Out) VAL='(Vpwr-0)*10/100+0' TD=0 FALL=1 ON

.tran 250p 300n
.end
This circuit is similar to that of DC Operating Point Analysis, except that voltage source
VVin in this schematic generates a pulse (indicated by the keyword PULSE) to In, rather
than setting a constant value.
The times and voltages that define the legs of the waveform are specified in the arguments
to PULSE. The initial current is zero amperes and the peak current is Vpwr, with an initial
delay of zero seconds. The rise and fall times are one nanosecond, with a pulse width of 49
nanoseconds and a pulse period of 100 nanoseconds. The .tran command specifies the
characteristics of the transient analysis to be performed. In this example, the maximum time
step allowed is 250 pico with a total duration of 300 nanoseconds.
1.13.3.3. Output
21
Section 1.14 Lights (Traffic Light Controller)
DesignType: Digital
Features: S-Edit
L-Edit SPR, StdDRC, StdExtract, HiPer Verify
LVS
S-Edit Design: \Designs\Lights\Lights.tanner

Cell: Lights
This example shows the organization of a project into libraries. Here Lights is the main
design. The schematic can be exported to a TPR netlist for use in Standard Place and
Route in L-Edit.
L-Edit Design: \Designs\Lights\Lights.tdb

Cell: Lights
This example shows how to perform Standard Cell Place and Route. Use netlist file
Lights.tpr exported from S-Edit with Standard Cell Library Lightslb.tdb to perform SPR.
DRC can be performed using Standard DRC or HiPer DRC using

\Process\Generic250nm\Generic250nmTech\Generic_025-DRC.cal
Completed layout can be extracted with Standard Extraction using extraction definition file
Lights.ext.
LVS Database : \Designs\Lights\Lights.vdb
Compare the extracted layout netlist Lights.spc with the schematic netlist Lights.sp to
track down any discrepancies.
Section 1.15 LinearFeedbackShiftRegister
Section 1.16 MonitorVoltageRange-Verilog
Section 1.17 MOS_Subthreshold
Section 1.18 MultipleSymbolViews
DesignType: Digital
Features: S-Edit
Section 1.18.1 MOSFET with 4- and 3-terminal symbols
22
S-Edit Design: \Designs\MultipleSymbolViews\MultipleSymbolViews.tanner

Cell: Toplevel, Devices\NMOS
This example illustrates the use of multiple views in a cell. The cell NMOS in the Devices
library is an NMOS MOSFET, and there is a 4-terminal symbol and a 3-terminal symbol
whose fourth terminal is automatically connected to ground. Cell NMOS consists of two
interface views and two symbol views, as follows:
4-terminal NMOS MOSFET interface view: NMOS4

4-terminal NMOS MOSFET symbol view: NMOS4
3-terminal NMOS MOSFET interface view: NMOS3
3-terminal NMOS MOSFET symbol view: NMOS3
There is no schematic view for cell NMOS as the cell is a SPICE primitive.
The fourth terminal of the 3-terminal MOSFET in view NMOS3 is connected to ground by
writing 0 in the SPICE.OUTPUT property. Compare the SPICE properties of each symbol.
4-terminal SPICE.OUTPUT properties (Note that SPICE.OUTPUT is omitted):
SPICE.PREFIX = M
SPICE.PINORDER = D G S B
SPICE.MODEL = $Model
SPICE.PARAMETERS = W= L= M~ AS= PS= AD= PD= NRD~ NRS~ RDC~ RSC~ RSH~ GEO~
TABLES~
3-terminal SPICE.OUTPUT properties:
SPICE.PREFIX = M
SPICE.PINORDER = D G S
SPICE.PARAMETERS = W= L= M~ AS= PS= AD= PD= NRD~ NRS~ RDC~ RSC~ RSH~ GEO~
TABLES~
SPICE.OUTPUT = ${SPICE.PREFIX}$Name %% 0 $Model $$
Cell PMOS is a 4- and 3-terminal PMOS MOSFET, analogous to NMOS.
Section 1.18.2 NMOS with IEEE and IEC symbols

Cell: NOR2
This example illustrates the use of multiple symbol views in a cell. The cell NOR2 is a NOR
gate, and there is an IEEE and IEC symbol view. Cell NOR2 consists of one interface view,
two symbol views, and one schematic view, as follows:
Interface view: Main

IEEE symbol view: IEEE
IEC symbol view: IEC
Schematic view: Main
23
Both symbols IEEE and IEC each reference the same interface and the same schematic.
The only difference is how the symbol will look when instanced into a schematic.
Section 1.18.3 Adder with 3 different symbols

Cell: Adder
This example illustrates the use of multiple symbol views in a cell. The cell is an Adder, and
there are three symbol views, one interface view, and one schematic view, as follows:
Interface view: Main

Schematic view: Main
Symbol view sequentially ordered: Pins_Sequential
Symbol view interleaved: Pins_Interleaved
Symbol view bus: Pins_Bus
When drawing a schematic, it is sometimes convenient to have the pins of a symbol

arranged in one particular order for making connections, and at other times one wants the
pins arranged in a different order. This can be accomplished by having multiple symbol
views, each of which has a different arrangement of pins. Here, one symbol
(Pins_Sequential) has input pins ordered on the left side as A0, A1, A2, A3, B0, B1, B2, B3,
a second symbol (Pins_Interleaved) has pins ordered as A0, B0, A1, B1, A2, B2, A3, B3,
and a third symbol (Pins_Bus) has pins grouped in busses. This is purely for drawing
convenience, and does not affect the order of pins as written to SPICE.
Section 1.19 OpAmp
DesignType: Analog
Features: S-Edit
T-Spice Analysis Examples AC, AC_Noise, DC_Op_Point,
DC_Sweep
Section 1.19.1 AC Analysis
S-Edit Design: \Designs\OpAmp\Inverter.tanner

T-Spice Netlist: \Designs\OpAmp\SimulationResults\OpAmpAC.sp
Cell: OpAmp_TestBench AC_Noise_Analysis Schematic
AC analysis characterizes the circuits behavior dependence on small-signal input

frequency. It involves three steps: (1) calculating the DC operating point; (2) linearizing the
circuit; and (3) solving the linearized circuit for each frequency.
This example involves a standard operational amplifier, consisting of one PMOS, one
NMOS, a transconductance amplifier and one capacitor.

.option Accurate
24
.probe
.option probev
.option probei

* Design: OpAmp / Cell: OpAmp_TestBench / View: AC_Noise_Analysis /
Page:
* Info: AC & Noise Testbench for Op Amp
* Date: 10/15/2008 9:48:41 AM
* Revision: 7
*************** Subcircuits *****************

.subckt TransAmp in1 in2 out vbias Gnd Vdd
* Design: OpAmp / Cell: TransAmp / View: Main / Page:
* Info: Transconductance Amplifier
* Date: 10/15/2008 9:24:13 AM
* Revision: 4

MMN1 vm1 in1 vn1 0 NMOS25 W=2u L=2u AS=1.8p PS=5.8u AD=1.8p PD=5.8u
MMN2 out in2 vn1 0 NMOS25 W=2u L=2u AS=1.8p PS=5.8u AD=1.8p PD=5.8u
MMN3 vn1 vbias Gnd 0 NMOS25 W=2u L=3u AS=1.8p PS=5.8u AD=1.8p
PD=5.8u
MMP1 vm1 vm1 Vdd Vdd PMOS25 W=2u L=2u AS=1.8p PS=5.8u AD=1.8p
PD=5.8u
MMP2 out vm1 Vdd Vdd PMOS25 W=2u L=2u AS=1.8p PS=5.8u AD=1.8p
PD=5.8u
.ends
.subckt OpAmp Out in1 in2 vbias Gnd Vdd

* Design: OpAmp / Cell: OpAmp / View: Main / Page:
* Info: Operational Amplifier
* Date: 10/15/2008 9:24:13 AM
* Revision: 54

XX1 in1 in2 vf1 vbias Gnd Vdd TransAmp
CComp vf1 Out 200f
MMN1 Out vbias Gnd 0 NMOS25 W=3u L=2u AS=2.7p PS=7.8u AD=2.7p
PD=7.8u
25
MMP1 Out vf1 Vdd Vdd PMOS25 W=6u L=2u AS=5.4p PS=13.8u AD=5.4p
PD=13.8u
.ends

*********
.param Vpwr = 3.3v

XX1 Out in1 in2 Bias Gnd Vdd OpAmp
CCout Out Gnd 200f
VVcm in2 Gnd DC Vpwr/2
VVbias Bias Gnd DC 700m
VVpwrPos Vdd Gnd DC Vpwr
VVdiff in1 in2 DC 0 AC 1 0
.PRINT AC Vdb(Out)
.PRINT AC Vp(Out)
.PRINT NOISE INOISE
.PRINT NOISE ONOISE
.PRINT NOISE TRANSFER dn(XX1.XX1.MMN3)
.MEASURE AC Gain<db> MAX vdb(Out) ON
.MEASURE AC PhaseMargin<deg> FIND 'vp(Out)' WHEN vdb(Out)=0 ON
.MEASURE AC UnityGainFrequency<Hz> WHEN Vdb(Out)=0 ON
.MEASURE AC MeasureGainBandwidthProduct_1_Gain MAX vdb(Out) OFF
.MEASURE AC MeasureGainBandwidthProduct_1_UGFreq WHEN Vdb(Out)=0 OFF
.MEASURE AC GainBandwidth<Hz>
PARAM='MeasureGainBandwidthProduct_1_Gain*MeasureGainBandwidthProduc
t_1_UGFreq' ON
.MEASURE NOISE InputNoise<nv/Hz^0.5> FIND 'inoise/1E-9' WHEN
Vdb(Out)=0 ON

.op
.ac dec 10 1 100Meg
.noise v(Out) VVdiff 5
.end
Three voltage sources (in addition to Vdd) are defined.
Vdiff sets the DC voltage difference between nodes in2 and in1 to 0 volts. The AC
magnitude is 1 volt and its AC phase is 0 degrees.
Vcm sets node in2 to 2 volts, relative to GND.
Vbias sets node vbias to 700 millevolts, relative to GND.
The .ac command performs an AC analysis. Following the .ac keyword is information
concerning the frequencies to be swept during the analysis. In this case, the frequency is
swept logarithmically, by decades (dec); 10 data points are to be included per decade; the
26
starting frequency is 1 Hz and the ending frequency is 100 MHz. The .PRINT command
writes the voltage magnitude (in decibels) and phase (in degrees), respectively, for the node
Out to the specified file. The other print and measurement commands are discussed in
alternate examples.
1.19.1.2. Output
The AC simulation will result in AC small-signal model parameters being written to the
output file, in addition to all output generated from the .print statements.
27
Section 1.20 Parameterized_NAND
DesignType: Digital
Features: S-Edit
T-Spice Analysis Examples Transient
Section 1.20.1 Using Subcircuits
S-Edit Design: \Designs\Parameterized_NAND\Parameterized_NAND.tanner

T-Spice Netlist: \Designs\Parameterized_NAND\SimulationResults\SubcircuitTRAN.sp
Cell: Subcircuit_TestBench
Subcircuit definitions allow arbitrarily complex arrangements of nodes and devices to be

easily reused multiple times in a circuit. A subcircuit definition in S-Edit is contained within a
cell definition, and is comprised of both a schematic view and a symbol view. Each instance
of the symbol encapsulates the subcircuit schematic, allowing a simple but complete
representation of subcircuit dynamics. This example uses a NAND gate to illustrate the use
of subcircuit definitions and subcircuit parameters.
An instance of the subcircuit NAND2C is created in the schematic and labeled X1. To
access NAND2C from the main schematic, double-click on the NAND2C item in the
Libraries list.
28
As discussed in DC Operating Point Analysis, symbol properties are used to define

component properties such as length and width. This example introduces a new symbol
property, SPICE.PARAMETERS, which allows parameters to be passed through a
hierarchical netlist.
The symbol that represents NAND2C has the SPICE parameter property:
SPICE.PARAMETER = L= NW= PW=
This property specifies that the cell properties L, NW, and PW are subcircuit parameters of
NAND2C. The cell also contains the three additional property definitions:
L = 0.5u
NW = 4.0u
PW = 8.0u
These parameters define properties of all n-channel and p-channel MOSFETS within the
subcircuit such that L represents the length property of both n- and p-channel MOSFETS,
NW represents n-channel width and PW represents p-channel width.
Attaching these parameters to NAND2C allows component properties within the subcircuit
definition to be controlled in the subcircuit call.

.option
search="\TannerToolsShippingFiles.NEW\Process\Generic250nm\Generic2
50nmTech"
.probe
.option probev
.option probei

* Design: Parameterized_NAND / Cell: Subcircuit_TestBench / View:
Main / Page:
* Info: Testbench for subcircuit example
* Date: 1/12/2009 10:57:20 AM
* Revision: 9
*************** Subcircuits *****************

.subckt NAND2C A B Out Outbar Gnd Vdd L=0.5u NW=4.0u PW=8.0u
* Design: Parameterized_NAND / Cell: NAND2C / View: Main / Page:
* Info: 2 Input NAND with complementary output.
* Date: 1/12/2009 2:09:59 PM
* Revision: 12
29
MM4p Out B Vdd Vdd PMOS25 W=PW L=L M=2 AS='if(0,

(650n*if(0,PW/1,PW)+floor(2/2)*750n*if(0,PW/1,PW)),
(2*650n*if(0,PW/1,PW)+(floor(2/2)-1)*750n*if(0,PW/1,PW)))' PS='if(0,
(2*650n+if(0,PW/1,PW)+if(0,PW/1,PW)*1+floor(2/2)*2*(750n+if(0,PW/1,P
W)*1)), (2*2*650n+if(0,PW/1,PW)+if(0,PW/1,PW)*1+(floor(2/2)-
1)*2*(750n+if(0,PW/1,PW)*1)))' AD='if(0,
floor(2/2)*750n*if(0,PW/1,PW))' PD='if(0,
W)*1)), floor(2/2)*2*(750n+if(0,PW/1,PW)*1))'
MM2n Out A 1 0 NMOS25 W=NW L=L AS='if(1,
(650n*if(0,NW/1,NW)+floor(1/2)*750n*if(0,NW/1,NW)),
(2*650n*if(0,NW/1,NW)+(floor(1/2)-1)*750n*if(0,NW/1,NW)))' PS='if(1,
(2*650n+if(0,NW/1,NW)+if(0,NW/1,NW)*1+floor(1/2)*2*(750n+if(0,NW/1,N
W)*1)), (2*2*650n+if(0,NW/1,NW)+if(0,NW/1,NW)*1+(floor(1/2)-
1)*2*(750n+if(0,NW/1,NW)*1)))' AD='if(1,
floor(1/2)*750n*if(0,NW/1,NW))' PD='if(1,
W)*1)), floor(1/2)*2*(750n+if(0,NW/1,NW)*1))'
MM3p Out A Vdd Vdd PMOS25 W=PW L=L M=2 AS='if(0,
1)*2*(750n+if(0,PW/1,PW)*1)))' AD='if(0,
W)*1)), floor(2/2)*2*(750n+if(0,PW/1,PW)*1))'
MM1n 1 B Gnd 0 NMOS25 W=NW L=L AS='if(1,
1)*2*(750n+if(0,NW/1,NW)*1)))' AD='if(1,
W)*1)), floor(1/2)*2*(750n+if(0,NW/1,NW)*1))'
MM5n Outbar Out Gnd 0 NMOS25 W=NW L=L AS='if(1,
1)*2*(750n+if(0,NW/1,NW)*1)))' AD='if(1,
W)*1)), floor(1/2)*2*(750n+if(0,NW/1,NW)*1))'
MM6p Outbar Out Vdd Vdd PMOS25 W=PW L=L M=2 AS='if(0,
30
1)*2*(750n+if(0,PW/1,PW)*1)))' AD='if(0,
W)*1)), floor(2/2)*2*(750n+if(0,PW/1,PW)*1))'
.ends

*********
.param Vpwr = 3.3v

XX1 A N_1 Out N_2 Gnd Vdd NAND2C L=0.5u NW=4.0u PW=8.0u
VVb N_1 Gnd DC 5
VVin A Gnd PULSE(0 Vpwr 0 1n 1n 49n 100n)
.PRINT TRAN V(Out)
.PRINT TRAN V(A)
.PRINT TRAN V(X1/1)

.tran/Powerup 250p 300n
.end
Subcircuits are defined by blocks of device statements bracketed with the .subckt and
.ends commands, and instanced by statements beginning with the key letter X. The
.subckt command includes the name of the subcircuit being defined (NAND2C), a list of
terminals, and three subcircuit parameters. The terminals do not have a predefined order,
but whatever order is used in the definition must be used in instances. Parameters can be
written in any order in both the definition and the instances. If a parameter value is not
specified in the instance the value in the definition is used as the default.
Within the subcircuit definition, four MOSFETs are defined in the usual mannerand in
these statements the order of terminals is important: draingatesourcebulk. Node 1 is the
source of transistor MM2n and the drain of transistor MM1n. Subcircuit parameters,
enclosed by single quotes, are used in place of numerical values.After the subcircuit is
defined, you can create an instance of the subcircuit. The instance statement
begins with the key letter X. The name of the instance, by which it is to be identified in the
rest of the
input file, is X1 (not "XX1.")
The list of terminals in the instance statement must have the same order as on the first line
of the
31
subcircuit definition so that A B Out Gnd in the definition corresponds to Vin N_1 OUT Gnd
in the
instance. The next argument of the instance statement is the original subcircuit name
NAND.
The default subcircuit parameter values, as specified by the definition, are overridden by
instancespecific
value assignments, which can appear in any order. Any parameters omitted from the
instance
statement retains its default value.
A standard DC operating point calculation (.OP) analysis is carried out on this circuit, with a
duration of
300 nanoseconds and a maximum timestep of 250 picoseconds. The .param command sets
the initial
node voltages to 3.3 volts. The .PRINT command reports simulation results for the voltages
at nodes
Vin, OUT, and X1/N_1.
1.20.1.2. Output
Section 1.21 PLL-Behavioral
Section 1.22 Pseudo-random Bit Sequence-Verilog
32
Section 1.23 ReadTextFile-Verilog
Section 1.24 Resonator
Section 1.25 RingOscillator
Section 1.26 RingOscillator-Behavioral
Section 1.27 RingVCO
Section 1.28 SpiceOutput
DesignType: Digital
Features: S-Edit
Section 1.28.1 SPICE Primitives
S-Edit Design: \Designs\SpiceOutput\SpiceOutput.tanner

Cell: NMOS4, PMOS4, INV
This example illustrates the use of the SPICE.OUTPUT property to output SPICE for a
primitive device. A primitive device is the lowest level device, for which there is no
schematic, and the output to SPICE is determined by the SPICE.OUTPUT property on the
symbol. The symbol of cell NMOS4 (an NMOS transistor), view NMOS4, has several
properties:
AD = ${W}*1.25u*${M}
AS = ${W}*1.25u*${M}}
L = 0.25u
M=1
Model = NMOS
NRD = 0
NRS = 0
PD = 2*(${W}+1.25u)*${M}
PS = 2*(${W}+1.25u)*${M}
RDC = 0
RSC = 0
RSH = 0
W = 2.50u
A SPICE.OUTPUT property on the symbol specifies the SPICE call written for each instance
of the symbol, and a SPICE.PRIMITIVE property set to True on the symbol indicates that
33
the device is a primitive. The SPICE.OUTPUT and SPICE.PRIMITIVE properties for the
symbol are as follows:
SPICE.OUTPUT = M${Name} %{D} %{G} %{S} %{B} ${Model} W=${W} L=${L} M=${M} AS=${AS}
PS=${PS} AD=${AD} PD=${PD}
SPICE.PRIMITIVE = True
The SPICE Export Control Property to enter when exporting SPICE is the name of the
property that contains the sub properties OUTPUT and PRIMITIVE. In this case, the word
SPICE is the Export Control property. Inspecting the SPICE.OUTPUT statement in detail,
each element of the property is written out as follows:
M Write M literally
${Name} Write the name of the instance
%{D}, %{G}, %{S}, %{B} Write the net names connected to pins D, G, S, and B
${Model} Write the value of the property Model on this instance
W= Write W= literally
${W} Write the value of the property W on this instance
L= Write L= literally
${L} Write the value of the property L on this instance
M= Write M= literally
${M} Write the value of the property M on this instance
AS= Write AS= literally
${AS} Write the value of the property AS on this instance
PS= Write PS= literally
${PS} Write the value of the property PS on this instance
AD= Write AD= literally
${AD} Write the value of the property AD on this instance
PD= Write PD= literally
${PD} Write the value of the property PD on this instance
The symbol of cell PMOS4, view PMOS4, has similar properties and a similar
SPICE.OUTPUT property as cell NMOS4, view NMOS4. Cell INV makes use of cells
NMOS4, view NMOS4 and PMOS4, view PMOS4. The SPICE output for the schematic of
INV is as follows:
MP1 Out A Vdd Vdd PMOS W=2.5u L='0.25u-(10n*match)' M=1 AS=3.125p

PS=7.5u AD=3.125p PD=7.5u
MN1 Out A Gnd Gnd NMOS W=2.5u L='0.25u-(10n*match)' M=1 AS=3.125p
PS=7.5u AD=3.125p PD=7.5u
We can see the substitutions of the instance name, net names, and property values in each
SPICE call line, according to the table above.
An alternate method that may be used instead of defining one SPICE.OUTPUT property to
specify the SPICE call is to define the SPICE.PREFIX, SPICE.PINORDER, SPICE.MODEL,
and SPICE.PARAMETERS properties. These four properties when used in conjunction with
each other will also specify the SPICE call written for each instance of the symbol. An
example of this is shown in symbol NMOS4, view NMOS4_Expand. The SPICE.PREFIX,
SPICE.PINORDER, SPICE.MODEL, and SPICE.PARAMETERS properties are as follows:
34
SPICE.PREFIX = M
SPICE.PINORDER = D G S B
SPICE.PARAMETERS = W= L= M~ AS= PS= AD= PD= NRD~ NRS~ RDC~ RSC~ RSH~
Inspecting the SPICE.PREFIX statement, the property is written out as follows:
M Write M literally followed by the name of the instance
The output of SPICE.PREFIX will be followed by the SPICE.PINORDER statement, the

SPICE.PINORDER property is written out as follows:
DGSB Write the net names connected to pins D, G, S, and B
The output of SPICE.PINORDER will be followed by the SPICE.MODEL statement, the

SPICE.MODEL property is written out as follows:
$Model Write the value of the property Model on this instance
The output of SPICE.MODEL will be followed by the SPICE.PARAMETERS statement, the

.PARAMETERS property is written out as follows:
W= Write W= literally followed by the value of the property W on this instance

L= Write L= literally followed by the value of the property L on this instance
M~ Write M= literally followed by the value of the property M on this instance
only if the value of M differs from its default value
AS= Write AS= literally followed by the value of the property AS on this
instance
PS= Write PS= literally followed by the value of the property PS on this
instance
AD= Write AD= literally followed by the value of the property AD on this
instance
PD= Write PD= literally followed by the value of the property PD on this
instance
NRD~ Write NRD= literally followed by the value of the property NRD on this
instance only if the value of NRD differs from its default value
NRS~ Write NRS= literally followed by the value of the property NRS on this
instance only if the value of NRS differs from its default value
RDC~ Write RDC= literally followed by the value of the property RDC on this
instance only if the value of RDC differs from its default value
RSC~ Write RSC= literally followed by the value of the property RSC on this
instance only if the value of RSC differs from its default value
RSH~ Write RSH= literally followed by the value of the property RSH on this
instance only if the value of RSH differs from its default value
Section 1.28.2 Passing parameters down hierarchy

Cell: Top_Inverters
35
This example illustrates how parameters can be passed down the hierarchy and written to
SPICE. Cell Top_Inverters contains three instances of cell INV. The symbol for INV contains
a property:
match=0
The first instance has no local override of match; the second instance has a local override:
match=1
The third instance has a local override:
match=2
The SPICE output for the schematic of Top_Inverters is as follows:
.subckt INV A Out Gnd Vdd match=0

PS=7.5u AD=3.125p PD=7.5u
PS=7.5u AD=3.125p PD=7.5u
.ends
XINV1 In Out1 Gnd Vdd INV match=0

Section 1.28.3 Subcircuits

Cell: Dig0, Dig1, Dig2, Top_Subcircuits
This example illustrates how to use the SPICE.OUTPUT and SPICE.DEFINITION properties
to control the SPICE output written for a subcircuit. A subcircuit is a symbol that is not a
primitive. The symbol for cell Dig0 has no SPICE.OUTPUT or SPICE.DEFINITION
properties. When no SPICE.DEFINITION property is present, the subcircuit definition will
contain all pins listed in alphabetical order, with global ports listed last, also in alphabetical
order. When no SPICE.OUTPUT property is present (nor the SPICE.PREFIX,
SPICE.PINORDER, SPICE.MODEL, or SPICE.PARAMETERS properties), the SPICE
written, corresponding to each symbol instance, will contain all pins followed by all interface
parameters. An interface parameter is a parameter with sub-property:
IsInterface = True
Exporting SPICE for cell Top_Subcircuits, we see the definition and call for Dig0 appears as
follows:
.subckt Dig0 Clk Data<0> Data<1> Data<2> Data<3> Out<0> Out<1>

Out<2> Out<3> Vdd
.ends
...
36
XXdig0 Clock A<0> A<1> A<2> A<3> BA<0> BA<1> BA<2> BA<3> PWR Dig0
Now consider cell Dig1. Cell Dig1 demonstrates the use of the SPICE.DEFINITION property
to pass parameters to the definition of a subcircuit. The symbol for cell Dig1 has a
SPICE.DEFINITION property as follows:
SPICE.DEFINITION = .subckt $Cell %% $$ Level = 5
Inspecting the SPICE.DEFINITION statement in detail, each element of the property is

written out on the SPICE definition interface as follows:
subckt Write .subckt literally

$Cell Write the name of the cell
%% Write the names of the ports on the symbol in the default order.
$$ Write all interface properties, written as property_name1 = property_value1

Level = 5 Write Level = 5 literally
Exporting the SPICE for cell Top_Subcircuits, we see the definition and call for Dig1
appears as follows:
.subckt Dig1 Clk Data<0> Data<1> Data<2> Data<3> Out<0> Out<1>

Out<2> Out<3> Vdd P1=10 P2=20 Level = 5
.ends
...
XXdig1 Clock A<0> A<1> A<2> A<3> BB<0> BB<1> BB<2> BB<3> PWR Dig1
P1=10 P2=20
Now consider cell Dig2. Cell Dig2 demonstrates the use of the SPICE.OUTPUT and
SPICE.DEFINITION properties to customize the pin order and to add special syntax to the
definition and call for a subcircuit. The symbol for cell Dig2 has a SPICE.DEFINITION and
SPICE.OUTPUT property as follows:
SPICE.DEFINITION = .subckt $Cell (%{Data<3:0>}) %{Vdd} %{Clk} (%{Out<0:3>})

SPICE.OUTPUT = X${Name} (%{Data<3:0>}) %{Vdd} %{Clk} (%{Out<0:3>}) $MasterCell
Inspecting the SPICE.DEFINITION statement in detail, each element of the property is

written out on the SPICE definition interface as follows:
.subckt Write .subckt literally

$Cell Write the name of the cell
( Write ( literally
%{Data<3:0>} Write Data ports, reversing the default order
) Write ) literally
%{Vdd} Write Vdd port
%{Clk} Write Clk port
( Write ( literally
%{Out<0:3>} Write Out ports
) Write ) literally
37
Inspecting the SPICE.OUTOUT statement in detail, each element is similarly constructed.

Exporting the SPICE for cell Top_Subcircuits, we see the definition and call for Dig2
appears as follows:
.subckt Dig2 (Data<3> Data<2> Data<1> Data<0>) Vdd Clk (Out<0>

Out<1> Out<2> Out<3>)
.ends
...
XXdig2 (A<3> A<2> A<1> A<0>) PWR Clock (BC<0> BC<1> BC<2> BC<3>)
Dig2
38
Section 1.28.4 SPICE Export Control property

Cell: PMOS4
This example illustrates the use of the SPICE Export Control Property to control the SPICE
output for a device. For a given device, one may want to define several SPICE output
properties, for example a default property, a basic property, and a detailed property. Each
property might have different parameters for different levels of simulation. The SPICE Export
Control property determines which output property is used when writing out a SPICE netlist.
When a list of property names is entered in the Export Control Property, SPICE will be
written according to the first Export Control Property in the list that exists on the device
being written. The Export Control Property can be set in the File > Export > Export
SPICE Property Name field or in the Setup > SPICE Simulation Netlisting
Options SPICE Export Control Property field.
Consider cell PMOS4 (a PMOS transistor), view PMOS4. Three SPICE.OUTPUT properties
are defined, as shown below. The SPICE Export Control Properties for these Output
properties are SPICE_BASIC, SPICE, and SPICE_DETAILED.
SPICE_BASIC.OUTPUT = M${Name} %{D} %{G} %{S} %{B} ${Model} W=${W} L=${L}
SPICE.OUTPUT = M${Name} %{D} %{G} %{S} %{B} ${Model} W=${W} L=${L} M=${M} AS=${AS}
PS=${PS} AD=${AD} PD=${PD}
SPICE_DETAILED.OUTPUT = M${Name} %{D} %{G} %{S} %{B} ${Model} W=${W} L=${L} M=${M}
AS=${AS} PS=${PS} AD=${AD} PD=${PD} NRD=${NRD} NRS=${NRS} RDC=${RDC} RSC=${RSC}
RSH=${RSH}
If we export SPICE from cell INV, and enter SPICE_DETAILED, SPICE, SPICE_BASIC for
the SPICE Control Property, we get the following output:

PS=7.5u AD=3.125p PD=7.5u NRD=0 NRS=0 RDC=0 RSC=0 RSH=0
PS=7.5u AD=3.125p PD=7.5u
The SPICE_DETAILED.OUTPUT property was used to export the PMOS4 instance

because it was first in the SPICE Control Property list and it existed on the PMOS4 instance.
No SPICE_DETAILED.OUTPUT property exists on the NMOS4 instance, so the next
property in the list was used, which is the SPICE.OUTPUT property.
If we export SPICE from cell INV, and enter SPICE_BASIC, SPICE for the SPICE Control
Property, we get the following output:
MP1 Out A Vdd Vdd PMOS W=2.5u L='0.25u-(10n*match)'

PS=7.5u AD=3.125p PD=7.5u
The SPICE_BASIC.OUTPUT property was used to export the PMOS4 instance because it
was first in the SPICE Control Property list and was present on the PMOS4 instance. No
39
SPICE_BASIC.OUTPUT property exists on the NMOS4 instance, so the next property in the
list was used, which is the SPICE.OUTPUT property.
If we export SPICE from Cell INV and enter only SPICE for the SPICE Control Property, we
get the following output:

PS=7.5u AD=3.125p PD=7.5u
PS=7.5u AD=3.125p PD=7.5u
The SPICE.OUTPUT property was used for both the PMOS4 and NMOS4 instances.
Section 1.29 Stimuli
Section 1.30 XOR
Section 2 Process
Section 2.1 Gallium Arsenide (GaAs)
Folder Path: \Process\ProcessName\GaAs\GaAsTech

GaAs.tdb Description
Description
Section 2.2 Generic 0.25um
Section 2.2.1 Analog Symbols Library
Folder Path: \Process\Generic250nm\Generic250nmAnalogLib

Generic250nmAnalogLib.tanner Description
Description
Section 2.2.2 Device Symbols Library
Folder Path: \Process\Generic250nm\Generic250nmDevices

Generic250nmDevices.tanner Description
Description
Section 2.2.3 I/O Pad Symbols Library
40
Folder Path: \Process\Generic250nm\Generic250nmIO_Pads

Generic250nmIO_Pads.tanner Description
Description
Section 2.2.4 Logic Gate Symbols Library
Folder Path: \Process\Generic250nm\Generic250nmLogicGates

Generic250nmLogicGates.tanner Description
Description
Section 2.2.5 Technology Files
Folder Path: \Process\Generic250nm\Generic250nmTech

Calibre025_4M.drc Description
Dracula025_4M.drc
Generic025umTCells.dll
Generic_025.drf
Generic_025.ext
Generic_025.lib
Generic_025.tdb
Generic_025.tf
Generic_025.xst
Generic_025-Ant.cal
Generic_025-Density.cal
Generic_025-DRC.cal
Generic_025-Ext.cal
SpecialDevices.md
Description
Section 2.3 MOSIS Scalable AMIS 0.8um
Folder Path: \Process\MOSIS_Scalable_AMIS_0800nm\

MOSIS_Scalable_AMIS_0800nmTech
mamin08.ext Description
mamin08.tdb Description
mamin08.xst Description
Description
Section 2.4 MOSIS Scalable AMIS 1.2um
41
Folder Path: \Process\MOSIS_Scalable_AMIS_1200nm\

MOSIS_Scalable_AMIS_1200nmTech
mamin12.ext Description
mamin12.tdb Description
mamin12.xst Description
Description
Section 2.5 MOSIS Scalable HP 0.5um
Folder Path: \Process\MOSIS_Scalable_HP_500nm\

MOSIS_Scalable_HP_500nmTech
mhp_n05.ext Description
mhp_n05.tdb Description
mhp_n05.xst Description
mhp_n05-soft.ext Description
Description
Section 2.6 MOSIS Scalable Orbit 1.2um
Folder Path: \Process\MOSIS_Scalable_Orbit_1200nm\

MOSIS_Scalable_Orbit_1200nmTech
morbn12.ext Description
morbn12.tdb Description
morbn12.xst Description
Description
Section 2.7 MOSIS Scalable Orbit 2.0um
Folder Path: \Process\MOSIS_Scalable_Orbit_2000nm\

MOSIS_Scalable_Orbit_2000nmTech
morb20cc.ext Description
morbn20.ext Description
morbn20.xst Description
Description
Section 2.8 Native Orbit 1.2um
Folder Path: \Process\Orbit_1200nm\Orbit_1200nmTech

orbtn12.ext Description
orbtn12.tdb Description
orbtn12.xst Description
orbtp12.ext Description
orbtp12.tdb Description
orbtp12.xst Description
42
Description
Section 2.9 Native Orbit 2.0um
Folder Path: \Process\Orbit_2000nm\Orbit_2000nmTech

orbtn20.ext Description
orbtn20.tdb Description
orbtn20.xst Description
orbtp20.ext Description
orbtp20.tdb Description
orbtp20.xst Description
Description
Section 2.10 Generic Standard Libraries
Section 2.10.1 Device Symbols Library
Folder Path: \Process\StdLibraries\Devices

Devices.tanner Description
Description
Section 2.10.2 Miscellaneous Symbols Library
Folder Path: \Process\StdLibraries\Misc

Misc.tanner Description
Description
Section 2.10.3 SPICE Command Symbols Library
Folder Path: \Process\StdLibraries\SPICE_Commands

SPICE_Commands.tanner Description
Description
Section 2.10.4 SPICE Element Symbols Library
Folder Path: \Process\StdLibraries\SPICE_Elements

SPICE_Elements.tanner Description
Description
43
Section 3 Automated Operations
Section 3.1 S-Edit TCL Scripts
Section 3.1.1 Calculator - TK
TCL Script Path: \Features By Tool\S-Edit\Calculator_TK.tcl
Section 3.1.2 Change Symbol Property Size
TCL Script Path: \Features By Tool\S-Edit\ChangeSymbolPropertySize.tcl
Section 3.1.3 Change WhenNotEval Property
TCL Script Path: \Features By Tool\S-Edit\ChangeWhenNotEvalProperty.tcl
Section 3.1.4 Copy Cells
TCL Script Path: \Features By Tool\S-Edit\CopyCells.tcl
Section 3.1.5 Copy Cells Traverse Hierarchy
TCL Script Path: \Features By Tool\S-Edit\CopyCells_Traverse.tcl
Section 3.1.6 Delete Empty Schematic View
TCL Script Path: \Features By Tool\S-Edit\DeleteEmptySchematicView.tcl
Section 3.1.7 Delete Property
TCL Script Path: \Features By Tool\S-Edit\DeleteProperty.tcl
Section 3.1.8 Find Property on Instance - TK
TCL Script Path: \Features By Tool\S-Edit\FindInstance_TK.tcl
Section 3.1.9 Find and Rename Instance
TCL Script Path: \Features By Tool\S-Edit\FindInstance_ModifyName.tcl
Section 3.1.10 Change Port and Netlabels
TCL Script Path: \Features By Tool\S-Edit\TCLScripts\Fixup_Vdd_Labels.tcl
This sample TCL script illustrates how to cycle over all schematic views in the design, and
change all ports and netlabels called vdd to VDD.
After loading the script, there are two functions:
44
fix_vdd_names: Renames ports and net labels in the current cell from
vdd to VDD
ForEachSchematicView Iterates through all schematic views in the database,
calling fix_vdd_names
fixall: Calls ForEachSchematicView so that it will in-turn call
fix_vdd_names
To run this script, first drag and drop it into the command window, then enter fixall to run the script.
A full list of S-Edit TCL commands is available by typing help in the Command window. Help on
any specific command, as well as a list of subcommands and options, can be obtained by entering the
command name followed by -help.
Section 3.1.11 Force Callback
TCL Script Path: \Features By Tool\S-Edit\ForceCallback.tcl
Section 3.1.12 Hello World - TK
TCL Script Path: \Features By Tool\S-Edit\ HelloWorld_TK.tcl
Section 3.1.13 Resizing Text - TK
TCL Script Path: \Features By Tool\S-Edit\TCLScripts\ResizeText.tcl
This sample TCL script illustrates how to cycle through all views in a design (schematic and
symbol views) and modify the size of Ports, Netlabels, and Textlabels. It also shows how to
use TK to write a dialog to enter parameters into a script. Note the use of the toplevel
command to declare a window to write into. This is required for all TK scripts as the default
toplevel window is the S-Edit application window, which the user is not permitted to modify.
After loading the script by dragging-and-dropping it into the command window, the following
dialog appears:
Enter appropriate text sizes, then press OK to resize Ports, Netlabels, and Textlabels in all
views.
A button to run the script can be created on a toolbar by removing the comment symbol (#)
from the workspace command. Also comment out the ResizeText command so the script
does not execute immediately when it is loaded, but only when the button is pressed.
45

workspace userbutton set ResizeText
# ResizeText
The button can then be added to the toolbar by right-clicking the toolbar and selecting
Customize, selecting the Commands tab and then the category Custom. Drag the
command Execute button text as Tcl to the location the button should appear on the
toolbar. Right-Click the new button and change the name to ResizeText. To use the button
the TCL script must first be loaded by dragging-and-dropping it into the command window.
If this is a commonly used script, it can be placed in the scripts\startup folder to

automatically load when S-Edit starts up. The location of the startup folder is:
C:\Documents and Settings\<username>\Application Data\Tanner EDA\scripts\startup
Scripts can also be loaded automatically whenever a design is opened, or when S-Edit is
shutdown. The location of the folders for these scripts is:
C:\Documents and Settings\<username>\Application Data\Tanner

EDA\scripts\open.design
C:\Documents and Settings\<username>\Application Data\Tanner

EDA\scripts\shutdown
Section 3.2 L-Edit UPI Macros
Section 3.2.1 Add to Find
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\AddToFind\Filename.c

Layout Path: \Features By Tool\L-Edit\UPIMacros\AddToFind\Filename.tdb
Description
Section 3.2.2 Boolean Operations
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\

BooleanOpSelectObjects\Filename.c
Layout Path: \Features By Tool\L-Edit\UPIMacros\
BooleanOpSelectObjects\Filename.tdb
Description
46
Section 3.2.3 Capacitor
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\Capacitor\capacitr.c

DLL Path: \Features By Tool\L-Edit\UPIMacros\Capacitor\release\capacitr.dll
Description
Section 3.2.4 Change Instance Name to Include Rotation Parameter

ChangeInstanceNameToIncludeRotationParameter\Filename.c
ChangeInstanceNameToIncludeRotationParameter\Filename.tdb
DLL Path: \Features By Tool\L-Edit\UPIMacros\
ChangeInstanceNameToIncludeRotationParameter\Filename.dll
Description
Section 3.2.5 Change Layer

ChangeLayer\chnglayr.c.c
ChangeLayer\release\chnglayr.dll.dll
Description
Section 3.2.6 Change Layer and Duplicate

ChangeLayerAndDuplicate\Filename.c
ChangeLayerAndDuplicate\Filename.tdb
ChangeLayerAndDuplicate\release\Filename.dll
Description
Section 3.2.7 Change Layer and Grow

ChangeLayerAndGrow\Filename.c
ChangeLayerAndGrow\Filename.tdb
ChangeLayerAndGrow\release\Filename.dll
Description
Section 3.2.8 Create Contact
47
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\Contact\Contact.c
Description
Section 3.2.9 Copy Layer Rendering

CopyRendering\Filename.c
CopyRendering\Filename.tdb
CopyRendering\release\Filename.dll
Description
Section 3.2.10 Create Derived Layer

CreateDerivedLayer\Filename.c
CreateDerivedLayer\Filename.tdb
CreateDerivedLayer\release\Filename.dll
Description
Section 3.2.11 Delete Layer
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\DeleteLayer\Filename.c

Layout Path: \Features By Tool\L-Edit\UPIMacros\DeleteLayer\Filename.tdb
DLL Path: \Features By Tool\L-Edit\UPIMacros\DeleteLayer\release\Filename.dll
Description
Section 3.2.12 Dialog Examples
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\DialogExamples\Filename.c

Layout Path: \Features By Tool\L-Edit\UPIMacros\DialogExamples\Filename.tdb
DialogExamples\release\Filename.dll
Description
Section 3.2.13 Gear
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\Gear\Filename.c

Layout Path: \Features By Tool\L-Edit\UPIMacros\Gear\Filename.tdb
DLL Path: \Features By Tool\L-Edit\UPIMacros\Gear\release\Filename.dll
Description
48
Section 3.2.14 Generate Derived Layer in Subcell

GenerateDerivedLayerInSubCell\Filename.c
GenerateDerivedLayerInSubCell\Filename.tdb
GenerateDerivedLayerInSubCell\release\Filename.dll
Description
Section 3.2.15 Goto
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\goto\goto.c

DLL Path: \Features By Tool\L-Edit\UPIMacros\goto\release\goto.dll
Description
Section 3.2.16 Grow Via
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\GrowVia\Filename.c

Layout Path: \Features By Tool\L-Edit\UPIMacros\GrowVia\Filename.tdb
DLL Path: \Features By Tool\L-Edit\UPIMacros\GrowVia\release\Filename.dll
Description
Section 3.2.17 Hello World
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\HelloWorld\HelloWorld.c

DLL Path: \Features By Tool\L-Edit\UPIMacros\HelloWorld\
Release-VC6\HelloWorld-VC6.dll
Description
Section 3.2.18 Hide Layer with GDS DataType = 1

HideLayerWithGDSDataType1\Filename.c
HideLayerWithGDSDataType1\Filename.tdb
HideLayerWithGDSDataType1\release\Filename.dll
Description
Section 3.2.19 Hierarchical Instance Location
49

HierarchicalInstanceLocation\Filename.c
HierarchicalInstanceLocation\Filename.tdb
HierarchicalInstanceLocation\release\Filename.dll
Description
Section 3.2.20 Import GDS Copy Cell
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\ImportGDSCopyCell\Filename.c

ImportGDSCopyCell\Filename.tdb
ImportGDSCopyCell\release\Filename.dll
Description
Section 3.2.21 Instance and Rotate a T-Cell

Instance&RotateT-Cell\Filename.c
Instance&RotateT-Cell\Filename.tdb
Instance&RotateT-Cell\release\Filename.dll
Description
Section 3.2.22 Instance a Cell
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\InstanceCell\Filename.c

Layout Path: \Features By Tool\L-Edit\UPIMacros\InstanceCell\Filename.tdb
DLL Path: \Features By Tool\L-Edit\UPIMacros\InstanceCell\release\Filename.dll
Description
Section 3.2.23 Interface
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\Interface\intrface.c

DLL Path: \Features By Tool\L-Edit\UPIMacros\Interface\release\ intrface.dll
Description
Section 3.2.24 Drawing Mode Keyboard Shortcuts
50

Layer-DrawingMode Keyboard Shortcuts\Filename.c
Layer-DrawingMode Keyboard Shortcuts\Filename.tdb
Layer-DrawingMode Keyboard Shortcuts\release\Filename.dll
Description
Section 3.2.25 MFC
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\MFC\mfcupi.cpp

DLL Path: \Features By Tool\L-Edit\UPIMacros\MFC\release\mfcupi.dll
Description
Section 3.2.26 MOSFET
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\Mosfet\Mosfet.c

Layout Path: \Features By Tool\L-Edit\UPIMacros\Mosfet\Filename.tdb
DLL Path: \Features By Tool\L-Edit\UPIMacros\Mosfet\release\Filename.dll
Description
Section 3.2.27 Move
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\Move\move.c

DLL Path: \Features By Tool\L-Edit\UPIMacros\Move\release\move.dll
Description
Section 3.2.28 Palette
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\Palette\Palette.c

DLL Path: \Features By Tool\L-Edit\UPIMacros\Palette\release\Palette.dll
Description
Section 3.2.29 Perimeter
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\Perimeter\perimetr.c

DLL Path: \Features By Tool\L-Edit\UPIMacros\Perimeter\release\perimetr.dll
Description
Section 3.2.30 Place Ports
51
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\PlacePorts\Filename.c

Layout Path: \Features By Tool\L-Edit\UPIMacros\PlacePorts\Filename.tdb
DLL Path: \Features By Tool\L-Edit\UPIMacros\PlacePorts\release\Filename.dll
Description
Section 3.2.31 Polar Array
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\PolarArray\PolarArray.c

PolarArray\VC++7\Release\PolarArray.dll
Description
Section 3.2.32 Port List
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\PortList\Filename.c

Layout Path: \Features By Tool\L-Edit\UPIMacros\PortList\Filename.tdb
DLL Path: \Features By Tool\L-Edit\UPIMacros\PortList\release\Filename.dll
Description
Section 3.2.33 Properties
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\Properties\Filename.c

Layout Path: \Features By Tool\L-Edit\UPIMacros\Properties\Filename.tdb
DLL Path: \Features By Tool\L-Edit\UPIMacros\Properties\release\Filename.dll
Description
Section 3.2.34 Read from Text File and Instance T-Cell

ReadfromFileAndInstanceT-Cell\Filename.c
ReadfromFileAndInstanceT-Cell\Filename.tdb
ReadfromFileAndInstanceT-Cell\release\Filename.dll
Description
Section 3.2.35 Rename Cell
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\RenameCell\Filename.c

Layout Path: \Features By Tool\L-Edit\UPIMacros\RenameCell\Filename.tdb
DLL Path: \Features By Tool\L-Edit\UPIMacros\RenameCell\release\Filename.dll
Description
Section 3.2.36 Resistor
52
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\Resistor\Resistor.c

DLL Path: \Features By Tool\L-Edit\UPIMacros\Resistor\release\Resistor.dll
Description
Section 3.2.37 Run L-Edit in Command Mode and Load a Macro

RunL-EditCmdModeLoadMacro\Filename.c
RunL-EditCmdModeLoadMacro\Filename.tdb
RunL-EditCmdModeLoadMacro\release\Filename.dll
Description
Section 3.2.38 Selected Polygon Vertex Summary Report

SelectedPolygonVertexSummary\Filename.c
SelectedPolygonVertexSummary\Filename.tdb
SelectedPolygonVertexSummary\release\Filename.dll
Description
Section 3.2.39 Set Layer Rendering
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\SetRendering\Filename.c

Layout Path: \Features By Tool\L-Edit\UPIMacros\SetRendering\Filename.tdb
SetRendering\release\Filename.dll
Description
Section 3.2.40 Spiral
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\Spiral\Spiral.c

DLL Path: \Features By Tool\L-Edit\UPIMacros\Spiral\release\Spiral.dll
Description
Section 3.2.41 Spring
UPI Macro Path: \Features By Tool\L-Edit\UPIMacros\Spring\Spring.c

DLL Path: \Features By Tool\L-Edit\UPIMacros\Spring\release\Spring.dll
Description
53
Section 3.3 L-Edit T-Cells
Section 3.3.1 Buffer
T-Cell Layout \Features By Tool\L-Edit\TCells\Buffer.tdb

Path:
Cell: BUFFER Generator
Description
Section 3.3.2 Change T-Cell Name
T-Cell Layout \Features By Tool\L-Edit\TCells\ChangeTCellName.tdb

Path:
Cell: Rules
Description
Section 3.3.3 Concentric Tori
T-Cell Layout \Features By Tool\L-Edit\TCells\ConcentricTori.tdb

Path:
Cell: Concentric Tori
Description
Section 3.3.4 Decoder
T-Cell Layout \Features By Tool\L-Edit\TCells\Decoder.tdb

Path:
Cell: Decoder Generator
Description
Section 3.3.5 Ellipse
T-Cell Layout \Features By Tool\L-Edit\TCells\Ellipse.tdb

Path:
Cell: Ellipse Generator
Description
Section 3.3.6 Layout Text Generator
T-Cell Layout \Features By Tool\L-Edit\TCells\LayoutText.tdb

Path:
Cell: LayoutText Generator
Description
54
Section 3.3.7 Matched Dual Capacitor Array
T-Cell Layout \Features By Tool\L-Edit\TCells\MatchedDualCapacitorArray.tdb

Path:
Cell: MatchedDualCapacitorArray
Description
Section 3.3.8 MOSFET
T-Cell Layout \Features By Tool\L-Edit\TCells\Mosfet.tdb

Path:
Cell: NFET Generator
Description
Section 3.3.9 Rounded Rectangle
T-Cell Layout \Features By Tool\L-Edit\TCells\RoundedRectangle.tdb

Path:
Cell: Rounded Rectangle
Description
Section 3.3.10 Segmented Tori
T-Cell Layout \Features By Tool\L-Edit\TCells\SegmentedTori.tdb

Path:
Cell: Segmented2Torii, SegmentedTest, SegmentedTest2,
SegmentedTest3, SegmentedTest4, SegmentedTorus
Description
Section 3.3.11 Spiral
T-Cell Layout \Features By Tool\L-Edit\TCells\Spiral.tdb

Path:
Cell: Spiral Generator
Description
Section 3.3.12 T-Cell Builder
T-Cell Layout \Features By Tool\L-Edit\TCells\T-CellBuilder.tdb

Path:
Cell: Contacts, MOSFET, Res
Description
Section 3.3.13 T-Cell Calls Another T-Cell
55
T-Cell Layout \Features By Tool\L-Edit\TCells\T-CellCallsT-Cell.tdb

Path:
Cell: TCellCallTCell
Description
Section 3.3.14 Test Pattern Generator
T-Cell Layout \Features By Tool\L-Edit\TCells\TestPatternGen_v2.2.tdb

Path:
Cell: LineGrating, LineGratingVaryWidth, TestPatternGenerator
Description
Section 3.4 L-Edit Bindkeys
Section 3.4.1 Cadence
Bindkey Path: \ Features By Tool\L-Edit\BindKeys\Cadence\Cadence.ini
Description
Section 4 Additional Examples
Section 4.1 T-Spice External C Models
Section 4.1.1 Diode
C Model Path: \Features By Tool\T-Spice\External_C_Models\Diode
Diode.c Description
Diode.dll Description
Diode_DLL.sp Description
Diode_Interpreted.sp Description
Description
Section 4.1.2 MOS1
C Model Path: \Features By Tool\T-Spice\External_C_Models\MOS1\
mos1.c Description
mos1.dll Description
mos1_DLL.sp Description
mos1_Interpreted.sp Description
56
Description
Section 4.1.3 Resistor
C Model Path: \Features By Tool\T-Spice\External_C_Models\Resistor\
resistor.c Description
resistor.dll Description
Resistor_DLL.sp Description
Resistor_Interpreted.sp Description
Description
Section 4.1.4 Switch
C Model Path: \Features By Tool\T-Spice\External_C_Models\Switch\
switch.c Description
switch.dll Description
Switch_DLL.sp Description
Switch_Interpreted.sp Description
Description
Section 4.1.5 VCO
C Model Path: \Features By Tool\T-Spice\External_C_Models\VCO\
vco.c Description
vco.dll Description
VCO_DLL.sp Description
VCO_Interpreted.sp Description
Description
Section 4.2 L-Edit Layer Setup
Section 4.2.1 Black Background
Layout Path: \Features By Tool\L-Edit\LayerSetup\BlackBackground.tdb
Description
Section 4.2.2 Multiple Vias
Layout Path: \Features By Tool\L-Edit\LayerSetup\Multivias.tdb
Description
57
Section 4.2.3 Pastel Colors
Layout Path: \Features By Tool\L-Edit\LayerSetup\Pastel.tdb
Description
Section 4.2.4 Stripes
Layout Path: \Features By Tool\L-Edit\LayerSetup\Stripe.tdb
Description
58

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Tanner Tools v15

Tanner EDA Division

Section 1.28 SpiceOutput................................................................... 33

Section 2 Process ................................................................................... 40

Section 3 Automated Operations .......................................................... 44

Section 3.2.5 Change Layer ................................................................... 47

Section 3.3.14 Test Pattern Generator ..................................................... 56

Section 4 Additional Examples .............................................................. 56

Section 1.1 ADC8

Section 1.2 ADC Behavioral

Section 1.3 Bargraph

Section 1.4 BusesAndArrays

Section 1.4.1 Simple Buses

S-Edit Design: \Designs\BusesAndArrays\BusesAndArrays.tanner

Section 1.4.2 Splitting Buses

S-Edit Design: \Designs\BusesAndArrays\BusesAndArrays.tanner

Section 1.4.3 Port Bundles

S-Edit Design: \Designs\BusesAndArrays\BusesAndArrays.tanner

Section 1.4.4 1-Dimensional Arrays

S-Edit Design: \Designs\BusesAndArrays\BusesAndArrays.tanner

Section 1.4.5 2-Dimensional Arrays

S-Edit Design: \Designs\BusesAndArrays\BusesAndArrays.tanner

Section 1.5 CCD Imager

Section 1.6 Comparator One Bit

Section 1.7 CPU

Section 1.8 DecayMeasurement-Verilog

Section 1.9 DLatch

Section 1.10 GaAsAmp

Section 1.11 GlobalNets

Section 1.11.1 Simple Global Nets

S-Edit Design: \Designs\GlobalNets\GlobalNets.tanner

*************** Subcircuits *****************

.subckt Block2 In1 In2 Out1 Out2 Gnd Vdd

.subckt Block3 In1 In2 Out Gnd Vdd

.subckt CoreHV_Global A1 A2 A3 B1 B2 B3 Gnd Vdd

.subckt CoreLV_Global A1 A2 A3 B1 B2 B3 Gnd Vdd

Section 1.11.2 Separate Power Supplies

S-Edit Design: \Designs\GlobalNets\GlobalNets.tanner

*************** Subcircuits *****************

.subckt Block2 In1 In2 Out1 Out2 Gnd Vdd

.subckt Block3 In1 In2 Out Gnd Vdd

.subckt CoreHV_VddNetCap A1 A2 A3 B1 B2 B3 Gnd

.subckt CoreLV_VddNetCap A1 A2 A3 B1 B2 B3 Gnd

XCoreHV_VddNetCap_1 N_2 N_3 N_4 N_1 N_5 N_6 Gnd CoreHV_VddNetCap

The Vdd nets in CoreHV_VddNetCap and CoreLV_VddNetCap can be reconnected by

SPICE.OUTPUT = .global Vdd

Section 1.11.3 Renaming Separate Power Supplies

S-Edit Design: \Designs\GlobalNets\GlobalNets.tanner

In this example, the design in Top_VddIsolationRename has been modified by adding In

*************** Subcircuits *****************

.subckt Block2 In1 In2 Out1 Out2 Gnd Vdd

.subckt Block3 In1 In2 Out Gnd Vdd

.subckt CoreHV_VddRename A1 A2 A3 B1 B2 B3 Vdd Gnd

.subckt CoreLV_VddRename A1 A2 A3 B1 B2 B3 Vdd Gnd

XU1 A1 B1 Gnd Vdd Block1

XCoreHV_VddRename_1 N_2 N_3 N_4 N_1 N_5 N_6 Vdd_5v Gnd

Section 1.11.4 Renaming Separate Power Supplies Alternate Method

S-Edit Design: \Designs\GlobalNets\GlobalNets.tanner

*************** Subcircuits *****************

.subckt Block2 In1 In2 Out1 Out2 Gnd Vdd

.subckt Block3 In1 In2 Out Gnd Vdd

.subckt CoreHV_VddRenameGlobal A1 A2 A3 B1 B2 B3 Gnd Vdd

.subckt CoreLV_VddRenameGlobal A1 A2 A3 B1 B2 B3 Gnd Vdd

* Subcircuits ***

* Subcircuits ***

* Subcircuits ***

* Subcircuits ***

* Simulation Settings - General section *

* Subcircuits ***

* Simulation Settings - Analysis section *

* Simulation Settings - Additional SPICE commands *

* Simulation Settings - General section *

* Subcircuits ***

* Simulation Settings - Analysis section *

* Simulation Settings - Additional SPICE commands *

* Simulation Settings - General section *

* Subcircuits ***

* Simulation Settings - Analysis section *

* Simulation Settings - Additional SPICE commands *