---------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - Demand for high accurate detection and code has considered to be in programming level and it also
correction of data in memory brings motivation for this work. utilizes expansion of number qualities to distinguish and
In this modern era flow of data has increased to a higher right delicate errors. Comparatively recent study as given a
extent which is creating the corruption of required data. hint that these demonstrated methodology has less delay
Errors created by self-generator machines have less control comparing to other methodologies.
from the human beings and also its very difficult to monitor
such a huge data. If one could achieve high accurate data 1.1 PROBLEM DEFINITION
correction then a capacity of memory integration on chip can
be increased to fill the gap between the technology and A modern literature survey conveys that scope for high
semiconductor industry. The scope for DMC exists because of reliability and high accurate error correction and detection
its less area and more accurate error detection. Along with exists using Decimal Matrix Code [1], [2], [3] and [4]. The
that scope exists for ERT because it determines the area technique of making less number of the redundant bits and
without actually encoding and decoding the maintaining the reliability of the planned task is a
challenging work as taking into account of fast accessing
Key Words: DMC (decimal matrix code), ERT (error reuse over a large data.
technique), Multiple Bit Upsets (MCUs), Error Correction An attempt has been made to detect and correct more errors
Code (ECC), Punctured Difference Set (PDS). by completely understanding the fundamental concepts of
DMC. The main objective is to:
1. INTRODUCTION
Maintain higher reliability of memory.
The CMOS technology has scaled down to nano scale which is Fault-tolerant memory protected with DMC can be
making more transistors on a chip. As the number of simulated by using Xilinx.
electronic components increased and error rate in memories Comparing the area, delay, power with different
also increased due to ionizing effects from atmosphere. In papers.
memory single bit error is a major problem and Multiple Bit Finding power and area using cadence.
Upsets (MCUs) has turned into a bigger problem than the
single bit error.Was used for over the year to correct the 1.2 OVERVIEW OF PREVIOUS WORKS
single bit errors in the memories. To manage MCUs Reed
Solomon codes, Punctured Difference Set (PDS) and Bose- In memories errors occurs and those errors are detected
Chaudri-Hocquenghem codes have been used till now. In and corrected by various methods like Hamming codes and
these converted codes encoding and decoding are more self-checking techniques but these are not competence to the
complex and requires more power, more area and large present generation need of accuracy and high speed. It is
delay. The technique of interleaving has been used in MCUs easy to detect error but its difficult to correct them because
to improve memory cells in physical arrangement on the correcting error into again a fault error will create a false
boards. In Content Addressable Memory (CAM) interleaving positive error which cannot be identified and hence it
cannot be used because of tight coupling in between the becomes a big problem. The system created for identifying
cells. the faults should give the assurance that output codes given
To assure the MCUs, with respect to single-error are not the fault codes. The decision of the output data code
rectification and two fold locations the Built-In Current is an exceptionally discriminating errand. They chose code
Sensors are used. To effectively rectify the MCUs error the that has mistake identification capacities can less demanding
new method, Two Dimensional Matrix Code (MCs) is used, accomplish the fault secure property however includes an
which divides the long data into the various sub datas. In extensive number of outputs, along these lines, expanding
Hamming codes a bit to every line is secured and in equality equipment cost. Then again, picking a code of less error
code every segment is secured. After identifying these two recognition capacities would include fewer additional
errors in Hamming codes the vertical syndrome in MC have outputs at the same time, for accomplishing shortcoming
capacity of correcting errors up to 2bits. In a methodology sacredness, so then it may be required to change the circuit
that gives number of calculation with respect to Hamming structure (and along these lines additional expense). Now
2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 1884
International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 04 Issue: 08 | Aug -2017 www.irjet.net p-ISSN: 2395-0072
that its out in the open, the determination of the generated 2.3 Planned Diagram of Fault-Tolerant Memory
code may be examined by the specific circuit, to get the finest
result. As shown in the Figure 2, encoder which takes data bit d
as input. Output of the DMC encoder is Horizontal (H) and
2. DESIGNS AND IMPLEMENTATION Vertical bits (V). These values are stored in the memory
temporarily. The SRAM redundant bits are compared with
DMC is planned to guarantee dependability of Multi bit the information bits while read operation. Then decoder
upsets with lessened execution overheads. To recognize the gives the data bits which are corrected that mean while read
right mistakes in the circuit a 32-bit of encoding and operations the errors can be corrected. This is an advantage
decoding is proposed in my project work. Various system of DMC with high performance and high fault-tolerant
architecture and methodologies are discussed. capacity, ERT technique is used to optimize the area.
2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 1885
International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 04 Issue: 08 | Aug -2017 www.irjet.net p-ISSN: 2395-0072
Furthermore, correspondingly to other rest vertical disorder 2.6 Bound of Binary Error Detection
bits, here "signifies decimal whole number deduction. At
In this planned twofold fault discovery method, in spite of
the point when these values _H4H3H2H1H0 and S3 S0 are
the fact that it obliges low repetitive bits, its slip recognition
equivalent to the value zero. At the point when these values
capacity is constrained. The principle purpose behind this is
_H4H3H2H1H0, S3 S0 becomes nonzero, the incited
that its error discovery component is in view of binary. We
mistakes can be distinguished and situated for image 0,
show the points of confinement of this basic paired slip
afterward those errors can be removed easily.
recognition utilizing a straightforward illustration. Figure 7
shows Binary bits (B3 to B0) which are unique and data bits
(C0 and C1) are redundant bits.
2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 1886
International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 04 Issue: 08 | Aug -2017 www.irjet.net p-ISSN: 2395-0072
2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 1887
International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 04 Issue: 08 | Aug -2017 www.irjet.net p-ISSN: 2395-0072
1) Information bits in symbols with decimal integer. 2.8 Results and Discussion
0 and 2 are equal to 2m 1 and
2) Every bits in symbols 0 and 2 are troubled.
Accepting that these 2 components have been accomplished,
by encoding and disentangling procedures of DMC,
H4H3H2H1H0, and are registered, as takes after:
2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 1888
International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 04 Issue: 08 | Aug -2017 www.irjet.net p-ISSN: 2395-0072
2.9 Applications
3. CONCLUSIONS
ACKNOWLEDGEMENT
REFERENCES
[1]. Jing Guo, Liyi Xiao, Zhigang Mao and Qiang Zhao,
Enhanced Memory Reliability Against Multiple Cell
Upsets Using Decimal Matrix Code, IEEE
TRANSACTIONS ON VERY LARGE SCALE
INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 1, pp.
127-135, JANUARY 2014
Fig.-17 Vertex5 Hardware output [2]. Riaz Naseer and Jeff Draper, Parallel Double Error
Correcting Code Design to Mitigate Multi-Bit Upsets
Table -2: Error Correction capability in SRAMs, 978-1-4244-2361-3/08/$25.00 2008
IEEE. Abbreviation
Types of no. of no. of error
applied Information redundant correction [3]. T.Maheswari and Mr.P.Sukumar, Error Detection
ECC bits bits capability and Correction in SRAM Cell Using Decimal Matrix
proposed 32 36 5 Code, IOSR Journal of VLSI and Signal Processing
DMC (IOSR-JVSP) Volume 5, Issue 1, Ver.II (Jan Feb.
matrix 32 28 2 2015), PP 09-14
code
hamming 32 7 1 [4]. Juan Antonio Maestro, Pedro Reviriego, Sanghyeon
code Baeg, Shijie Wen, Richard Wong, Soft error tolerant
Content Addressable Memories (CAMs) using error
2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 1889
International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 04 Issue: 08 | Aug -2017 www.irjet.net p-ISSN: 2395-0072
2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 1890