International Journal of Electronics

ISSN: 0020-7217 (Print) 1362-3060 (Online) Journal homepage: http://www.tandfonline.com/loi/tetn20

Analysis, design and experimentation of an

interleaved active-clamping buck-type converter

Bor-Ren Lin , Po-Li Chen & Kun-Liang Shih

To cite this article: Bor-Ren Lin , Po-Li Chen & Kun-Liang Shih (2010) Analysis, design and
experimentation of an interleaved active-clamping buck-type converter, International Journal
of Electronics, 97:6, 677-693, DOI: 10.1080/00207211003697814

To link to this article: http://dx.doi.org/10.1080/00207211003697814

Published online: 01 Jun 2010.

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 International Journal of Electronics
Vol. 97, No. 6, June 2010, 677693

Analysis, design and experimentation of an interleaved active-clamping

buck-type converter
Bor-Ren Lin*, Po-Li Chen and Kun-Liang Shih

Department of Electrical Engineering, National Yunlin University of Science and Technology,

Yunlin 640, Taiwan
(Received 3 April 2009; nal version received 27 January 2010)

An interleaved pulse-width modulation (PWM) zero voltage switching (ZVS)

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converter is presented in this article. Two converter modules with an interleaved

PWM scheme are used in the proposed circuit to achieve load current sharing and
to reduce the ripple currents on the input and output capacitors such that the size
of the output choke and capacitor is reduced. For each module, two buck-type
dcdc converters with only two switches are used to reduce the current rating of
transformer winding and share the load current. Two buck-type converters in
each module use the same switching devices to regulate the output voltage. The
ZVS turn-on of the switches is achieved by utilising the transformer leakage
inductance and output capacitance of switches. Thus, the switching losses of
the proposed converter are reduced. Experiments based on a 660 W prototype are
provided to verify the theoretical analysis and the eectiveness of the proposed
converter.
Keywords: SMPS; buck-type converter; converters; PWM; power electronics

1. Introduction
Forward converters have been used widely in many power supply systems because of
their well-regarded features, such as smooth output current on the output side and
simple circuit conguration. However, transformer utilisation and the magnetic ux
reset circuit are the main drawbacks of forward converters. Soft switching converters
with high eciency and high power density have been presented for the distribution
of power systems in telecommunication applications. Phase-shift pulse-width
modulation (PWM) (Yungtack, Jovanovic and Chang 2003; Ruan and Wang
2004) has been presented for medium- and high-power applications with zero voltage
switching (ZVS) turn-on. However, phase-shift PWM converters are expensive and
the ZVS turn-on of switches at light load is not easy to implement. Asymmetrical
PWM half-bridge converters (Chen and Chen 2002; Choi and Lim 2005) have been
proposed to achieve ZVS turn-on during the commutation stage of a pair of
complementary switches. However, the voltage and current stresses of power
switches in the transformer primary side and rectier diodes at the transformer
secondary side are related to the duty cycle. Active-clamping techniques (Lee, Choi
and Moon 2007; Lin and Chen 2008; Lin, Huang and Chen 2009; Lin and Shen

*Corresponding author. Email: linbr@yuntech.edu.tw

ISSN 0020-7217 print/ISSN 1362-3060 online

2010 Taylor & Francis
DOI: 10.1080/00207211003697814
http://www.informaworld.com
 678 B.-R. Lin et al.

2009) were proposed to achieve magnetic ux reset, absorb the surge energy stored in
the leakage and magnetising inductances, and limit the voltage stresses on power
switches. Thus, the voltage stresses on switches are reduced compared with the
voltage stresses in the conventional forward converter with an RCD (resistor
capacitordiode) snubber. For medium- or high-power applications, the parallel
techniques with two or more converter modules can distribute the current stresses
and power losses in each module. Parallel forward converters with ZVS techniques
have been presented by Torrico-Bascop and Barbi (2001), Veerachary, Senjyu and
Uezato (2001), Wong, Lee, Cheng and Chow (2004), Li and He (2007) and Lin and
Tseng (2007) for high output current applications. However, the control schemes of
these converters are complex. The interleaved PWM technique is a parallel
technique with a phase shift over a switching period. The interleaved PWM
technique can not only reduce the current stresses in each converter module but
can also decrease the ripple currents on the input and output capacitors. Thus, the
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size of the magnetising components, power losses and thermal stresses on power
converters can be reduced.
In this study, an interleaved soft switching converter with ZVS turn-on is
presented. The proposed converter includes two modules to achieve load current
sharing and ripple current reduction using interleaved PWM scheme. Each module
combines two buck-type converters. These two buck-type converters are connected
in parallel at the input and output sides to further share load current and reduce the
ripple current on the output capacitor. The buck-type converters in each module
share the same power switches such that the proposed converter has a lower switch-
count compared to the conventional interleaved forward converter with four
switches. One active-clamping circuit is used in each module to achieve magnetic ux
reset and limit the voltage spike on power switches. During the commutation stage of
two switches, the resonant inductance and the output capacitance of the switches are
resonant such that the power switches can be turned on at ZVS. Experimental results
based on a 660 W (12 V/55 A) prototype circuit are presented to verify the circuits
performance.

2. Circuit conguration
Figure 1(a) shows the circuit conguration of the proposed active-clamping
converter. Two buck-type converters are connected in parallel in this circuit. The
converter 1 includes the circuit components of Vin, Lr1, T1, S1, Cr, D1 and Lo. The
components of converter 2 include C2, Lr2, T2, S1, Cr, D2 and Lo. Vin and Vo
are input and output voltages, respectively. Co is the output capacitor. C1 and S2
are clamp capacitor and auxiliary switch, respectively. Cr is an equivalent
capacitance including the output capacitances of S1 and S2 and parasitic
capacitance of the transformer. Lr1, Lr2 and Cr are resonant during the transition
interval such that power switches S1 and S2 are turned on at ZVS. Based on the
series connection of the two transformers, the power ow can be transferred from
the primary side to the secondary side by asymmetrical PWM scheme. The gate
signals of S1 and S2 are complementary to each other with a short delay time.
Figure 1(b) shows the proposed interleaved ZVS converter. Two converter modules
are phase-shifted at 1808 to reduce the current ripples on the input and output
capacitors, reduce the size of output chokes and reduce the current stresses of
power semiconductors.
 International Journal of Electronics 679
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Figure 1. (a) Circuit conguration of the proposed ZVS converter; (b) proposed interleaved
ZVS converter.

3. Principles of operation
Based on the on/o states of S1S4 and D1D4, the proposed interleaved ZVS
converter has eight operating modes in each half of the switching cycle. The key
waveforms of the proposed converter are shown in Figure 2. The system analysis is
based on the following assumptions.

. The turns ratio of transformers T1T4 is equal, n Np/Ns.

. C1, C2, C3 and C4  Cr1 and Cr2.
. Lr1 Lr2 Lr3 Lr4:Lr is less than the magnetising inductance Lm of
transformers T1T4.
. The ripple voltages of C1C4 are much small in one switching cycle.

Figure 3 shows the equivalent circuits of each operating mode in the rst half of
the switching cycle. The typical waveforms for each mode will be discussed in the
following sections. Prior to t0, the rectier diodes D1 and D2 were both conducting to
commutate the output inductor current iLo1 in converter module 1.
 680 B.-R. Lin et al.
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Figure 2. Key waveforms of the proposed interleaved ZVS converter.

3.1. Mode 1 [t0  t 5 t1]

At time t0, diode D2 is turned o. For converter module 1, the input power is
transferred to output load through Vin, Lr1, T1, D1, Lo1, Co and S1. The primary
voltage of T1 approximates the input voltage Vin. The magnetising inductor current
iLm1 increases linearly. The secondary winding voltage of T1 is positive. The voltage
across output inductor Lo1 approximates Vin/n7Vo 4 0. Thus, the output inductor
current iLo1 and resonant inductor current iLr1 are given as:
Vin =n  Vo
iLo1 t  iLo1 t0 t  t0
Lo1
Vin iLo1 t
iLr1 t  iLr1 t0 t  t0 1
Lm1 n
 International Journal of Electronics 681
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Figure 3. Equivalent circuits of the proposed interleaved ZVS converter in the rst half of
switching cycle (a) mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5 (f) mode 6 (g) mode 7
(h) mode 8.
 682 B.-R. Lin et al.

where n Np/Ns is the turns ratio of transformers T1T4. The primary voltage of T2
approximates vC2 in this mode. The inductor current iLr2 increases linearly.
vC2
iLr2 t iLm2  iLr2 t0 t  t0 2
Lm2
In the same manner, the power stored in magnetising inductances Lm4 and Lr4 is
transferred to the output load through C3, T4, Lr4, D4, Lo2, Co and S4 in converter
module 2. The inductor currents in converter 2 are given as:
VC3 =n  Vo
iLo2 t  iLo2 t0 t  t0
Lo2
Vin  vC3  vC4
iLr3 t  iLr3 t0 t  t0
Lm3
VC3 iLo2 t
iLr4 t  iLr4 t0  t  t0  3
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Lm4 n

The time interval in this mode approximates dT, where d and T are the duty cycle
and the switching period of switch S1, respectively. This interval ends at time t1 when
switch S1 is turned o.

3.2. Mode 2 [t1  t 5 t2]

At time t1, switch S1 is turned o. Capacitor Cr1 is charged by the positive switch
current iS1(t1). The components of Cr1, Lr1, Lr2 and the magnetising inductances of
T1 and T2 are resonant in this mode. The capacitor voltage vCr1 and the inductor
currents iLr1 and iLr2 are given as:

vCr1 t Vin 1  cos o1 t  t1 iLr1 t1 ; iLr2 t1 Z1 sin o1 t  t1 ;

Vin iLr1 t1 iLr2 t1
iLr1 t sin o1 t  t1 iLr1 t1  1  cos o1 t  t1 ;
Z1 2
Vin iLr1 t1 iLr2 t1 4
iLr2 t sin o1 t  t1 iLr2 t1  1  cos o1 t  t1
Z1 2

wherepCr1 Cr2 Cr, Lr1 Lr2 Lp

Lr4 Lr, Lm1 Lm2 Lm3 Lm4 Lm,
r3
o1 2=Cr Lm Lr  and Z1 2Lm Lr =Cr . At time t2, capacitor Cr1
is charged to Vin (vC2). From Equation (4), the time interval in this mode is
expressed as:
 
1 1 Vin
Dt12 t2  t1 tan 5
o1 iLr1 t1 iLr2 t1 Z1

3.3. Mode 3 [t2  t 5 t3]

After time t2, the capacitor voltage vCr1 Vin vC2. At this instant, the primary
voltages of transformers T1 and T2 equal zero. Thus, the secondary winding voltages
of T1 and T2 also equal zero voltage. Then both diodes D1 and D2 conduct to
commutate the inductor current iLo1. The diode current iD1 decreases and the
diode current iD2 increases. The output inductor voltage vLo1 7Vo and
 International Journal of Electronics 683

the output inductor current iLo1 decreases in this mode. In this mode, Lr1, Lr2 and Cr1
are resonant. The inductor currents, iLr1 and iLr2, and capacitor voltage vCr1 are
given as:

vCr1 t vC2 iLr1 t2 iLr2 t2 Z2 sin o2 t  t2 ;

iLr1 t2 iLr2 t2
iLr1 t iLr1 t2  1  cos o2 t  t2 ;
2
iLr1 t2 iLr2 t2 6
iLr2 t iLr2 t2  1  cos o2 t  t2
2
p p
where o2 2=Cr Lr and Z2 Lr =2Cr . Capacitor Cr1 is continuously
charged from vC2 to vC1 vC2. Since the primary and secondary winding voltages
of T1 and T2 are all in zero voltage, the inductor voltages vLr1 Vin7vCr1 and
vLr2 vC27vCr1. Thus, the inductor currents iLr1 and iLr2 decrease. This mode
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ends at time t3 when vCr1(t3) vC1 vC2. Then the anti-parallel diode of
auxiliary switch S2 starts conducting. From Equation (6), the time interval in this
mode is expressed as:
 
1 1 vC1
Dt23 t3  t2  sin 7
o2 iLr1 t2 iLr2 t2 Z2

3.4. Mode 4 [t3  t 5 t4]

At time t3, vCr1(t3) vC1 vC2 and the anti-parallel diode of auxiliary switch S2
starts conducting. Thus, S2 can be turned on at this interval to achieve ZVS. On the
secondary side, the diodes D1 and D2 are still conducting to commutate the inductor
current iLo1. The inductor voltages vLr1Vin7vC17vC2 and vLr27vC1. Thus, the
inductor currents iLr1 and iLr2 decrease. This mode ends at time t4 when the diode
current iD1 decreases to zero value.

3.5. Mode 5 [t4  t 5 t5]

This mode starts at time t4 when the diode current iD1 decreases to zero value. The
voltage across the inductor Lr1 and the magnetising inductor of T1 approximates
Vin7vC17vC2 5 0. Thus, the inductor current iLr1 decreases in this mode. The
voltage across inductor Lr2 and the magnetising inductor of T2 approximates 7vC1.
The inductor current iLr2 also decreases and the output inductor current iLo1
increases with the current slope of (vC1/n7Vo)/Lo1 in this mode. Power stored in the
magnetising inductor Lm2 and the resonant inductor Lr2 is delivered to output load
through T2, S2, D2, Lo1 and Co in converter module 1.

3.6. Mode 6 [t5  t 5 t6]

This mode starts at time t5 when auxiliary switch S4 in converter module 2 is turned
o. Since iLr3(t5) iLr4(t5) is negative, capacitor Cr2 is discharged from vC3 vC4.
The components of Cr2, Lr3, Lr4 and the magnetising inductances of T3 and T4 are
resonant. The capacitor voltage vCr2 and the inductor currents iLr3 and iLr4 are
expressed as:
 684 B.-R. Lin et al.

vCr2 t vC4 vC3 cos o1 t  t5 iLr3 t5 iLr4 t5 Z1 sin o1 t  t5 ;

vC3 iLr3 t5 iLr4 t5
iLr3 t  sin o1 t  t5 iLr3 t5  1  cos o1 t  t5 ;
Z1 2
vC3 iLr3 t5 iLr4 t5
iLr4 t  sin o1 t  t5 iLr4 t5  1  cos o1 t  t5 8
Z1 2
At time t6, the capacitor voltage vCr2(t6) vC4Vin. The time interval in this
mode can be expressed as follows.
 
1 1 vC3
Dt56 t6  t5 tan 9
o1 iLr3 t5 iLr4 t5 Z1

3.7. Mode 7 [t6  t 5 t7]

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At time t6, the capacitor voltage vCr2(t6) vC4Vin. At this instance, the primary
and secondary voltages of transformers T2 and T4 in converter module 2 are all in
zero values. Thus, diodes D3 and D4 are conducting after time t6. The output
inductor voltage vLo2 7Vo and the output inductor current iLo2 decreases. The
diode currents iD3 increases and iD4 decreases. The circuit components Lr3, Lr4 and
Cr2 are resonant during this interval. The inductor currents iLr3 and iLr4 and
capacitor voltage vCr2 are given in Equation (10).

vCr2 t vC4 iLr3 t6 iLr4 t6 Z2 sin o2 t  t6 ;

iLr3 t6 iLr4 t6
iLr3 t iLr3 t6  1  cos o2 t  t6 ;
2
iLr3 t6 iLr4 t6
iLr4 t iLr4 t6  1  cos o2 t  t6 10
2
To ensure the switch S3 turn-on at ZVS, capacitor voltage vCr2 should be
decreased to zero value before the end of this mode. Thus, the following equation
can be obtained from Equation (10).

Lr  2Cr v2C4 =iLr3 t6 iLr4 t6 2  2Cr V2in =iLr3 t6 iLr4 t6 2 11

The other condition of ZVS turn-on of S3 is that the energy stored in resonant
inductors Lr3 and Lr4 should be greater than the energy stored in capacitor Cr2.
Thus, the ZVS condition of S3 can be expressed as in Equation (12).

Lr  Cr V2in =i2Lr3 t6 i2Lr4 t6  12

From Equations (11) and (12), it is clear that 2Cr V2in =iLr3 t6 iLr4 t6 2 >
Cr V2in =i2Lr3 t6 i2Lr4 t6 . Thus, Equation (11) is selected to achieve ZVS turn-on of
S3. This mode ends at time t7 when the capacitor voltage vCr2 0 and the anti-
parallel diode of S3 is conducting. The time interval in this mode is given as:
 
1 Vin
Dt67 t7  t6 sin 1 13
o2 iLr3 t6 iLr4 t6 Z2
 International Journal of Electronics 685

3.8. Mode 8 [t7  t 5 T/2 t0]

After time t7, the capacitor voltage vCr2 0 and the anti-parallel diode of S3 is
conducting. Thus, switch S3 can be turned on at ZVS before iS3 is positive. In this
mode, diodes D3 and D4 are still in the commutation interval. The inductor voltages
vLr3 Vin and vLr4 vC2. Thus, the inductor currents iLr3 and iLr4 increase and the
output inductor current iLo2 decreases. This mode ends at time T/2 t0 when iD4
decreases to zero value. Then, the rst half of circuit operation is completed. The
second half of circuit operation in converter module 2 is symmetrical to the rst half
of the circuit operation in converter module 1.

4. Circuit characteristics
The transition intervals in modes 2 and 3 for converter module 1 and modes 6 and 7
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in converter module 2 are much shorter. Thus, those modes can be neglected when
deriving the voltage conversion ratio of the proposed converter. Based on the
voltage-second balance on the primary side of T1 and T2 in converter 1, the following
equations can be obtained.

dVin 1  dVin  VC1  VC2 0;

dVC2  1  dVC1 0 14
where VC1 and VC2 are the average voltages on capacitors C1 and C2, respectively in
a switching cycle. From Equation (14), the average capacitor voltages VC1 and VC2
can be rewritten as:

VC1 dVin =1  d; VC2 Vin 15

In the same manner, the average capacitor voltages VC3 and VC4 in converter 2
can be obtained as:

VC3 dVin =1  d; VC4 Vin 16

From Equations (15) and (16), we can observe that the capacitor voltages VC1
and VC3 depend on the duty cycle d and the input voltage Vin. Based on the voltage-
second balance on the output inductors Lo1 and Lo2, the following equation can be
obtained.
2d  2d2  dloss Vin 2d
Vo  VF  Vin  VF 17
n1  d n
where dloss is the duty cycle loss in modes 4 and 8 and VF is the voltage drop on
diodes D1D4. Thus, the dc voltage conversion ratio M of the proposed converter is
expressed as:

M Vo =Vin  2d=n  VF =Vin 18

The primary winding turn Np of T1T4 can be expressed as:

Np Vin d=Ae DBf 19

 686 B.-R. Lin et al.

where DB is the working ux density, Ae is the eective cross-sectional area of the

selected transformer core and f is the switching frequency. Based on Equations (18)
and (19), the secondary winding turn Ns of T1T4 is given as:

Np Vo VF
Ns 20
2dVin

Based on the circuit conguration, the voltage stresses of S1 and S2 are equal to
vC1 vC2 and the voltage stresses of S3 and S4 are clamped at vC3 vC4. Since
vC3 vC4 Vin and vC1 vC3 dVin/(17d) in steady state, we can obtain the
drain voltage of switches S1S4 in Equation (21).

d Vin
vS1;stress vS2;stress vS3;stress vS4;stress  Vin Vin 21
1d 1d
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The maximum currents of S1 and S2 approximate the maximum value of

(iLr1 iLr2). In mode 1, the maximum switch currents can be expressed as:

iS1;max iS2;max  iLr1 t1 iLr2 t2  ILo1 =n ILm1 ILm2

22
DILo1 =2n DILm1 =2 DILm2 =2
where ILm1 and ILm2 are the average magnetising currents of T1 and T2,
respectively. When auxiliary switch S2 is in the on-state, the average capacitor
current iC1 is zero.
ILm1 ILm2  ILo1 =n 0 23

Based on the current-second on the capacitor C2, we can derive the following
equation.
ILm2 d  ILm1 1  d 0 24

From Equations (23) and (24), we can derive the average magnetising currents.

dILo1 dIo 1  dILo1 1  dIo

ILm1  ; ILm2  ; 25
n 2n n 2n

From Equations (22) and (25), the maximum switch currents of S1 and S2 can be
expressed as:

iS1;max iS2;max  Io =n DILo1 =2n DILm1 =2 DILm2 =2 26

In the same manner, we can obtain the average magnetising currents and
maximum switch currents in converter module 2.
dIo 1  dIo
ILm3  ; ILm4  ;
2n 2n 27
iS3;max iS4;max  Io =n DILo2 =2n DILm3 =2 DILm4 =2
 International Journal of Electronics 687

If the current ripples on the output inductors are selected as DiLo1 DiLo2 rIo,
then the output inductances can be given as:

Vin =n  Vo d 1  2dVo
Lo1 Lo2   28
rIo fs 2rIo fs

The maximum currents of the diodes D1D4 are approximately expressed as:

iD1;max iD2;max iD3;max iD4;max 0:5 rIo 29

The average currents of the diodes D1D4 are expressed as:

iD1;av iD3;av  dIo =2; iD2;av iD4;av  1  dIo =2; 30

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The root-mean-square (rms) currents of D1D4 are expressed as:

p p
iD1;rms iD3;rms  dIo =2; iD2;rms iD3;rms  1  dIo =2; 31

The maximum voltage of the diodes D1D4 are expressed as:

2dVin 2Vin
vD1;max vD3;max  ; vD2;max vD4;max ; 32
n1  d n

Basically the ZVS of auxiliary switches S3 and S4 are naturally achieved by the
energy stored in the leakage and magnetising inductances of T1T4. To ensure the
ZVS operation of switch S3, Equation (11) is used to select resonant inductor to
achieve ZVS turn-on of S3. In the same manner, the ZVS condition of S1 is given as:

Lr  2Cr V2in =iLr1 t6 T=2 iLr2 t6 T=22 33

The capacitances of C1C4 can be expressed as in Equation (34) based on the

voltsecond feature of the magnetising inductance and the ripple voltages of clamp
capacitors.

1  d2 d2
C1 C3  ; C2 C4  ; 34
2a1 Lm f2 2a2 Lm f2

where a1 DvC1/VC1 DvC3/VC3 and a2 DvC2/VC2 DvC4/VC4.

5. Realisation and experimentation

An example of the proposed converter is designed in this section and realised in the
next section. The circuit parameters of the prototype circuit are given as: Vin:180
220V, Vo 12 V, Po 660 W, f 100 kHz and dmax 0.45. The EER40C core
with Bmax 2000 G and Ae 1.49 cm2 was used to design the power transformer.
Thus, the minimum primary turns of T1T4 are given as:

Np;min Vin;min dmax  108 =Ae Bmax f 180  0:45  108 =

35
1:49  2000  105 27:18T
 688 B.-R. Lin et al.

In the proposed converter the selected primary turns Np 37T. The secondary
winding turns of T1T4 are can be given as:

Np Vo VF 37  12 1
Ns 2:97T 36
2dVin 2  0:45  180

The secondary winding turns in the adopted prototype are Ns 3T. Finally, the
adopted transformers T1T4 have the following parameters: Np 37T, Ns 3T and
Lm 260 mH. The designed ripple currents on Lo1 and Lo2 are 5% of maximum
load current Io,max. Thus, we can obtain the inductance of Lo1 and Lo2 from
Equation (28).
1  2dmin Vo 1  2  0:368  12
Lo1 Lo2 5:76 mH 37
2rIo fs 2  0:05  55  105
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The power core CM343125 with AL 79 nH/N2 is used to design the output
inductances Lo1 and Lo2. Thus, the turns of output inductors are given as:
r r
Lo1 5:76  106
N 8:53T 38
AL 79  109

The used winding turns of Lo1 and Lo2 are N 9 and the output inductances
Lo1 Lo2 AL 6 N2 79 6 109 6 92 6.4 mH. The average currents of the
diodes D1D4 are expressed as:

iD1;av iD3;av  dmax Io =2 0:45  55=2 12:375A;

39
iD2;av iD4;av  1  dmin Io =2 1  0:368  55=2 17:38A

The maximum voltage of the diodes D1D4 are expressed as:

2dVin 2  0:45  180

vD1;max vD3;max  23:88 V;
n1  d 371  0:45=3
40
2Vin 2  220
vD2;max vD4;max 35:68 V
n 37=3

STPS30H100CW Schottky rectier diodes with 30 A current stress and 100 V

voltage stress were used as the rectier diodes D1D4. Neglecting the ripple current
on output inductance and magnetising inductance, the rms currents of S1 and S2 can
be expressed as:
Io p 55 p
iS1;rms iS3;rms  d 0:45 3 A 41
n 37=3

The rms currents of S3 and S4 can be expressed as:

DILm1 DILm2 p
iS2;rms iS4;rms 1  d=3
2
42
Vin;max dmin p
 1  dmin =3 1:43 A
Lm fsw
 International Journal of Electronics 689
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Figure 4. Photograph of the experimental prototype.

Figure 5. Measured PWM signals of switches S1S4 at (a) light load (Io 3 A); (b) full load
(Io 55 A).

Figure 6. Measured gate and drain voltages of power switches at light load (Io 3 A) (a) S1
and S2 (b) S3 and S4.
 690 B.-R. Lin et al.

The voltage stresses of S1S4 are equal to Vin/(17d)327 V. The MOSFETs

FS14SM-16 with 800 V voltage stress and 14 A current stress were used as the power
switches S1S4. The Coss of FS14SM-16 is about 290 pF. Therefore, the capacitances
of Cr1 and Cr2 are about 2 6 4 6 290/3 773 pF. The selected resonant inductors
Lr1Lr2 are 17 mH to achieve ZVS condition in Equation (33). The selected
capacitance of C1C4 is 0.1 mF. The capacitance of output capacitor Co is 2200 mF.
Figure 4 shows the photograph of the experimental prototype.
Figure 5 shows the measured PWM signals of switches S1S4 at light load (3 A)
and full load (55 A). It is clear that PWM signals of S1 and S3 are phase-shifted at
1808 and PWM signals of S1 and S3 in converter 1 and S2 and S4 in converter 2 are
complementary to each other with a short time delay. The measured gate voltage and
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Figure 7. Measured gate and drain voltages of power switches at full load (Io 55 A) (a) S1
and S2 (b) S3 and S4.

Figure 8. Measured current waveforms of the proposed converter in converter module 1 at

full load (Io 55 A).
 International Journal of Electronics 691

drain voltage of power switches at light load condition are given in Figure 6. Before
the power switches are turned on, the drain voltages vS1,dsvS4,ds have been decreased
to zero. Thus, both switches S1 and S2 are turned on at ZVS. In the same manner,
the measured gate voltage and drain voltage at full load condition are given in
Figure 7. Switches S1S4 are also turned on at ZVS. Figure 8 shows the measured
currents of the proposed converter in converter module 1 at full load (Io 55 A).
When S1 is in the on-state, the inductor currents iLr1 and iLr2 increase. The switch
currents iS1 iLr1 iLr2 and iS2 0. The diode D1 is conducting and iD1 iLo1.
When S1 is o and S2 is on, the inductor currents iLr1 and iLr2 decrease. The switch
currents iS2 7iLr17iLr2 and iS1 0. The diode D2 is conducting and iD2 iLo1.
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Figure 9. Measured current waveforms of the proposed converter in converter module 2 at

full load (Io 55 A).

Figure 10. Measured waveforms of gate voltage vS1,gs and output inductor currents iLo1, iLo2
and iLo1 iLo2 at full load.
 692 B.-R. Lin et al.
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Figure 11. Measured eciencies of the proposed converter and the conventional interleaved
active-clamp forward converter.

In the same manner, the measured current waveforms of the proposed converter in
converter module 2 at full load are illustrated in Figure 9. When S3 is on, the
inductor currents iLr3 and iLr4 increase. The switch currents iS3 iLr3 iLr4 and
iS4 0. The diode D3 is conducting and iD3 iLo2. When S3 is o and S4 is on, the
inductor currents iLr3 and iLr4 decrease. The switch currents iS3 7iLr37iLr4 and
iS4 0. The diode D4 is conducting and iD4 iLo2. Figure 10 shows the measured
gate voltage vS1,gs and output inductor currents iLo1, iLo2 and iLo1 iLo2 at full load
condition. Figure 11 shows the measured eciency of the proposed converter and
the conventional interleaved active-clamp forward converter with dierent output
power. The proposed converter has a better circuit eciency compared with the
interleaved active-clamp forward converter. The measured maximum eciency of
the proposed interleaved ZVS converter is 90.8%.

6. Conclusion
This article presents an interleaved converter with ZVS turn-on and load current
sharing. Active clamp circuit is used to implement the transformer ux reset and
limit the voltage stresses on the switches. The ZVS turn-on of switches is realised at
the commutation stage of main and auxiliary switches. Two converter modules with
interleaved PWM scheme are used to achieve load current sharing and reduce the
ripple currents on the input and output capacitors such that the size of the output
chokes and capacitor is reduced. The experiments based on a 660 W prototype are
provided to verify the theoretical analysis and the eectiveness of the proposed
converter.

Acknowledgement
This project is supported by the National Science Council of Taiwan under Grant NSC 97-
2221-E-224-064-MY2.

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