UNIT 3

COMBINATIONAL DESIGN
TOPICS
Dataflow Style Behavioral Style

Logical and relational
Process statement

operators
Case statement

Signal assignments
If statement

Don’t care conditions
Loop statement

Lookup tables
Variables
DATAFLOW STYLE

Logical and relational operators

Signal assignments

Encoders and decoders

Lookup tables
OPERATORS
VHDL operators listed from higher to lower
precedence
Miscellaneous ** abs not
Multiplying * / mod rem
Sign + -
Adding + - &
Shift sll srl sla sra rol ror
Relational = /= < <= > >=
Logical and or nand nor xor xnor
LOGICAL OPERATORS
A B not A A and B A nand B A or B A nor B A xor B A xnor B
0 0 1 0 1 0 1 0 1
0 1 1 0 1 1 0 1 0
1 0 0 0 1 1 0 1 0
1 1 0 1 0 1 0 0 1

All operators have the same level of precedence

except for not

Associative operators: and, or, xor, xnor

A and B and C -- valid

A nand B nand C -- invalid
SIGNAL ASSIGNMENTS

A signal assignment placed in the statement part
of an architecture is a concurrent statement.

2 forms of concurrent signal assignment:

Selected signal assignment

Conditional signal assignment

Using Boolean expression (3rd form)

Synthesizable signal assignment form:
target <= value_expression;
EXAMPLE: 4-TO-1 MULTIPLEXER
Logic Symbol Entity Declaration

entity mux4to1 is
Port ( I : in STD_LOGIC_VECTOR
(3 downto 0);
S : in STD_LOGIC_VECTOR
(1 downto 0);
nE : in STD_LOGIC;
Y : out STD_LOGIC);
end mux4to1;
EXAMPLE: 4-TO-1 MULTIPLEXER

Concurrent signal assignment using Boolean
expression:

architecture Dataflow of mux4to1 is

begin
Y <= (not nE) and (
(not S(1) and not S(0) and I(0))
or (not S(1) and S(0) and I(1))
or (S(1) and not S(0) and I(2))
or (S(1) and S(0) and I(3)));
end Dataflow;
SELECTED SIGNAL ASSIGNMENT

Also called a with-select-when statement

It allows one of several possible values to be
assigned to a signal based on a select
expression.

Form:

with expression select

target <= value_expression1 when choices1,
value_expression2 when choices2,
…
value_expressionn when others;
EXAMPLE: 4-TO-1 MULTIPLEXER

Selected signal assignment:

architecture Dataflow of mux4to1 is

begin
with (nE & S) select
Y <= I(0) when "000",
I(1) when "001",
I(2) when "010",
I(3) when "011",
'Z' when others;
end Dataflow;
RELATIONAL OPERATORS
Operator Operation Left Right Result
Operand Operand
= Equality Any except Same as Boolean
file left
/= Inequality -do- -do- -do-
< Less than Scalar or -do- -do-
composite
discrete type
<= Less than or -do- -do- -do-
equal
> Greater than -do- -do- -do-
>= Greater than -do- -do- -do-
or equal
CONDITIONAL SIGNAL ASSIGNMENT

Also called when-else statement

It allows a signal to be assigned a value based on
a set of conditions (expressions involving
relational operators).

Form:

target <= value_expression1 when condition1 else

value_expression2 when condition2 else
…
value_expressionn-1 when condition-1 else
value_expressionn;
EXAMPLE: 4-TO-1 MULTIPLEXER

Conditional signal assignment:

architecture Dataflow of mux4to1 is

signal tmp : std_logic_vector(2 downto 0);
begin
tmp <= nE & S;
Y <= I(0) when tmp = "000" else
I(1) when tmp = "001" else
I(2) when tmp = "010" else
I(3) when tmp = "011" else
'Z';
end Dataflow;
UNDESIRED IMPLIED LATCH
EXAMPLE: MAGNITUDE COMPARATOR
entity Comparator is
Port ( A, B : in STD_LOGIC_VECTOR (7 downto
0);
G, E, L : out STD_LOGIC);
end Comparator;

architecture Behavioral of Comparator is

begin
G <= '1' when A > B else '0';
E <= '1' when A = B else '0';
L <= '1' when A < B else '0';
end Behavioral;
EXAMPLE: PRIORITY ENCODER

I3 I2 I1 I0 A1 A0
X X X 1 0 0
X X 1 0 0 1
X 1 0 0 1 0
1 0 0 0 1 1
EXAMPLE: PRIORITY ENCODER
entity PEncoder is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
A : out STD_LOGIC_VECTOR (1 downto 0));
end PEncoder;

architecture Conditional of PEncoder is

begin
A <= "00" when I(0) = '1' else
"01" when I(1) = '1' else
"10" when I(2) = '1' else
"11" when I(3) = '1' else
"ZZ";
end Conditional;
DON’T CARE INPUTS AND OUTPUTS

Traditional logic design

Could be 1 or 0

Represented as ‘-’ in VHDL

Simulator

treated as a literal value

For output, it indicates that a choice for that output’s
state has not been made

Synthesizer

treated as a literal value

For output, it is treated as a true don’t care condition
used for logic minimization
EXAMPLE: PRIORITY ENCODER
RTL Schematic w/ don’t care conditions
EXAMPLE: PRIORITY ENCODER W/ DON’T
CARE CONDITIONS

A <= "00" when temp = "---1" else

"01" when temp = "--10" else
"10" when temp = "-100" else
"11" when temp = "1000" else
"ZZ";
EXAMPLE: PRIORITY ENCODER W/ DON’T
CARE CONDITIONS & STD_MATCH

A <= "00" when std_match(temp, "---1") else

"01" when std_match(temp, "--10") else
"10" when std_match(temp, "-100") else
"11" when std_match(temp, "1000") else
"ZZ";
SEATWORK 3-1
1. Given the entity diagram, create a dataflow
VHDL description of a 3-to-8 line decoder. Use
selective signal assignment. (Note: Follow the
truth table of the 74LS138 for the behavior of the
system).

decoder3to8
A(3)
G1 D(8)
nG2A
nG2B
SEATWORK 3-1
2. Given the entity diagram, create a dataflow
VHDL description of a 8-input priority encoder.
Use conditional signal assignment with don’t care
conditions and std_match function. (Note: Follow
the truth table of the 74LS148 for the behavior of
the system).
PEncoder
nI(8) nGS
nE A(3)
nEO
LOOKUP TABLE

A simple way to describe a combinational system

For single output systems, use a constant vector

For multiple outputs systems, use an array of

constant vectors

Usually uses the to_integer function found in
the package numeric_std

Hardware implementation is similar to a ROM
LUT EXAMPLE 1
A B C Y library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
0 0 0 0 use IEEE.NUMERIC_STD.ALL;
0 0 1 1 entity LUT_1 is
Port ( A, B, C : in STD_LOGIC;
0 1 0 - Y : out STD_LOGIC);
0 1 1 0 end LUT_1;
architecture Behavioral of LUT_1 is
1 0 0 1
constant output : std_logic_vector (0 to 7) :=
1 0 1 - "01-01-10";
begin
1 1 0 1 y <= output(to_integer(unsigned'(A, B, C)));
1 1 1 0 end Behavioral;
LUT EXAMPLE 2
input output library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
00 11 use IEEE.NUMERIC_STD.ALL;
01 10 entity LUT_2 is
Port ( input : in STD_LOGIC_VECTOR (1 downto 0);
10 01 output : out STD_LOGIC_VECTOR (1 downto 0));
11 00 end LUT_2;
architecture Behavioral of LUT_2 is
type bin2ref is array (0 to 3) of std_logic_vector(1 downto 0);
constant reflected_lut : bin2ref := ("11", "10", "01", "00");
begin
output <= reflected_lut(to_integer(unsigned(input)));
end Behavioral;
SIMULATION WAVEFORMS
SEATWORK 3-2
1. Given the ff. truth table, write a complete VHDL
description for a design entity named two_out_lut
that implements the function described by the
truth table above. The architecture body must
use only a lookup table to implement this
function.
decoder3to8
A(3)
G1 D(8)
nG2A
nG2B
SEATWORK 3-2
2. Given the ff. truth table, A B C X Y
write a complete VHDL 0 0 0 1 0
description for a design 0 0 1 0 -
entity named two_out_lut 0 1 0 1 0
that implements the 0 1 1 0 -
function described by the 1 0 0 0 0
truth table above. The 1 0 1 - 1
architecture body must use 1 1 0 - 0
only a lookup table to
1 1 1 1 1
implement this function.
SOURCE

VHDL for Engineers, Kenneth Short, Pearson
Education, Inc., 2009

VHDL Modular Design and Synthesis of Cores

and Systems, Zainalabedin Navabi, Mc-Graw-
Hill Companies, 2007