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FLIP-FLOPS AND COUNTERS

1. A combinational logic circuit

a) must contain flip-flop s b) may contain flip-flops

c) does not contain flip-flops d)contains latches

2. The output of a logic circuit depends upon the sequence in which the input is applied .the circuit

a) is a combinational logic circuit

b) is a sequential logic circuit

c) may be a combinational or sequential logic circuit

d) is none of the above

3. A sequential circuit does not use clock pulses. It is

a)an asynchronous sequential circuit b)a synchronous sequential circuit

c)a counter d)a shift register

4. The basic memory element in a digital circuit

a)consists of a NAND gate b)consists of NOR gate

c) is a flip-flop D)is a shift register

5. A flip-flop has two output which are

a) always 0 b)always 1

c)always complementary d)all of the above states

6. A flip-flop can be made using

a) basic gates such as AND,OR and NOT b)NAND gates

c) NOR gates d) any of the above

7. Which of the following flip-flop is used as a latch?

a) J-K flip-flop b) master-slave flip-flop

c) T flip-flop d) D flip-flop

8. Which of the following flip-flop is used as a latch?

a) J-K flip-flop b) master-slave flip-flop

c) S-R flip-flop d) T flip-flop

9. A flip-flop can store

a) one bit of data b)two bits of data

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c)three bits of data d)any number of bits of data

10. When an inverter is placed between the inputs of an S-R flip-flop, the resulting flip-flop is a

a) J-K flip-flop b) master-slave flip-flop

c) T flip-flop d) D flip-flop

11. Which of the following input combinations is not allowed in an S-R flip-flop?

a)S=0,R=0 b)S=0,R=1

c)S=1,R=0 d)S=1,R=1

12. The functional difference an S-R flip-flop and J-K flip-flop is that

a) J-K flip-flop is faster than S-R flip-flop b) J-K flip-flop has a feedback path

c)J-K flip-flop accepts both input 1 d)J-K flip-flop does not required external clock

13. When a flip-flop is set, its outputs will be

a) Q=0,=0 b)Q=1,=0 C)Q=0,=1 d)Q=1,=1

14. When a flip-flop is reset, its outputs will be

a)Q=0,=0 b)Q=1,=1 C)Q=0,=1 d)Q=1,=0

15. The race around condition occurs in a J-K flip-flop when

a. both inputs are 0 b)both inputs are 1

c) the inputs are complementary d)any one of the above input combinations is present

16. Master-slave configuration is used in flip-flops to

a. increase its clocking rate b. reduce power dissipation

c. eliminate race-around condition d. improve its reliability

17. Flip-flop can be used to make

a. latches b .bounce-elimination switches

c. registers d. all of the above

18. The toggle mode for a j-k flip-flop is

a. J=0, K=0 b. J=1, K=0 C.J=0, K=1 d. J=1, K=1

19. The transparent latch is

a. an S-R flip-flop b .a D flip-flop C. a T flip-flop d. a J-K flip-flops

20. The characteristic equation of a J-K flip-flop is

a.Qn+1= Jn+ K Qn b. JQn +kn c) J n+ Qn d. J n+k Qn

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21. The characteristic equation of a D flip-flop is

a.Qn+1=D b) Qn+1=Qn c) Qn+1=1 d) Qn+1= n

22. The characteristic equation of a T flip-flop is

a. n+1= nT+ Qn T b) Qn+1= n T + QnT c) Qn+1= Qn d) Qn+1= n

23.The characteristic equation of a S-R flip-flop is

a. Qn+1= Qn R +S b) Qn+1= nR+S C) Qn+1= Qn R+ S d) Qn+1= Qn

24. A shift register using flip-flop is called a

a. dynamic shift register b. flip-flop shift register

c. static shift register d. buffer shift register

25. A universal register

a. accepts serial input b. accepts parallel input

c. gives serial and parallel outputs d. is capable of all of the above

26. How many states a 6-bit ripple counter can have?

a.6 b.12 c.32 d.64

27. How many flip-flops are needed to divide the input frequency by 40?

a.4 b.5 c.6 d.40

28. The number of flip-flops required for decade counter is

a.3 b.4 c.5 d.10

29. The minimum number of flip-flops required for a mod -12 ripple counter is

a.3 b.4 c.6 d.12

30. The maximum number that can obtained by a ripple counter using five flip-flop is

a.32 b.5 c.16 d.31

31. The number of flip-flops required for a mod-16 ring counter is

a.4 b.8 c.15 d.16

32. The number of flip-flops required for a mod-12 Johnson counter is

a.4 b.6 c.12 d.24

33. In a counter circuit consisting of four J-K flip-flops, all the flip-flops get triggered simultaneously .this counter circuit

a. is a combinational circuit b. is an asynchronous circuit

c. is a synchronous circuit d. may be a combinational or a sequential circuit

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34. In a 4-bit binary ripple counter, for every input clock pulse

a. all the flip-flops get clocked simultaneously

b. only one flip-flops gets clocked at a time

c. only two flip-flops get clocked at a time

d. all the above statements are false

35. A 4 bit binary ripple counter uses flip-flops with propagation delay time of 25 ns each. The maximum possible time required
for change of state will be

a. 25ns b.50ns c.75ns d.100ns

36. A4 bit synchronous counter uses flip-flops with propagation delay time of 25 ns each. The maximum possible time required
for change of state will be

a. 25ns b.50ns c.75ns d.100ns

37. A mod-2 counter followed by a mod-5 counter is

a. the same as amod-5 counter followed by a mod-2 counter b. a decade counter

c. amod-7 counter d. none of the above

38. A 4-bit preset table up-counter has present input 0101.the presetting operation takes place as soon as the counter becomes
maximum, i.e .1111.the modulus of this counter is

a. 5 b.10 c.11 d.15

39. In general, a sequential logic circuit consists of

a. only flip-flop b. only gates

c. flip-flops and combinational logic circuits d. only combinational logic circuit

40. The output frequency of amod-16 counter, clocked from a 20 -kHz clock input signal is

a. 20 kHz b. 52 kHz c. 625 Hz d. 1250 Hz

41. The output frequency of amod-12 counter is 6 kHz .its input frequency is

a. 6kHz b. 500 kHz c. 24 kHz d. 72 kHz

42. A sequential circuit with ten states will have

a. 10 flip-flops b.5 flip-flops c.4 flip-flops d.0 flip-flops

43.

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A ripple counter using negative edge triggered flip flop as shown above. The flip-flops are cleared to 0 at R input.The feed
back logic Is to be degined to obtain the count sequence shown in the same figure.The correct feed back logic is

44. The figure shows a mod N counter where n is equal to

(a)1 (b)2 (c)3 (d)4

45. The given shows a ripple counter using positive edge triggered flip flops. If the present state of the counter Q 2Q1Q0= 011 .
Then its next state Q2Q1Q0 will be

(a)011 (b)100 (c)010 (d)110

46. Two flip-flops are to be connected as a synchronous as shown below that goes through the following Q 1Q0 sequence 00
01 11 10. The inputs D0&D1 respectively should be connected as

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47. For the circuit shown in figure the counter state Q1Q0 will follows the sequence

(a)00,01,10,11,00--- (b)00,01,10,00,01---- (c)00,01,11,00,01----- (d)00,10,11,00,10----

48. What are the counting stages (Q1,Q2)for the counter shown below? Assume k2=1

(a) 11, 10, 00, 11, 10. (b) 01, 10, 11, 00, 01.. (c) 00, 11, 01, 10, 00. (d) 01, 10, 00, 01, 10.

49. Assuming all the flip flops are in reset condition only, the count sequence observed at Q A in the circuit shown as shown figure

(a) 0010111 (b) 0001011 (c) 0101111 (d)0110100..

50. Two D Flip-flops are connected as a synchronous counter that goes through the following Q B QA sequence 00 11 01
10 00 .The connections of the inputs DA and DB are

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51. The output of the two flip-flops Q1,Q2 in the figure shown initialized to 00, The sequence generated at Q1 upon application
of clock signal is

(a) 01110 (b)01010. (c) 00110.. (d)01100.

52. The circuit shown in figure is

(a) Toggle flip-flop (b)JK Flip flop (c) SR LATCH (D)Master-slave D FLIP-FLOP

53. The mod-n counter using synchronous binary up counter with synchronous clear input is shown in figure. The value of n
is----------------------

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(a)2 (b)3 (c)4 (d)6

54. The figure shows a binary counter with synchronous clear input. With the decoding logic circuit the counter works as

(a) Mod-2 counter (b)mod-4 counter (c) mod-5 counter (d)mod-6 counter

55. The circuit shown consists of J-K Flip Flops, each with an active low synchronous reset input. The counter corresponding to
this circuit is

(a) Mod-5 counter (b) mod-6 counter (c) mod-7counter (d) mod-8 counter

56. A three bit pseudo random number generator is shown. Initially the value of output Y= Y 2 Y1 Y0. The value of output after
three clock pulses.

(a) 000 (b)010 (c)010 (d)100

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57. In the following sequential ckt the initial state of the circuit is Q0Q1=00. The state Q1Q0 immediately after 333 rd clock
pulse is

(a) 00 (b)01 (c)10 (d)11

58. The figure shown is a digital circuit constructed using negative edge triggered J-K Flip-Flops. Assuming a starting state of
Q2Q1Q0=000. This state Q2Q1Q0=000 will repeat after ------------------ number of clock pulses

(a) 1 (b)2 (c)4 (d) 6

59. Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor and the supply voltage is 5V. The D
flip-flops D1, D2, D3, D4 and D5 are initialized with logicvalues 0,1,0,1 and 0, respectively. The clock has a 30% duty cycle R
10k.

(a) 1.1mw (b)1.5mw (c)5mw (d)10mw

60. For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.
If the clock (Clk) frequency is 1 GHz, then the counter behaves as a

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(A)Mod3 (b)mod4 (c) mod7 (d) mod8

61. The current state QA QB of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of
the JK flip-flop. The next state of the system is

(a) 00 (b)01 (c)11 (d) 10

62. A 4-bit shift register circuit configured for right-shift operation in is shown. If the present state of the shift register is ABCD
= 1101, the number of clock cycles required to reach the state ABCD = 1111 is _________.

(a) 5 (b) 4 (c)8 (d)10

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