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# Assignment-1

## 1. Draw the minimised two level NOR gate implementation of function

F, where F(A,B,C,D) = m(9,11,12,14) + d(1,3,4,6).

## 2. A decoder with an enable input can be used as a DEMUX. Justify

and design a 3:8 decoder using 2:4 decoder so that it can also be used
as a 1:8 DEMUX.

3.

## In the figure given above, ABCD = 1001 is a 4-bit Binary input

data. Find all three outputs of the 2-bit magnitude comparator,
assuming Odd parity system for Hamming Code Encoder and input
line having highest decimal subscript is having the highest priority
in the Priority Encoder.

## 4. Design a Combinational circuit using 2-input basic gates only which

has three inputs A, B & C and three outputs X, Y & Z. When the
decimal equivalent of the binary input is 0, 1, 5 or 3, the decimal
equivalent of the binary output is one greater than the input and when
decimal equivalent of the binary input is 4, 2, 6 or 7, the decimal
equivalent of the binary output is one less than the input.

5. Design a 4:2 Priority Encoder such that the order of priority of the
decimal inputs is given as D2 > D0 > D1 > D3, where all Dis are
inputs to the priority encoder.

## 6. Implement the following logic function using an 8:1 MUX

F(A,B,C,D)= + + .

7. Design both even parity bit generator and odd parity generator for a
3-bit input using one 4X1 MUX and two XOR gates only.
8. Design a logic circuit using minimum number of NAND gates to
detect the decimal numbers 5 through 12 in a 4-bit Gray code input.
Implement 1-bit binary comparator using a 2:4 decoder and basic
gates.

9. Assume that that XOR gate has propagation delay of 10 nS and the
AND or OR gates has propagation delay of 5 nS. What is the total
propagation delay time in the 4-bit ripple carry adder and 4-bit look