624
5, OCTOBER 2003
Circuit Implementation of Linguistic-Hedge Fuzzy
Logic Controller in Current-Mode Approach
Chuen-Yau Chen, Member, IEEE, Yuan-Ta Hsieh, and Bin-Da Liu, Senior Member, IEEE
AbstractIn this paper, a novel fuzzy logic controller called
linguistic-hedge fuzzy logic controller in a mixed-signal circuit
design is discussed. The linguistic-hedge fuzzy logic controller
has the following advantages: 1) it needs only three simple-shape
membership functions for characterizing each variable prior to
the linguistic-hedge modifications; 2) it is sufficient to adopt nine
rules for inference; 3) the rules are developed intuitively without
heavy dependence on the endeavors of experts; 4) it performs
better than conventional fuzzy logic controllers; and 5) it can be
realized with a lower design complexity and a smaller hardware
overhead as compared with the controllers that required more
than nine rules. In this implementation, a current-mode approach
is adopted in designing the signal processing portions to simplify
the circuit complexity; digital circuits are adopted to implement
the programmable units. This design was fabricated with a TSMC
0.35 m single-polysilicon-quadruple-metal CMOS process.
In this chip, the LHFLC processes two input variables and one
output variable. Each variable is specified using three membership
functions. Nine inference rules, scheduled in a rule table with a
dimension of 3 3, define the relationship implications between
these three variables. Under a supply voltage of 3.3 V, the mea-
surement results show that the measured control surface and the
control goal are consistent. The speed of inference operation goes
up to 0.5M FLIPS that is fast enough for the control application of
the cart-pole balance system. The cart-pole balance system experi-
mental results show that this chip works with nine inference rules.
Furthermore, by performing some off-chip modifications, such as
shifting and scaling on the input signals and output signal of this
design, according to the specifications defined by the controlled
plants, this design is suitable for many control applications.
Index TermsCurrent mode, fuzzy logic controller, linguistic
hedge.
I. INTRODUCTION
F UZZY logic, proposed by Zadeh in 1965, is a logic with
fuzzy truth, fuzzy connectives and fuzzy rules of infer-
ence rather than the conventional two-valued or even multi-
valued logic [1]. It combines multi-valued logic, probability
Manuscript received July 15, 2002; revised September 24, 2002 and De-
cember 2, 2002. This work was supported by the Chip Implementation Center
and the National Science Council, Republic of China, under Grant NSC-91-
2215-E-006-029.
C.-Y. Chen was with the Department of Electrical Engineering, National
Cheng Kung University, Taiwan 70101, R.O.C. He is now with the Depart-
ment of Electrical Engineering, National Yunlin University of Science and
Technology, Taiwan 64045, R.O.C. (e-mail: cychen@ieee.org).
Y.-T. Hsieh was with the Department of Electrical Engineering, National
Cheng Kung University, Tainan, Taiwan 70101, R.O.C. He is now with
the Chip Implementation Center, Hsinchu, Taiwan 30077, R.O.C. (e-mail:
ythsieh@tn.cic.edu.tw).
B.-D. Liu is with the Department of Electrical Engineering, Na-
tional Cheng Kung University, Tainan, Taiwan 70101, R.O.C. (e-mail:
bdliu@spic.ee.ncku.edu.tw).
Digital Object Identifier 10.1109/TFUZZ.2003.817841
1063-6706/03$17.00 2003 IEEE
IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 11, NO.
theory and a knowledge base to mimick human thinking by
incorporating the uncertainty inherent in all physical systems.
Relying on the human nature of fuzzy logic, an increasing
number of successful applications have been developed, like au-
tomatic process control [2], pattern recognition systems [3] and
so forth.
Conventional control system designs rely heavily on
linearized models or the mathematical descriptions of the
controlled plants. In the real world, nonlinear and more com-
plex systems that have no adequate descriptive mathematical
expressions, have very difficult controller model construction
processes. The fuzzy logic controller (FLC) first implemented
by Mamdani [2] on the basis of the fuzzy logic system gen-
eralized from the fuzzy set theory originated by Zadeh [1]
has appeared to offer a feasible solution to various control
problems [4][8]. In an FLC, the inference engine plays the
role of a kernel. It explores the fuzzy rules preconstructed by
experts to accomplish inference. Since the rules specify the im-
plication relationships between the input and output variables
characterized by their corresponding membership functions,
the rule selections along with the membership functions have
a significant impact on the final performance of the FLC and,
therefore, becomes the major control strategy in FLC design.
The greater the number of membership functions exist, the
greater the number of rules become, and the better the inference
will result.
The advantages of the search ability of the superior charac-
teristics inherent in linguistic hedges and the genetic algorithms
(GAs) [9], [10] are used to design a novel FLC called a lin-
guistic-hedge fuzzy logic controller (LHFLC) [11][16]. In this
controller, each variable utilized is characterized by only three
fuzzy sets with simple-shape membership functions. Therefore,
the maximum number of fuzzy rules required for a system with
input variables is . Moreover, a module called the lin-
guistic-hedge module embedded in this controller plays the role
of a linguistic modifier. It is used to dynamically modify the
shape of simple-shape membership functions according to the
feedback signals from the controlled plants. This modification
action allows the LHFLC to utilize only a few rules and simple-
shape membership functions without any degradation in perfor-
mance. In addition, to prevent the factors from damaging the
system design, the linguistic-hedge module is adjusted using the
attached modified simple-genetic-algorithm (MSGA) module,
modified from the simple genetic-algorithm to make this con-
troller adaptive.
The hardware realizations of fuzzy systems can be consid-
ered from the viewpoint of the application purposes and the
operating signal domains. For the application purposes, the
CHEN et al.: CIRCUIT IMPLEMENTATION OF LINGUISTIC-HEDGE FUZZY LOGIC CONTROLLER
FLCs are divided into two classes; the general-purpose fuzzy
processor and the dedicated fuzzy hardware. However, the
general-purpose fuzzy processors have always been realized on
computers, processors, and lookup table using digital memory
devices. Although a general-purpose fuzzy processor has
higher application flexibility, it provides lower performance.
For the operating domains of signals, various kinds of hard-
ware realizations of the fuzzy inference system have been
proposed. From the design technique point of view, they are
divided into three groups: analog, digital, and mixed-mode.
Yamakawa [17], [18] first proposed the voltage-mode FLCs
and the current-mode FLCs [19][21], which was followed by
many designs [22][25]. For the digital designs, Togai [26]
proposed a fuzzy logic chip and a fuzzy inference accelerator
for approximate reasoning. Watanabe [27] proposed a digital
VLSI FLC design with dynamic reconfigurable and cascadable
features. Chiueh [28] proposed an optimization structure
for the fuzzy inference mechanism taking advantage of the
fact that few rules are active simultaneously in a rule-based
controller. Daijin [29] implemented an FLC on a reconfigurable
field-programmable gate array (FPGA) system. Fattaruso [30]
proposed a fuzzy logic inference engine designed in a mixed
analog-digital process. Whichever the design techniques are
adopted, all of them focused on conventional FLCs.
In this study, the LHFLC is realized in a mixed-signal VLSI
approach. In this system, the signal processing portions were
designed in a current-mode approach. The programmable units
were designed in a digital approach. Instead of using complex
circuit configurations like those in the voltage-mode approach,
the current-mode approach simplifies the circuit complexity in
the signal processing portions, such as the addition and subtrac-
tion operations can be realized by simply wiring the current sig-
nals together according to Kirchhoffs Current Law (KCL).
II. FUZZY LINGUISTIC HEDGES AND LHFLC ARCHITECTURE
A. Fuzzy Set Theory and Fuzzy Set Operations
Fuzzy sets have been interpreted as membership functions
that associate with each element of the universe of dis-
course a number in the interval [0, 1]. Unlike the
crisp set logic that distinguishes the members of a given set from
no-members by binary decision, the fuzzy sets are characterized
by their membership functions. In order to manipulate the fuzzy
sets as well as ordinary sets with Boolean operations, Zadeh [11]
proposed the extension of the ordinary set theory for fuzzy sets.
Let and be two fuzzy sets in with membership functions
and , respectively. The fuzzy set operations of union, in-
tersection, and complement are defined as follows.
Union:
(1)
Intersection:
(2)
625
Fig. 1. Effects of the fuzzy linguistic hedge very and more or less.
Complement:
(3)
These fundamental fuzzy operations are often used to build the
other fuzzy logic functions.
B. Fuzzy Linguistic Hedges
In a fuzzy logic based system, the information is described
linguistically. The linguistic hedge is an operator with an op-
eration like a modifier used to modify the shape of member-
ship functions. According to the statement in [11], linguistic
hedge operations are classified into three categories: concentra-
tion, dilation, and contrast intensification. In this paper, only
the concentration type and the dilation type hedge operations
are focused.
ConcentrationApplying a concentration operator to a
fuzzy set results in the reduction in the magnitude of the
grade of membership of in which is relatively small for
those with a high grade of membership in and relatively
large for those with low membership. The linguistic-hedge
operation of concentration x defined by Zadeh [11] is
(4)
Based on the above definition, a few related linguistic-hedge
operations such as absolutely, very, much more, more, and plus
can be defined by specifying the values of in (4) as 4, 2, 1.75,
1.5, and 1.25, respectively [12], [15].
DilationIn contrast, the effect of dilation is opposite to that
of concentration. The linguistic-hedge operation of dilation x
defined by Zadeh [11] is
(5)
Similarly, some related linguistic-hedge operations such as
minus, more or less, and slightly is defined by specifying the
values of in (5) as 0.75, 0.5, and 0.25, respectively [14], [15].
In order to consider the hedge effect on the fuzzy set, the
hedge operator very is used to stand for the concentration type
operation; the hedge operator more or less is used to stand for
the dilation type operation. The fuzzy sets cold, very cold, and
more or less cold characterized by their membership functions
, , and are shown in Fig. 1.
In this figure, the membership function of the fuzzy set very
626
Fig. 2. Basic configuration of a fuzzy logic controller.
cold is generated by applying the hedge operator very to that of
the fuzzy set cold while the membership function of the fuzzy
set more or less cold is generated by applying the hedge oper-
ator more or less to that of the fuzzy set cold. Obviously, the
linguistic hedge very tends to narrow the shape of the mem-
bership function and decrease the membership degree; the lin-
guistic hedge more or less tends to widen the shape of the mem-
bership function and increase the membership degree.
C. FLC
An FLC designed on the basis of the fuzzy logic is an ap-
proximate reasoning-based controller, which does not require
exact analytical models and is much closer spiritually to human
thinking and natural language than the traditional logic system.
Fig. 2 shows the block diagram of an FLC consisting of four
principal units: the fuzzifier module, the fuzzy inference engine,
the knowledge base, and the defuzzifier module. In fuzzy con-
trol applications, the observed data are usually crisp. Since the
data manipulation in an FLC is based on fuzzy set theory, fuzzi-
fication is necessary during an earlier stage. Fuzzification is re-
lated to the vagueness and imprecision in a natural language,
which translates the input crisp data into the fuzzy represen-
tation for further processing. The most outstanding feature of
fuzzy set theory which made it very attractive for applications is
its ability to model the meaning of natural language expressions.
A fuzzy system is characterized by a set of linguistic statements
according to expert knowledge that is usually represented in the
form of IFTHEN rules expressed as
(6)
The antecedent and the consequence of these IFTHEN rules are
associated with fuzzy concepts, and are often referred as fuzzy
conditional statements. In fact, antecedent is a condition within
the application domain and the consequence is a control action
for the system under control. Above all, the fuzzy control rules
provide a convenient way for expressing control policy and do-
main knowledge. The knowledge base module is used to specify
the control rules, which comprises a knowledge of the applica-
tion domain and the attendant control goals. Moreover, to deal
with the fuzzy information described above, the fuzzy inference
engine employs the fuzzy knowledge base to simulate human
decision making and infer fuzzy control actions. Finally, the de-
fuzzifier module is used to translate the processed fuzzy data
into the crisp data suitable for real world applications.
Essentially, the control strategies in the FLC are based on
expert experience, therefore, the FLC can be regarded as the
simulation of a humanoid control model. When designing an
IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003
FLC, the control strategies must be based on the determination
of the fuzzy membership function of control variables and the
linguistic control rules. Therefore, upon completing the design
of a controller, if the control result fails to meet the system re-
quirements due to a change in the outside environment of the
control system, the system control strategies must be modified
to fit the control objective. The possible solution to this problem
is that either the membership function of the fuzzy sets or the
control rules to achieve the control objective can be adjusted.
D. LHFLC Architecture
The LHFLC is designed by taking advantage of the superior
characteristics inherent in the linguistic hedges which can be
used to modify the shape of the fuzzy membership functions in
order to achieve better inference performance. The major differ-
ence between this proposed LHFLC and the conventional FLC
is that a module called linguistic-hedge module is inserted into
the conventional FLC to adjust the shape of fuzzy membership
functions dynamically according to the feedback signal from the
controlled plant. Result shows that this LHFLC maintains better
performance even though the number of the inference rules is
reduced to nine rules. Fig. 3 is a block diagram of this LHFLC,
which consists of several modules similar to those in a con-
ventional FLC except for the linguistic-hedge module attached
to the fuzzifier module. Relying on the benefits described, the
number of inference rules used in this LHFLC is nine. These
rules are usually scheduled in a 3 3 rule table. As shown in
Fig. 4, three fuzzy sets labeled NB, ZE, and PB are used in this
architecture, which are the most general and universal represen-
tations of the membership functions used in FLCs. The Z-shape
membership function of fuzzy set NB is expressed as
(7)
.
The -shape membership function of fuzzy set ZE is
expressed as
(8)
.
The S-shape membership function of fuzzy set PB is
expressed as
(9)
.
In order to apply the linguistic-hedge operations to the pro-
posed FLC, the input-variable domains are partitioned into
intervals. Mathematically, the membership functions ,
, and seem to be assembled using piecewise
linear functions. These partitioned membership functions, de-
noted as , , and , are expressed as
(10)
CHEN et al.: CIRCUIT IMPLEMENTATION OF LINGUISTIC-HEDGE FUZZY LOGIC CONTROLLER 627

Fig. 3. Architecture of LHFLC.

interval of membership function. Since the matrix is diag-

onal, the membership functions , , and
, resulting from modification by corresponding lin-
guistic-hedge operators, can be expressed as

(16)
Upon processing in the fuzzifier module and the linguistic-
hedge module, the resulting signals are sent to the inference en-
Fig. 4. Membership functions applied to LHFLC.
gine. This stage infers the fuzzy control actions employing fuzzy
implication and rules constructed using expert experience. The
where denotes the trace of a matrix and is the partition
fuzzy reasoning method adopted in the LHFLC is Mamdanis
matrix defined as
Minimum Operation Rule [31]. The final stage is the defuzzifier
module whose function is to transfer the signal from a fuzzy set
(11) into the real world for obtaining the actual control actions. The
widely used method, central of gravity (COG) [6], was adopted
in which denotes the step size of the input domain partition,
in the proposed LHFLC.
is the unit step function of defined as when denotes
According to the aforementioned descriptions, this architec-
the step size of the input domain partition, and is the unit
ture is able to simplify the complexity of the LHFLC design
step function of defined as
both in the architecture itself and the hardware realization.
(12) From the viewpoint of the LHFLC architecture, inserting
a linguistic-hedge module allows for the use of the simple
and is the basis of the -dimensional vector space, which is triangle-like membership functions and nine rules instead of
defined as the more carefully designed membership functions and a large
number of rules to reach the control goals. As a result, the
(13) membership function constructions and the rule developments
and become simple. From the viewpoint of the hardware realization,
by comparing this LHFLC and the conventional FLCs, only
(14) one extra module, called a linguistic-hedge module, is inserted.
otherwise. The fuzzifier circuit (membership function generator) becomes
The membership function in each interval more simple than those in conventional FLCs because only
is now modified by its corresponding linguistic-hedge operator three and more simple triangle-like membership functions are
which is the th element of the linguistic-hedge combination generated. Thus, the size of memory is decreased dramatically
vector defining the proper linguistic-hedge op- because nine rules are required for storing. Therefore, this
erators of the intervals of the whole input domain. For the LHFLC can be realized with low design complexity and small
convenience of mathematical expression, the linguistic-hedge hardware overhead.
combination matrix is defined as In the LHFLC, the linguistic-hedge combinations, which are
difficult to acquire from human experience and knowledges,
(15) must be tuned. To acquire an optimal combination, the MSGA
That is, every entry for is 0 except the diagonal entries s as the search method was adopted. In this work, the MSGA
which give the linguistic-hedge operators of the corresponding module works offline. That is, it searches for the optimal lin-
628
guistic-hedge combination vector according to the controlled
plants specified, and then provides this solution to the linguistic-
hedge module to make the LHFLC adaptive.
According to the eight linguistic-hedge operations mentioned
before and the empty-hedge operation defined as
- (17)
there are nine possible linguistic-hedge operations to be
adopted in the linguistic-hedge module for modifying the
corresponding membership functions properly. Consider the
input domain partitioned into intervals, each with its own
linguistic-hedge operations. In the case of a system with three
fuzzy sets, the overall number of linguistic-hedge combinations
is as many as . To simplify this search problem, these
three membership functions are investigated, as shown in Fig. 4
again. The demonstrated significant result is their symmetrical
property. That is, the membership function is self-sym-
metrical about the line . The membership functions
and are symmetrical to one another about
the line . Therefore, the linguistic-hedge combination of the
fuzzy set ZE ranging from the first interval to the th interval
and those ranging from the st interval to the th
interval must be symmetrical about the line . Accordingly,
the linguistic-hedge combination vector used to specify the
membership function of the fuzzy set ZE must be in the form of
(18)
where specifies the linguistic-hedge opera-
tors corresponding to the intervals to the left of the line ,
and is the vector whose elements are in the reverse order
with respect to those of , i.e.,
(19)
where the transfer matrix is defined as
.. .. .. (20)
. . . by
Similarly, consider the fuzzy sets NB and PB. The linguistic-
hedge combination vector specifying the linguistic-hedge op-
erators ranging from the first interval to the th interval of
the fuzzy set NB and the linguistic-hedge combination vector
specifying the linguistic-hedge operators ranging from the
st interval to the th interval of the fuzzy set PB
must be also symmetrical about the line . That is
(21)
Obviously, once the vector and the vector are determined,
the vectors and can be also obtained in turn. The
linguistic-hedge combination vector used to specify the fuzzy
sets NB and PB becomes
(22)
where specifies the linguistic-hedge operators ranging from
the first interval to the th interval of the fuzzy set NB while
specifies the linguistic-hedge operators ranging from the
st interval to the th interval of the fuzzy set PB.
Accordingly, the linguistic-hedge combination vectors that we
must determine are and with the dimension of . ac signal. The purpose of the operation scale in this work is
IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003
III. CIRCUIT IMPLEMENTATION
A. Architecture for VLSI Implementation of Linguistic-Hedge
Fuzzy Logic Controller
According to the characteristics, such as the signal flows,
number of fuzzy sets, and number of inference rules, inher-
ently in the LHFLC, the corresponding circuit implementation
architecture as shown in Fig. 5 is proposed. This architecture
represents a two-inputone-output LHFLC, which contains sev-
eral units including the fuzzification unit, the programmable lin-
guistic-hedge unit, the programmable inference-rule-base unit,
the defuzzification unit, the sample-and-hold units, and the dig-
ital-memory units. In the fuzzification unit, there are two pairs
of fuzzifier circuits each of which contains three types of fuzzi-
fier circuits that represent the fuzzy sets NB, ZE, and PB, re-
spectively. In the programmable linguistic-hedge unit, there are
six linguistic-hedge circuit sets (LHCS) each of which contains
eight kinds of linguistic-hedge circuits. In the programmable in-
ference-rule-base unit, there are nine two-input minimum cur-
rent selector circuits and three nine-input maximum current se-
lector circuit, which are bridged by 27 voltage-controlled cur-
rent switches with control signals programmed by a 27-bit se-
rial-inputparallel-output (SIPO) shift register. In the defuzzi-
fication unit, there is one three-input defuzzifier circuit. The
mixed-signal approach is adopted to realize this architecture.
According to the signal modes, the whole design is divided
into two kinds of portions. The first portions are those designed
using the current-mode approach. The second portions are those
designed using digital approach. The current-mode approach
was adopted to design the signal processing units, such as the
fuzzification unit, the programmable linguistic-hedge unit, the
programmable inference-rule-base unit and the defuzzification
unit, such that the circuit complexity will be decreased. The dig-
ital approach was adopted to design the digital-memory units,
such as the SIPO shift registers.
Definition 1: The function : defined
where for all , is
called the membership-degree-current function for [0, 1].
Definition 2: The function : defined
by
(23)
where and , is
called the fuzzy-label-current function for .
Definition 3: If : and
(24)
where is a constant, for all , then we call a distor-
tionless function from to .
Consider the signal specifications. For convenience, the vari-
ables in the mathematical domain are shifted and scaled such
that some simplifications in circuit implementation can be ob-
tained. The purpose of the operation shift in this work is to
add a bias quantity to a variable such that it becomes a non-
negative that can be realized using a dc signal rather than an
CHEN et al.: CIRCUIT IMPLEMENTATION OF LINGUISTIC-HEDGE FUZZY LOGIC CONTROLLER 629

Fig. 5. VLSI architecture of LHFLC.

implementation specifications of the proposed LHFLC in this

paper are as follows:
number of input variables 2;
number of output variable 1;
number of fuzzy sets specifying each input variable 3;
number of fuzzy sets specifying output variable 3;
number of inference rules 9;
range of input and output variables [0 A, 32 A];
range of membership degrees [0 A, 16 A];
maximum overlap between membership functions 2;
number of intervals each input domain can be partitioned
into 16;
number of linguistic-hedge operators 8;
COG defuzzification;
Fig. 6. (a) Symbol of the current repeater circuit. (b) Symbol of the inference speed 0.5M FLIPS (fuzzy logic inference per
current comparator circuit. (c) Symbol of the square-rooter/multiplier circuit. second).
(d) Symbol of the squarer/divider circuit.
B. Basic Components
to magnify or shrink a variable into a reasonable range such 1) Current Repeater: In the current-mode circuit design
that the signal-to-noise ratio (SNR) is acceptable in the cir- methodology, because the fan-out of the current-mode circuit
cuit implementation phase. In this design, the operations shift is one, the current repeater is required to connect and transmit
and scale are applied to the related variables by means of the current signals between the circuit cells. Fig. 6(a) is the
the membership-degree-current function defined in Definition 1 symbol of the current repeater circuit with the inputoutput
and the fuzzy-label-current function defined in Definition 2. For (I/O) relationship [15]
the fuzzy sets of the input variables and output variable of the (25)
LHFLC, the fuzzy label of fuzzy set NB is represented by a cur-
rent signal A, the fuzzy label of fuzzy where is the input current; are the duplicated cur-
set ZE is represented by a current signal rents of .
A, and the fuzzy label of fuzzy set PB is represented by 2) Current Comparator: Fig. 6(b) shows the symbol of the
a current signal A. For the member- current comparator circuit. The function of this circuit is to com-
ship degrees, the mathematical domain [0, 1] is mapped into a pare two input current signals denoted as and , and indicate
current-signal range [0 A, 16 A] using the membership-de- the result by the output voltage denoted as . The I/O relation-
gree-current function defined in Definition 1where the current ship can be described as [15]
signal A stands for zero-membership and the cur- V if
(26)
rent signal A stands for full-membership. The V if
630 IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003

Fig. 7. (a) Schematic of the minimum current selector circuit. (b) Symbol of the minimum current selector circuit.

3) Square-Rooter/Multiplier Circuit: The square-rooter/ are equal in turn. Under this situation, the differential pair is
multiplier circuit in Fig. 6(c) is designed to multiply the two balanced, and and share the bias current . Consider
input current signals and first, and then calculate the the case that is slightly decreased. The decrease in forces
square-root of this product. If the two input currents for this to decrease, which causes . Once the condition
circuit are and , then the output current is expressed
as [14], [33] (30)
(27)
is satisfied, all of the bias current will be sunk by ,
4) Squarer/Divider Circuit: The schematic of the squarer/ and sinks zero current which breaks the negative-feedback
divider circuit is shown in Fig. 6(d). Assume that the input cur- loop formed by and . Consider the negative-feedback
rents for this circuit are and , and the output current is loop formed by and again. The decrease in leads to
, then the circuit has the I/O relationship [12], [34] the decrease in . The decrease in leads to the decrease in
such that the source-to-drain current of is not more
(28) than . The decrease in leads to a decrease in the
gate-to-source voltage of , therefore, increases to keep
5) Minimum Current Selector Circuit: Fig. 7(a) shows the the drain-to-source current as in . The negative-feedback
circuit diagram of the minimum current selector circuit. The mechanism continues until a stable condition is met. Under
circuit is designed by generalizing the current-mode multiple- the stable condition, only the negative-feedback loop formed
input minimum circuit proposed by Huang and Liu [35]. The by and exists while the other loop is broken. The gate
principal function of this circuit is to detect the minimum current voltage of dominates . The minimum current signal
among all its input currents, and generate the minimum current is mirrored to the output terminal through the current mirror
at its output terminal. The following expression describes the formed by and , and the current mirror formed by
input and output relationship of this circuit .
According to the previous descriptions, the resolution of dis-
(29) tinguishing nonidentity currents heavily depends on the sensi-
where and are the input current signals and is the tivity of with respect to . Take the first input terminal as an
output current signal, which is equal to the minimum current of example, the sensitivity of with respect to is
and .
The operational principle of this circuit is described as fol- (31)
lows. As in the schematic shown in Fig. 7, the transistors ,
, , and are the core part of this circuit. The transistors Obviously, the sensitivity of with respect to is proportional
and form a differential pair which sinks the bias current to the input impedance . For this reason, transistors and
provided by a constant current source. The transistors are added to the minimum circuit proposed by Huang and
and form a negative-feedback loop, and so do the transistors Liu [35] to increase the input impedance at each input terminal.
and . At the beginning, assume that the input current sig- As shown in Fig. 7(a), let the drain-to-source impedance of
nals and are equal. The voltages and built by and be , the drain-to-source impedance of be , the gate
CHEN et al.: CIRCUIT IMPLEMENTATION OF LINGUISTIC-HEDGE FUZZY LOGIC CONTROLLER 631

Fig. 10. Schematic of Z-shaped membership function generator circuit.

Fig. 8. (a) Schematic of the maximum current selector circuit. (b) Symbol of
the maximum current selector circuit. The operational principle of this circuit is described as follows.
The transistors , , , , and
are the core part of this circuit. The s tran-
sistors form a nine-input source couples with their source ter-
minals tied together and their nine input terminals connected to
the drains of s, respectively. The transistors and
are connected as an active load which provides a bias current to
the source couples as mentioned. The transistors and
form a negative-feedback loop. The operation of this circuit is
based on this negative-feedback mechanism. At the beginning,
assume that all of the input currents are equal. The drain voltage
s built by the current signals s are also equal, and so are the
gate voltages at s. The source couplers are under a balanced
condition, which means that the s equally share the bias cur-
rent provided by the active load formed by and . Con-
sider the case that is slightly increased. The increase in
Fig. 9. (a) Schematic of the SI memory cell. (b) Symbol of the SI memory cell. forces to decrease, which causes .
Once the condition

impedance of be , and the transconductance of be

. The input impedance at the drain terminal of becomes (34)

(32) is satisfied, all of the bias current will be sunk by ,

and the other transistors of the source couplers sink zero
which means that the sensitivity of with respect to is much currents which breaks the negative-feedback loop formed by
larger in this circuit than in that proposed by Huang and Liu and . Consider the negative-feedback
[35]. This implies that this design performs at a much higher loop formed by and again. The increase in leads
resolution. to the increase in . The increase in leads to the decrease
6) Maximum Current Selector Circuit: Fig. 8 shows the cir- in such that the source-to-drain current of is kept
cuit diagram of the maximum current selector circuit. This cir- as in . The decrease in leads to the increase in the
cuit was designed by generalizing the current-mode multiple- source-to-gate voltage of , therefore, decreases to keep
input maximum circuit proposed by Huang and Liu [36] which the source-to-drain current no greater than . The nega-
is extended from the winner-take-all (WTA) circuit proposed tive-feedback mechanism continues until a stable condition is
by Lazzaro [37]. The principal function of this circuit is to de- met. Under the stable condition, only the negative-feedback
tect the maximum current among all of its input currents and loop formed by and exists while the other loops
generate this maximum current at its output terminal. The fol- are broken. The gate voltage of dominates . The
lowing expression describes the input and output relationship of maximum current signal is mirrored to and , and
this circuit transferred to the output terminal through .
According to the previous descriptions, the resolution of dis-
(33) tinguishing nonidentity currents heavily depends on the sensi-
632 IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003

Fig. 11. Schematic of ^-shaped membership function generator circuit.

tivity of with respect to . Take the first input terminal as an

example, the sensitivity of with respect to is

(35)

Obviously, the sensitivity of with respect to is proportional

to the input impedance . For this reason, the transistors
are added to the maximum circuit proposed by Huang and Liu
[36] to increase the input impedance at each input terminal. Take
the first input terminal as an example. As shown in Fig. 8(a), let
the drain-to-source impedance of be , the drain-to-
source impedance of be , the gate impedance of
be , and the transconductance of be . The input
impedance at the drain terminal of becomes

Fig. 12. Schematic of S-shaped membership function generator circuit.

(36)

That is, the sensitivity of with respect to is much larger
in this circuit than that proposed by Huang and Liu [36]. This
implies that this design performs at a much higher resolution.
7) Switched-Current (SI) Memory Cell: The SI memory
cell, also known as the current copier or the dynamic current
mirror, was initially conceived to overcome the inherent
matching limitations of continuous time current mirrors. It
also plays a really important role as a current delayer in the
current-mode design. There are SI memory cells with various
structures. The SI memory design in regulated-cascoded struc-
ture proposed by Toumazou [38] as shown in Fig. 9 is selected
for this design. The sample and hold operations of this circuit
can be expressed as
for logic
(37)
for logic
That is, during logic 1, this circuit is in sample
mode, which produces a current signal with 0 A; during
logic 1, this circuit is operated in hold mode, which
outputs the held current signal, , sampled in the pre-
vious sample mode. The clock signals and should be
nonoverlaped which are generated by the clock generator cir-
cuit described in the following section.
C. Fuzzification Unit
The function of the fuzzification unit is to receive the input
crisp current signal and produce output current signal meeting
the corresponding membership value. According to the LHFLC
architecture, there are three types of membership functions; the
Z-shaped membership function, the -shape membership func-
tion and the S-shape membership function. The Z-shaped mem-
bership function specifies the membership between the universe
of discourse and the fuzzy set . The -shaped membership
function specifies the membership between the universe of dis-
course and the fuzzy set . The S-shaped membership func-
tion specifies the membership between the universe of discourse
and the fuzzy set .
CHEN et al.: CIRCUIT IMPLEMENTATION OF LINGUISTIC-HEDGE FUZZY LOGIC CONTROLLER 633

Fig. 13. Linguistic hedge absolutely circuit.

1) Z-Shaped Membership Function Generator Circuit: The

function of the Z-shaped membership function generator cir-
cuit is to generate a membership function with the shape of the
capital letter Z, which produces a current signal that stands Fig. 14. Linguistic hedge very circuit.
for the membership degree corresponding to the input current
signal stands for the crisp input. Fig. 10 shows the schematic of stand for the output corresponding membership degree be ,
the Z-shaped membership function generator circuit composed there is
of three n-channel current mirrors and one p-channel current
mirror. Let the input current signal stands for the crisp input (42)
be and the output current signal stands for the output cor-
responding membership degree be . Applying the KCL at where is used to set the linguistic label of the fuzzy set
node A, the output current signal is derived as .

(38) D. Programmable Linguistic-Hedge Unit

The programmable-linguistic-hedge unit receives the feed-
where ; is used to set the back signal from the plant output and turns on the corresponding
linguistic label of the fuzzy variable. However, according to this hedge switch which bridges the output current signal generated
circuit architecture, a negative current will cease the function by the fuzzifier circuit to the proper linguistic-hedge circuit.
block. Equation (38) is rewritten as This module consists of three principal functional blocks. They
are the linguistic-hedge circuit set, interval decision circuit, and
(39)
register-controlled switch array.
where the operator is defined as E. Linguistic-Hedge Circuits and Linguistic-Hedge Circuit
Sets
(40)
1) Linguistic-Hedge Circuits:
in which is the unit step function defined in (12). Lemma 1: The current-signal representation of the linguistic
2) -Shaped Membership Function Generator Circuit: The hedge is
function of the -shaped membership function generator circuit
(43)
is to generate a membership function with a shape of the symbol
. This generator produces a current signal that stands for the Proof: Mathematically:
membership degree corresponding to the input current signal Let be defined by for all
stands for the crisp input. Fig. 11 shows the schematic of the . Then
-shaped membership function generator circuit composed of (44)
four n-channel current mirrors and two p-channel current mir-
rors. Let the input current signal stand for the crisp input be From the circuit realization viewpoint:
and the output current signal stand for the output corresponding Let : [0 A, 16 A] [0 A, 16 A] be defined by
membership degree be , there is for all A A . Then
(45)
(41)
Comparing terms in (44) and (45), there are
where is used to set the linguistic label of the fuzzy set . (46)
3) S-Shaped Membership Function Generator Circuit: The
(47)
function of the S-shaped membership function generator circuit
is to generate a membership function with the shape of the (48)
capital letter S. This generator produces a current signal Therefore
that stands for the membership degree corresponding to the
(49)
input current signal stands for the crisp input. Fig. 12 shows
a schematic of the S-shaped membership function generator
circuit which is composed of four n-channel current mirrors Lemma 2: The function : [0, 1] [0 A, 16 A] de-
and two p-channel current mirrors. Let the input current signal fined by is a distortionless function of for
stand for the crisp input be and the output current signal all where .
634
Fig. 15. Linguistic hedge much more circuit.
Proof: Since ,
(50)
Therefore, is a distortionless function of
, which means that an 1% variation in will cause
an 1% variation in . as the PI of so another one-to-two current repeater is needed
Definition 4: A function defined as :
where is called a
square-rooter/multiplier function.
Definition 5: A function defined as :
where is called a squarer/divider
function.
Absolutely circuitFrom Lemma 1, the current-mode
representation of the linguistic hedge absolutely denoted as
can be expressed in terms of the composition of
the square-rooter/multiplier function and the squarer/divider
function as
(51)
Consider the relationship between the expression in (51)
and its circuit realization. Since (51) is composed of two s,
two squarer/divider circuits are needed. The current signal
appears twice as the primary input (PI) of , therefore,
an one-to-two current repeater is to generate two copies of
the current signal . Fig. 13 shows the schematic of the
current-mode linguistic hedge absolutely.
Very circuitSince the function of the squarer/divider cir-
cuit is the same as that of the hedge very circuit, the hedge very
circuit can be constructed using the squarer/divider circuit di-
rectly as shown in Fig. 14.
Much more circuitFrom Lemma 1, the current-mode
representation of the linguistic hedge much more denoted as
can be expressed in terms of the composition of
the square-rooter/multiplier function and the squarer/divider
function as
(52)
Consider the relationship between the expression in (52) and
its circuit realization. Since (52) is composed of one and two
s, one squarer/divider circuits and two square-rooter/multiplier
circuits are needed. The current signal appears once as the
IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003
Fig. 16. Linguistic hedge more circuit.
primary input (PI) of and once as the PI of so an one-to-two
current repeater is needed to generate two copies of the current
signal . On the other hand, the current signal appears twice
to generate two copies of the current signal . Fig. 15 shows
the schematic of the current-mode linguistic hedge much more.
More circuitFrom Lemma 1, the current-mode represen-
tation of the linguistic hedge more denoted as can be ex-
pressed in terms of the composition of the square-rooter/multi-
plier function and the squarer/divider function as
(53)
Consider the relationship between the expression in (53) and
its circuit realization. Since (53) is composed of one and one
, one squarer/divider circuit and one square-rooter/multiplier
circuit are needed. The current signal appears once as the
PI of and once as the PI of , therefore, a one-to-two current
repeater is required to generate two copies of the current signal
. Fig. 16 shows the schematic of the current-mode linguistic
hedge more.
Plus circuitFrom Lemma 1, the current-mode represen-
tation of the linguistic hedge plus denoted as can be ex-
pressed in terms of the composition of the square-rooter/multi-
plier function and the squarer/divider function as
(54)
Consider the relationship between the expression in (54) and its
circuit realization. Since (54) is composed of two s and one
, two square-rooter/multiplier circuits and one squarer/divider
circuit are required. The current signal appears twice as the
PI of and once as the PI of . A one-to-three current repeater is
therefore required to generate three copies of the current signal
. Fig. 17 shows the schematic of the current-mode linguistic
hedge plus.
Minus circuitFrom Lemma 1, the current-mode represen-
tation of the linguistic hedge minus denoted as can be
expressed in terms of the composition of the square-rooter/mul-
tiplier function and squarer/divider function as
(55)
CHEN et al.: CIRCUIT IMPLEMENTATION OF LINGUISTIC-HEDGE FUZZY LOGIC CONTROLLER
Fig. 17. Linguistic hedge plus circuit.
Fig. 18. Linguistic hedge minus circuit.
Fig. 19. Linguistic hedge more or less circuit.
Consider the relationship between the expression in (55) and
its circuit realization. Since (55) is composed of two s, two
square-rooter/multiplier circuits are required. The current signal
appears twice as the PI of , therefore, a one-to-two current
repeater is required to generate two copies of the current signal
. Fig. 18 shows the schematic of the current-mode linguistic
hedge minus.
More or less circuitSince the function of the square-
rooter/multiplier circuit is the same as that of the hedge
more or less circuit, the hedge more or less circuit using the
square-rooter/multiplier circuit directly can be constructed, as
shown in Fig. 19.
Slightly circuitFrom Lemma 1, the current-mode repre-
sentation of the linguistic hedge slightly denoted as
can be expressed in terms of the composition of the square-
rooter/multiplier function and squarer/divider function as
(56)
Consider the relationship between the expression in (56) and
its circuit realization. Since (56) is composed of two s, two
square-rooter/multiplier circuits are required. The current signal
appears twice as the PI of , therefore an one-to-two current
repeater is required to generate two copies of the current signal
. Fig. 20 shows the schematic of the current-mode linguistic
hedge slightly.
2) Linguistic-Hedge Circuit Set (LHCS): The LHCS is a set
of linguistic-hedge circuits with a switch at each input terminal.
Fig. 21 shows the schematic of the LHCS. In this design, only
eight linguistic-hedge circuits were selected to build this LHCS.
They are absolutely, very, much more, more, nonhedge, minus,
more or less, and slightly.
635
Fig. 20. Linguistic hedge slightly circuit.
F. Interval Decision Circuit (IDC)
Fig. 22 shows the IDC which consists of a set of current com-
parators and a set of XOR gates. The current signal labeled as
represents the upper-boundary of the th in-
terval over the input domain and is called as the input-do-
main-partition current. The current signal labeled as is the
current signal fed back from the output of the controlled plant.
This set of current comparators subtracts the input-domain-
partition currents, , from the feedback cur-
rent signal and generates the voltages with either 0 V or
3.3 V to indicate whether the difference is negative or positive.
These resulting voltages are then fed to the XOR gates in the
manner shown in Fig. 22. The output voltages of the XOR
gates, the compared currents , and s can be related by
V
(57)
V otherwise
where are the output voltages used to de-
cide the states of the corresponding switches in the register-con-
trolled switch array which will be described in the next section.
G. Register-Controlled Switch Array (RCSA)
The connecting configuration between the output signal
of the fuzzifier circuit and the LHCS is programmed by the
register-controlled switch array (RCSA), as shown in Fig. 23.
The RCSA is built using one 48-bit SIPO register, 48 switches
and one 3-to-8 decoder. This 48-bit SIPO register is partitioned
into 16 groups with three bits in each group. That is, the
48-bit SIPO register can be seen as 16 serial 3-bit registers.
636 IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003

Fig. 21. Linguistic-hedge circuit set.

Fig. 22. Interval decision circuit.

Fig. 23. Register-controlled switch array.

These 48 switches are also partitioned in the same manner. are delivered to the 3-to-8 decoder by connecting the MSBs of
These 16 groups of switches are labeled SWG1, SWG2, , all 3-bit registers to the MSB of the input of the 3-to-8 decoder,
SWG16. The status of these switches is controlled by the and so are the second bits and the LSBs. This 3-to-8 decoder
signals generated by the range will generate the proper signals to control the switches bridging
decision circuit. The data in each group in this SIPO register the fuzzifier circuits and the LHCS.
CHEN et al.: CIRCUIT IMPLEMENTATION OF LINGUISTIC-HEDGE FUZZY LOGIC CONTROLLER
Fig. 24. Block diagram of the minimum current selector circuit array.
H. Programmable Inference-Rule-Base Unit
The programmable inference-rule-base unit is composed
of a 3 3 minimum current selector circuit array and a
programmable rule-base.
1) Minimum Current Selector Circuit Array: Since the
LHFLC has two inputs, each of which is characterized by
three fuzzy sets, there are nine rules scheduled in a rule
table with a dimension of 3 3. In the circuit realization
phase, nine two-input minimum circuits are needed to deter-
mine the minimum current between the two current signals
provided by the LHCS. Fig. 24
shows the minimum circuit array with a dimension of 3 3.
As shown in Fig. 24, the function of each minimum circuit cell
can be expressed as
where
stands for the activated degree of the
rule which specifies the relationship between the th fuzzy set
of the first input variable , the th fuzzy set of the second
input variable , and the output fuzzy set specified in the grid
.
2) Programmable Rule-Base: To achieve a programmable
rule base, the switch array was inserted between the minimum
current selector circuit array and the maximum current selector
circuits as shown in Fig. 25. In this unit, three copies of the cur-
rents sent from the 3 3 minimum cur-
rent selector circuit array are duplicated by the current repeaters
and fed into three nine-input maximum current selector circuits
named MAX_N, MAX_Z, and MAX_P through switch arrays
named SW_N, SW_Z, and SW_P. These three maximum cur-
rent selector circuits, MAX_N, MAX_Z, and MAX_P, calcu-
late the membership degrees representing how the inferred re-
sults belong to the output fuzzy sets, NB, ZE, and PB. A 27-bit
637
Fig. 25. Block diagram of the programmable rule-base.
SIPO shift register with data was adopted to
program these switches. Therefore, the rule base with the di-
mension of 3 3 becomes programmable.
I. Defuzzification Circuit
For an FLC with three output fuzzy sets labeled NB, ZE, and
PB, the current signal standing for the output crisp value gener-
ated by the current-mode COG defuzzifier circuit are expressed
as [40], [41]
(59)
where , , and stand for the fuzzy labels of the
output fuzzy sets NB, ZE, and PB, respectively. , , and
stand for the activated membership degrees of NB, ZE,
and PB, respectively. stands for the crisp output value.
Performing shift and scale operations on all of the variables, the
(58) current signal becomes 0 A. The expression in (59) is
reduced to
and
th (60)
Rewriting (60) in terms of and as defined before, there is
(61)
Consider the relationship between the expression in (60) and
its circuit realization. Since (61) is composed of two s and two
s, two square-rooter/multiplier circuits and two squarer/divider
circuits are required. The current signal
appears twice as the PI of , therefore, an one-to-two current
repeater is needed to generate two copies of the current signal
. Taking advantage of current-mode ap-
proach, the addition of current signals can be easily realized by
wiring the corresponding branches together. Fig. 26 shows the
schematic of the current-mode defuzzifier circuit.
638
Fig. 26. Block diagram of the defuzzifier circuit.
IV. NONIDEAL EFFECTS
The nonideal effects of MOS transistors, neglected in the pre-
vious discussions, always impacts the circuit performance. The
following are precautions for lessening these effects.
A. Body Effect
The increase of the source-to-substrate voltage ( ) in
an MOS transistor will thicken the depletion region, and the
threshold voltage ( ) will increase in turn. This is the body
effect which can be characterized by [42]
(62)
where is the zero-bias threshold voltage, is the body-effect
coefficient, and is the bulk potential.
To avoid this effect, we placed cascoded MOS transistors,
such as and in the squarer/divider circuit, and and
in the squarer-rooter/multiplier circuit, in separate wells to
ensure that is zero. However, the speed of these circuits will
be slowed down due to the large well-to-substrate capacitances.
Although the body effect can be compensated by designing the
related circuits in the translinear up-down topology, thus pre-
cluding the need to place the cascoded MOS transistors in sepa-
rate wells [39], the stacked loop topology is used rather than the
up-down one in the design for the following reasons: 1) almost
any loop equation is easily realized in a stacked loop topology,
and the resultant circuit is usually more compact than that de-
signed in an updown loop topology that would need some extra
circuits to achieve the desired functions; and 2) a stacked-loop
topology often results in a circuit with higher accuracy than an
updown topology.
B. Channel Length Modulation
Taking the channel-length-modulation effect into account, the
square law of an MOS transistor must include the channel-
length-modulation factor, , and is expressed as
(63)
IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003
where is the device transconductance parameter
and is the gate-to-source voltage. This -effect causes the
drain current to depend on the drain-to-source voltage ( ).
The finite output resistance ( ) also causes the load effect
when cascading other stages. To lighten this effect, we provided
two precautions in this design. First, longer channel length MOS
transistors rather than the minimum size were used in the cir-
cuits. For example, the minimum channel lengths of 10 m and
6 m were chosen in the core part of the square-rooter/multiplier
circuit and the squarer/divider circuit, respectively. The criterion
can be found in the simulation results of [41]. Second, a cas-
coded structure was used to increase the output impedances. For
example, the cascoded structure was adopted in the fuzzification
circuit, the minimum current selector circuit and the maximum
current selector circuit.
C. Device Mismatch
The current mirror is the key component in the current-mode
design. The device mismatch problem in the current mirror
makes a big impact on the current-mode circuit design. To con-
sider this problem, the variance in the drain current expressed
in (63) is
(64)
where , , and are the standard deviation of , ,
and , respectively. is the expected value of the random
variable . is the standard deviation of . In [43],
Lakshmikumar indicated that the mismatches in and
are almost independent through the theoretical derivation and
experimental measurements. As a consequence, the mismatch
problem is considered as a mismatch in threshold voltage
and in the conductance constant respectively. According to
the disscussion of Pelgroms model for intradie papameter
variations, , , and decrease as the gate area of the
matching transistors are increased and as the separation dis-
tance between the transistors decreases [44]. To minimize the
mismatch problem, identical devices are not only used in the
circuits but also placed them as close as possible in the layout.
V. EXPERIMENTAL RESULTS
A. Software Verifications
The capability and feasibility of the proposed LHFLC are
demonstrated here. The focus here is to emphasize that the
LHFLC with nine rules can work better than a conventional
FLC with more rules. To do this, three well-known nonlinear
systems including the nonlinear plant model control system,
the truck backer-upper control system, and the cart-pole
balance system are used to verify the performance of the
LHFLC. The number of rules chosen in this LHFLC is nine;
the domain of each input variable is divided into 16 equal
intervals. Throughout this paper, all simulations are performed
with MATLAB [45]. In addition, the physical cart-pole balance
system is also used to demonstrate the feasibility of this
LHFLC.
CHEN et al.: CIRCUIT IMPLEMENTATION OF LINGUISTIC-HEDGE FUZZY LOGIC CONTROLLER 639

1) Nonlinear Plant Model Control System: The first ex-

ample in this work is a non-BIBO nonlinear plant [46] with the
plant model

(65)
where is the input signal of the plant and is its output signal.
The reference model that the plant output will track is chosen as
(66)
The goal of this system is to determine the plant input such
that

(67)

where is a suitably chosen constant. That is, the faster Fig. 27. Simulation result of nonlinear plant model control system.
tracks the reference signal , the better the controller will
TABLE I
perform. The variables and represent the error input PERFORMANCE FACTORS OF NONLINEAR PLANT MODEL CONTROL SYSTEM
and the change rate of error input of the controller, respectively,
which are expressed as
(68)
and
(69)

where the time step is chosen as 0.1 s. Furthermore, in

(65) can be expressed as
(70)
where represents the increment of the plant input at each
iteration. Since the chosen plant model is nonlinear, it is diffi-
cult to handle it when the controller is determined by the clas-
sical control theory. The FLC is therefore a suitable choice to
replace the role played by this controller. The input variables of
the FLC are the error and its change rate ; the output variable
is . In order to stress the power of the proposed LHFLC, the
performance of the system controlled by the conventional FLC Fig. 28. Diagram of simulated truck and loading zone.
with 7 7 rules and 3 3 rules is also concerned [16]
Fig. 27 is the simulation result. The plant output tracks is targeted to drive the truck to the loading dock
the reference signal with 0.3 s settling time, defined as at a right angle .
the time for response to settle within 0.1% of the steady-state At each stage, the fuzzy logic controller produces the steering
value, in the proposed LHFLC system. In contrast, the plant angle which causes the truck to back up to the loading zone
output tracks the reference signal with 1.1 s settling from any initial position with any angle in the plane. The dy-
time when it is controlled by the conventional FLC with 7 7 namic equations describing the truck moving backward from
rules. Also, tracks with 2.7 s settling time when it is to at each iteration can be expressed as [47]
controlled by the conventional FLC with 3 3 rules. Clearly,
the LHFLC possesses the best performance. Table I summaries (71)
these results. (72)
2) Truck Backer-Upper Control System: The truck backer- (73)
upper control system with the goal of parking the truck in a
prescribed parking lot is shown in Fig. 28. Three variables , where is the fixed moving distance of the truck at each itera-
, and describe this system thoroughly, where the variable tion. The constraints of these mentioned variables are
specifies the angle of the truck to the horizontal while the
(74)
coordinate pair specifies the position of the rear center
of the truck in the plane [0, 100] [0, 100]. The truck moves (75)
backward by some fixed distance at each step. The experiment (76)
640
Fig. 29. Trajectories of truck with the initial point (x; y; )
(10; 10; 260 ).
where the positive values of represent clockwise rotations of
the steering wheel while the negative ones represent counter-
clockwise rotations.
The performance of the fuzzy logic controller is measured
in terms of the docking error defined as the Euclidean distance
between the actual final position and the desired final
position of the truck, i.e.,
docking error
(77)
For the FLC, the input variables are the -position and the
truck angle ; the output variable is the steering angle . The
-position can be ignored because and are both the functions
of . In this example, the results acquired from the conventional
FLC with 5 7 rules and 3 3 rules are also mentioned to
demonstrate the outstanding behavior of this proposed LHFLC
[16].
Fig. 29 shows the trajectory of the truck with the initial
state . The performance factors
are listed in Table II. According to the results in Table II, the
proposed LHFLC possesses the lowest docking-error with
the smallest number of iterations. To verify the generality
of this linguistic-hedge combination, the other initial point
is also chosen to simulate this
truck backer-upper control system. The simulation results in
Fig. 30 and Table II reveal that the LHFLC still obtains the best
performance of the truck backer-upper control system. These
results again meet the claims. That is, the LHFLC possesses
the best performance.
IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003
= Fig. 30. Trajectories of truck with the initial point (x; y; ) =
(30; 20; 60 ).
3) Cart-Pole Balance System: The cart-pole balance system
is a true renowned nonlinear system, the goal of which involves
both vertically balancing a pole hinged to a motor-driven cart
and causing the cart to be stopped at the specified position by
applying forces on it either left or right. Fig. 31 represents the
cart-pole balance system, which is described by the nonlinear
differential equations (78) and (79) [48], shown at the bottom
of the page, where the related parameters are
m/s acceleration due to gravity
kg, mass of cart;
kg, mass of pole
m, half-pole length
, coefficient of friction of cart on track;
coefficient of friction of pole on cart
s, the sample time
the four state variables and the output variable are
: position of the cart on the track (in m)
: cart velocity (in m/s)
: angle of the pole with the vertical (in rad)
: rate of change of the angle (in rad/s)
: force (in N) applied to cart's center of mass
In this example, the switching-type fuzzy sliding mode
controller (FSMC) is used to control the cart-pole balance
system as the platform. The switching-type FSMC proposed by
Li [49] is a method based on FLC and SMC [50][52], which
(78)
(79)
CHEN et al.: CIRCUIT IMPLEMENTATION OF LINGUISTIC-HEDGE FUZZY LOGIC CONTROLLER 641

TABLE II
PERFORMANCE FACTORS OF TRUCK BACKER-UPPER CONTROL SYSTEM

Fig. 31. Diagram of simulated cart-pole balance system.

achieves asymptotic stability of the system. The dynamics

of the cart-pole balance system is divided into approaching
condition and departure condition. Two different FSMCs to Fig. 32. Simulation result of the cart-pole balance system with initial
solve control problems for these two conditions should be _ x; x_ ) = (0; 0; 0; 0). (Top) Response of pole angle.
conditions (; ;
designed, each characterized by the associated sliding surface (Bottom) Response of cart position.
chosen. The sliding surface of the cart-pole balance system for
the approaching mode is designed as

(80)

while that for the departure mode is chosen as

(81)

in which the error vector is defined as the

difference between the actual state vector and
the desired state vector . That is

(82)

Fig. 33. Microphotograph of this chip.

The input variables of the switching-type FSMC are and its
time derivative ; the output variable is the force applied to the
cart. In the simulation as well as the experiment, the objective
with which are concerned is to control the pole being balanced
at the position m with the angle rad.
Fig. 32 shows the response of the cart-pole balance system
controlled by the switching-type FSMC with either 5 5 or
3 3 rules and the LHFLC. Obviously, either the pole angle
response or the cart position response reveals that the LHFLC
really enhances the performance of the FLC adopting 5 5 rules
and Gauss-like membership functions or the FLC adopting 3
3 rules and triangle-like membership functions.
642
Fig. 34. Measurement result of the whole system.
B. Layout Considerations on Chip Implementation
Fig. 33 shows the microphotograph of this chip. This chip
has been designed and fabricated with a TSMC 0.35 m SPQM
CMOS process [53], [54]. The number of pads is 48 including
the power pads, analog I/O pads, digital I/O pads, and several
testing pads. The total chip area is m m where
the core part occupies an area of m m. Since
this chip is a mixed-signal design, several precautions are ap-
plied in the chip layout in order to prevent from the interference
between the portion of digital circuits and the portion of analog
circuits. With regard to the placement of cells, the digital por-
tion is placed apart from the analog portion. The analog portion
is separated from the digital portion by double guard rings. With
regard to the supply voltages, the digital portion, the digital I/O
pads, and the analog portion have individual supply voltages,
which ensures that the supply voltages for the analog portion
are clean without any interference from the digital portion or
I/O pads. With regard to the charge-injection effect, the switch
circuit is widely used in the programmable units and the cur-
rent memory cells. In order to lessen the charge-injection ef-
fects caused by this component switching between the ON and
OFF states, each of this switch is surrounded by a double guard
ring. Consider the device-mismatch problem. The variance of
the mismatch between transistors 1 and 2 of a general model
parameter, , can be represented by [43], [44], and [55].
(83)
where is the distance between transistors 1 and 2,
and are the gate areas of transistors 1 and 2, and
and are process dependent fitting constants. Generally, the
device matching can be influenced through device size, device
orientation and device proximity from the layout viewpoint. In
this work, the matched devices in the mentioned circuits were
designed at proper size rather than the minimum size and the
large mismatches between the devices due to random width
and length variation and implant shadowing were diminished.
Since component matching was also degraded by placing them
far apart, two devices intended to match as close as possible
IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003
Fig. 35. Control surface.
as placed, and the expected value of their mismatch will de-
crease. In a continuous time current-mode circuit, the current-
mirror based multiplier and divider are the primitive cells. The
matching condition of these primitive cells will have a signifi-
cant influence on the performance of the whole system. To re-
duce this influence, a method that layed out identical
devices is adopted and wired of them in parallel to achieve
an ratio for higher accuracy. For the body effect, the tran-
sistors is placed in a cascoded structure in the individual wells,
which ensures that these transistors have a zero-biased threshold
voltage.
C. Measurement Results
This chip is operated at 3.3 V supply voltage. Since the
signal processing portion is current-mode, while the avail-
able instruments for the testing job are mostly in a voltage
mode, simple off-chip grounded load voltage-to-current (V/I)
converters, the Howland current generator [56], were used to
convert the voltage signal to a corresponding current signal
suitable for the on-chip circuit. After the on-chip current-mode
signal processing, the output current signals were sent off chip
into a current-to-voltage (I/V) converter, the transresistance
amplifier, for conventional voltage-mode testing environment.
CHEN et al.: CIRCUIT IMPLEMENTATION OF LINGUISTIC-HEDGE FUZZY LOGIC CONTROLLER 643

Fig. 37. Experimental result of the cart-pole balance system.

Fig. 36. (a) Experimental setup. (b) Rule base.

The conversion ratios are 1 mV/1 A for V/I converters and

1 A/1 mV for I/V converters.
To test the entire system, the cart-pole balance control system
[57] is taken as the demonstrative example. The rule table is
shown in Fig. 36(b). The linguistic-hedge combination vectors
are

Fig. 38. Photograph of cart and pole during control with initial conditions
(84) _ x; x_ ) = (0; 0; 0; 0).
(; ;

for the fuzzy set ZE and

D. Experimental Results
To apply the proposed LHFLC to the real experimental
(85) system, the cart-pole balance system manufactured by Phimatic
Enterprise Co. Ltd. was used to demonstrate this work. The
control goal of this system involved both vertically balancing
for the fuzzy sets NB and PB, the linguistic hedge module and
a pole hinged to a motor-driven cart and causing the cart to
the inference rule base are programmed initially by loading
be stopped at the specified position by applying forces on it
the data through the 48-bit SIPO shift register and the 27-bit
either left or right. The arrangement of the whole experimental
SIPO shift register, respectively. The domain-partition currents
setup is illustrated in Fig. 36. The specifications of the related
were set as 2 A, 4 A, , 32 A, re-
hardware are listed as follows:
spectively. The current signals represent the fuzzy labels ,
, and , of all variables including the input variables and pole: 0.5 m length;
output variable were set as A, A, and drive force: dc motor (15 W);
A, respectively. The current signal was set as sensor: photo encoder (500 pulse per rotation);
16 A. The whole system is tested by setting the first input Micro-computer: 486 personal computer;
signal standing for be a ramp signal swept from 0 A to A/D, D/A, and DSP controller: MBSP card [57].
30 A. The second input signal standing for was set as a The four state variables and the output variable are
constant signal with its current increased from 0 A to 30 A : position of the cart on the track (in m);
by a step of a size equals to 2 A. Fig. 34 shows one of these : cart velocity (in m/s);
measurement results, which was measured under the condition : angle of the pole with the vertical (in rad);
of A. In this figure, the trace in the upper panel : rate of change of the angle (in rad/s);
shows the input current signal . The trace in the lower panel : force (in N) applied to carts center of mass.
shows the output current signal. Fig. 35 is the control surface The switching-type FSMC is used to control the cart-pole bal-
describing these measurement results, which is consistent with ance system [49]. The dynamics of the cart-pole balance system
the inference rule shown in Fig. 36(b). were divided into approaching condition and departure condi-
644
TABLE III
HARDWARE OVERHEAD COMPARISONS
tion. The sliding surface of the cart-pole balance system for the
approaching mode was designed as
(86)
while that for the departure mode was chosen as
(87)
in which the error vector was defined as the
difference between the actual state vector and
the desired state vector . The input vari-
ables of the switching-type FSMC were and its time derivative
. The output variable was the force applied to the cart. The
pole being balanced at the position m with the angle
rad is controlled in the experiment. Fig. 36(b) shows the
rule table for this system, which has a dimension of only 3
3. Each input variable was defined by three fuzzy sets with tri-
angle-like membership functions distributed over the intervals
and , respectively. The output
variable was defined by three fuzzy singletons distributed over
the interval . In this study, current-mode circuits such as the fuzzifier
Initially, the interface between the LHFLC chip and the
MBSP card was specified in C language run by a personal
computer used only to acquire and deliver the data between the
MBSP card and the interface card before the LHFLC chip. All
of the data in the programmable units were serially shifted into
the corresponding SIPO registers to set up the corresponding
switches prior to starting the inferencing operation. First, the
state of the cart-pole balance system is sensed by a photo
encoder and fed back to the A/D converter of the MBSP card.
The personal computer fetches these signals and delivers them
to LHFLC chip through the interface card. After the LHFLC
chip processing, the personal computer fetches the inferencing
signal and sends it to the DSP controller of the MBSP card
through the 25-pin RS-232 transmission line. The DSP con-
troller processes the received signals to produce the control
IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003
actions. These control actions are delivered to a dc motor via
the D/A converter in order to apply the suitable force to the
cart. The state of the cart-pole balance system is sensed by a
photo encoder and fed back to the A/D converter of the MBSP
card. This routine is run continuously until the system demand
is met. The responses of the pole angle and the cart position
are recorded by computer and plotted in Fig. 37. Fig. 38 shows
a photograph of the cart-pole balance system controlled by the
resultant LHFLC with an exposure of about 10 s.
E. Hardware Overhead Comparisons
Combining the linguistic-hedge concept with a conventional
FLC leads to the compactness of inference rules. The conven-
tional FLCs and the proposed LHFLC from the hardware real-
ization viewpoints are considered to tabulate the differences in
Table III.
VI. CONCLUSION
circuit, a set of linguistic-hedge circuits, minimum current
selector circuit, maximum current selector, and defuzzifier
circuit, were integrated with programmable units to implement
a mixed-signal VLSI design of LHFLC. Taking advantage of
the inherent characteristics in LHFLC, a smaller hardware
overhead was required in the fuzzification unit, the inference
unit, the defuzzification unit and the rule storage elements as
compared with the controllers needing more than nine rules.
This LHFLC operated at 3.3-V supply voltage with an opera-
tion speed of 0.5M FLIPS. The programmable linguistic-hedge
module and the programmable rule-base cause this system to
have a good flexibility. This chip has been successfully applied
to control the cart-pole balance system. By performing some
proper signal scaling works, this design is applicable to many
real world fuzzy logic control applications. In the future, the
CHEN et al.: CIRCUIT IMPLEMENTATION OF LINGUISTIC-HEDGE FUZZY LOGIC CONTROLLER
A/D converters, D/A converters, and other signal processing
units can be integrated with this design such that it will be more
suitable for specific applications.
REFERENCES
[1] L. A. Zadeh, Fuzzy sets, Inform. Control, vol. 8, pp. 338353, 1965.
[2] P. J. King and E. H. Mandani, The application of fuzzy control systems
to industrial processes, Automatica, vol. 13, no. 3, pp. 235242, 1977.
[3] S. K. Pal, R. A. King, and A. A. Hashim, Image description and prim-
itive extraction using fuzzy set, IEEE Trans. Syst., Man., Cybern., vol.
SMC-13, pp. 94100, Jan. 1983.
[4] M. Sugen and K. Murakami, Fuzzy parking control of model car, in
Proc. 23rd IEEE Conf. Decision Control, Las Vegas, NV, Dec. 1984, pp.
902903.
[5] O. Itoh, K. Gotoh, T. Nakayama, and S. Takamizawa, Application of
fuzzy control to activated sludge process, in Proc. 2nd Int. Fuzzy Syst.
Association Congr., Tokyo, Japan, July 1987, pp. 282285.
[6] C. C. Lee, Fuzzy logic in control systems: Fuzzy logic controllerPart
I, II, IEEE Trans. Syst., Man, Cybern., vol. 20, pp. 404432, Mar./Apr.
1990.
[7] H. J. Zimmermann, Fuzzy Set Theory and Its Applications, 2nd
ed. Norwell, MA: Kluwer, 1991.
[8] D. G. Schwartz and G. J. Klir, Fuzzy logic flowers in Japan, IEEE
Spectrum, vol. 29, pp. 3235, July 1992.
[9] J. H. Holland, Adaptation in Natural and Artificial Systems. Ann
Arbor, MI: Univ. Michigan Press, 1975.
[10] D. E. Goldberg, Genetic Algorithms in Search, Optimization and Ma-
chine Learning. Reading, MA: Addison-Wesley, 1989.
[11] L. A. Zadeh, Outline of a new approach to the analysis of complex
systems and decision processes, IEEE Trans. Syst., Man, Cybern., vol.
SMC-3, pp. 2844, Jan. 1973.
[12] C. Y. Huang, C. Y. Chen, and B. D. Liu, Current-mode linguistic hedge
circuit for adaptive fuzzy logic controllers, Electron. Lett., vol. 31, no.
17, pp. 15171518, Aug. 1995.
[13] C. Y. Chen, C. Y. Huang, and B. D. Liu, Current-mode fuzzy linguistic
hedge circuitcontrast intensification, in Proc. IEEE Int. Symp. Cir-
cuit Syst., vol. 3, Atlanta, GA, May 1996, pp. 511513.
[14] C. Y. Chen, C. Y. Huang, B. D. Liu, and T. J. Su, A current-mode fuzzy
linguistic hedge circuitmore or less, in Proc. IEEE 5th Int. Conf.
Fuzzy Syst., New Orleans, LA, Sept. 1996, pp. 10801085.
[15] C. Y. Huang, C. Y. Chen, and B. D. Liu, Current-mode fuzzy linguistic
hedge circuits, Analog Integr. Circuits Signal Processing, vol. 19, no.
3, pp. 255278, June 1999.
[16] B. D. Liu, C. Y. Chen, and J. Y. Tsao, Design of adaptive fuzzy logic
controller based on linguistic-hedge concepts and genetic algorithms,
IEEE Trans. Syst., Man, Cybern. B., vol. 31, pp. 3253, Feb. 2001.
[17] T. Yamakawa and T. Miki, Implementation of fuzzy logic hardware sys-
temsThree fundamental arithmetic circuits, Trans. IEICE, vol. 63-C,
no. 10, pp. 720721, Oct. 1980.
[18] T. Yamakawa, Y. Shirai, T. Inoue, and F. Ueno, Construction of a
programmable multifunction voltage mode fuzzy logic circuit, Trans.
IEICE, vol. 63-C, no. 10, pp. 724725, Oct. 1980.
[19] , Implementation of fuzzy logic (complement, bounded difference,
bounded sum, and absolute difference) by current mode circuits, Trans.
IEICE, vol. 63-C, no. 10, pp. 722723, Oct. 1980.
[20] , Implementation of fuzzy logics and a programmable multifunc-
tion circuit with current mode, Trans. IEICE, vol. 64-C, no. 2, pp.
147148, Feb. 1981.
[21] T. Yamakawa and T. Miki, The current mode fuzzy logic integrated cir-
cuits fabricated by the standard CMOS process, IEEE Trans. Comput.,
vol. C-35, pp. 161167, Feb. 1986.
[22] B. D. Liu and C. Y. Huang, Array based fuzzy inference mechanism im-
plemented with current-mode CMOS circuits, in Proc. IEEE Int. Symp.
Circuits Syst., London, U.K., May 1994, pp. 537540.
[23] M. Sasaki, T. Inoue, Y. Shirai, and F. Ueno, Fuzzy multiple-input
maximum and minimum circuits in current mode and their analyzes
using bounded-difference equations, IEEE Trans. Comput., vol. 39,
pp. 768774, June 1990.
[24] V. Catania, A. Puliafito, M. Russo, and L. Vita, A VLSI fuzzy inference
processor based on a discrete analog approach, IEEE Trans. Fuzzy Syst.,
vol. 2, pp. 93106, May 1994.
[25] L. Lemaitre, M. J. Patyra, and D. Mlynek, Analysis and design of
CMOS fuzzy controller in current mode, IEEE J. Solid State Circuits,
vol. 29, pp. 317322, Mar. 1994.
645
[26] M. Togai and H. Watanabe, Expert system on a chip: An engine for
real-time approximate reasoning, IEEE Expert, pp. 5562, 1986.
[27] H. Watanabe, W. D. Dettloff, and K. E. Yount, A VLSI fuzzy logic
controller with reconfigurable, cascadable architecture, IEEE J. Solid
State Circuits, vol. 25, pp. 376382, Apr. 1990.
[28] T. C. Chiueh, Optimization of fuzzy logic inferene architecture, IEEE
Trans. Comput., vol. 25, pp. 6771, May 1992.
[29] D. Kim, An implementation of fuzzy logic controller on the recon-
figurable FPGA systems, IEEE Trans. Ind. Electron., vol. 47, pp.
703715, June 2000.
[30] J. W. Fattaruso, S. S. Mahant-Shetti, and J. B. Barton, A fuzzy logic
inference processor, IEEE J. Solid State Circuits, vol. 29, pp. 397402,
Apr. 1994.
[31] E. H. Mamdani, Application of fuzzy logic to approximate reasoning
using linguistic synthesis, IEEE Trans. Comput., vol. C-26, no. 12, pp.
11821191, Dec. 1977.
[32] K. A. De Jong, An analysis of the behavior of a class of genetic adaptive
systems, Ph.D. dissertation, Dept. Comput. Sci., Univ. Michigan, Ann
Arbor, MI, 1975.
[33] E. Seevinck and R. J. Wiegerink, Generalized translinear circuit prin-
ciple, IEEE J. Solid State Circuits, vol. 26, pp. 10981102, Aug. 1991.
[34] K. Bult and H. Wallinga, A class of analog CMOS circuits based on
the square-law characteristic of an MOS transistor in saturation, IEEE
J. Solid State Circuits, vol. SC-22, pp. 357364, June 1987.
[35] C. Y. Huang, C. J. Wang, and B. D. Liu, Modular current-mode multiple
minimum circuit for fuzzy logic controllers, Electron. Lett., vol. 32, no.
12, pp. 10671068, June 1996.
[36] C. Y. Huang and B. D. Liu, Current-mode multiple input maximum
circuit for fuzzy logic controllers, Electron. Lett., vol. 30, no. 23, pp.
19241925, Nov. 1994.
[37] J. Lazzaro, S. Ryckebush, M. A. Mahowald, and C. A. Mead, Winner-
take-all network of O(N ) complexity, in Advances in Neural Infor-
mation Processing Systems. Los Altos, CA: Morgan Kaufmann, 1989,
vol. 1, pp. 703711.
[38] C. Toumazou, J. B. Hughes, and D. M. Pattullo, Regulated cascode
switched-current memory cell, Electron. Lett., vol. 26, no. 5, pp.
303305, 1990.
[39] R. J. Wiegerink, Analysis and Synthesis of MOS Translinear Cir-
cuits. Boston, MA: Kluwer, 1993.
[40] C. Y. Chen, C. Y. Huang, and B. D. Liu, Current-mode defuzzifier cir-
cuit to realize the centroid strategy, in Proc. 1997 IEEE Int. Symp. Cir-
cuit Systems, Hong Kong, June 1997, pp. 609612.
[41] , Current-mode defuzzifier circuit to realize the centroid strategy,
Proc. Inst. Elect. Eng.Circuits Devices Systems, vol. 144, no. 5, pp.
265271, Oct. 1997.
[42] R. S. Muller and T. I. Kamins, Devices Electronics for Integrated Cir-
cuits. New York: Wiley, 1977.
[43] K. R. Lakshmikuman, R. A. Hadaway, and M. A. Copeland, Charac-
terization and modeling of mismatch in MOS transistors for precision
analog design, IEEE J. Solid State Circuits, vol. SC-21, pp. 10571066,
Dec. 1986.
[44] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, Matching
properties of MOS transistors, IEEE J. Solid State Circuits, vol. SC-24,
pp. 14331440, Oct. 1989.
[45] MATLAB, Matrix Laboratory. Natwick, MA: The Math Works, Inc.,
1992.
[46] C. C. Ku and K. Y. Lee, Diagonal recurrent neural networks for
dynamic systems control, IEEE Trans. Neural Networks, vol. 6, pp.
144156, Jan. 1995.
[47] B. Kosko, Neural Networks and Fuzzy Systems. Upper Saddle River,
NJ: Prentice-Hall, 1992.
[48] P. H. Cannon, Dynamics of Physical Systems. New York: McGraw-
Hill, 1967.
[49] T. S. Li and C. Y. Tsai, Parallel fuzzy sliding mode control of the
cart-pole system, in Proc. IEEE IECON95, Orlando, FL, Nov. 1995,
pp. 14681473.
[50] J. E. Slotine, Applied Nonlinear Control. Upper Saddle River, NJ:
Prentice-Hall, 1991.
[51] J. Y. Hung, G. Senior, and J. C. Hung, Variable structure control: A
survey, IEEE Trans. Ind. Electron., vol. 40, pp. 222, Feb. 1993.
[52] W. Gao and J. C. Hung, Variable structure control of nonlinear systems:
A new approach, IEEE Trans. Ind. Electron., vol. 40, no. 1, pp. 4555,
Feb. 1993.
[53] TSMC 0.35 m Logic Silicide (SPQM, 3.3 V) SPICE Models. Hsinchu,
Taiwan: Taiwan Semiconductor Manufacturing Co., Ltd., 1998.
[54] TSMC 0.35 m Logic Silicide 3.3 V Design Rule. Hsinchu, Taiwan:
Taiwan Semiconductor Manufacturing Co., Ltd., 1998.
646
[55] J. B. Shyu, G. C. Temes, and F. Krummenacher, Random error effects
in matched MOS capacitors and current sources, IEEE J. Solid State
Circuits, vol. SC-19, pp. 948955, Dec. 1984.
[56] S. Franco, Design with Operational Amplifiers and Analog Integrated
Circuits. New York: McGraw-Hill, 1988, pp. 5863.
[57] J. C. Hung, MBSP Manual. Hsinchu, Taiwan, R.O.C.: Phimatic Enter-
prise Co., Ltd., 1995.
Chuen-Yau Chen (S00M02) received the B.S. National Cheng Kung University. He was the Associate Chairman of the
and Ph.D. degrees in electrical engineering from
National Cheng Kung University (NCKU), Tainan,
Taiwan, R.O.C., in 1995 and 2001, respectively.
From 1999 to 2000, he was the System Ad-
ministrator of the VLSI/CAD Laboratory at the
Department of Electrical Engineering, NCKU. From
July 2001 to July 2003, he was with the Department
of Electronic Engineering, I-Shou University,
Kaohsiung, Taiwan, R.O.C. He is currently an As-
sistant Professor with the Department of Electrical
Engineering, National Yunlin University of Science and Technology, Taiwan,
R.O.C. His current research interests are physical design and testing for VLSI
circuits, SoC system integration and verification, design and VLSI implemen-
tation for fuzzy logic controller and CORDIC algorithm, current-mode and
mixed-signal circuits, and system designs.
Dr. Chen is a Member of Phi Tau Phi Honorary Scholastic Society, Taiwan
Integrated Circuit Design Society, Digital IP Consortium, and Advanced Tech-
nology ConsortiumVLSI Educational Program of Ministry of Education. He
served as a Member of the Technical Program Committee of the R.O.C. VLSI
Design/CAD Symposium in 2002. He will be the Finance Chair of the 2004
IEEE Asia-Pacific Conference on Circuits and Systems.
Yuan-Ta Hsieh received the B.S. and M.S. degrees
in electrical engineering from National Cheng Kung
University, Tainan, Taiwan, R.O.C., in 1998 and
2000, respectively.
In 2000, he joined the Chip Implementation Center
of National Applied Research Laboratories, where he
is an Associate Researcher of the Chip Implemen-
tation Service division. His current research is ESD
protection circuits design for ultra-deep submicron
process.
IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003
Bin-Da Liu (S79M82SM95) received the
B.S., M.S., and Ph.D. degrees, all in electrical engi-
neering, from the National Cheng Kung University,
Tainan, Taiwan, R.O.C., in 1973, 1975, and 1983,
respectively.
From 1975 to 1977, he served as Electrical Officer
in the Combined Service Forces. Since 1977, he has
been on the Faculty of the National Cheng Kung
University, where he is currently a Professor in
the Department of Electrical Engineering. During
19831984, he was a Visiting Assistant Professor in
the Department of Computer Science, University of Illinois at Urbana-Cham-
paign. During 19881992, he was the Director of Electrical Laboratories,
Electrical Engineering Department during 19961999 and the Chairman
during 19992002. From 1990 to 1993, he was a Member of the Evaluation
Committee for Junior Engineering College, Ministry of Education. Since 1995,
he has been a consultant of the Chip Implementation Center, National Science
Council. Since 2002 he has been the Coordinator of the Digital IP Consortium,
VLSI Educational Program of Ministry of Education and the Coordinator
of the SoC Design Promotion Program of National Science Council. He
has published more than 170 technical papers. He also contributed chapters
in Neural Networks and Systolic Array Design (D. Zhang, Ed. Singapore:
World Scientific, 2002) and Trade-Off Between Accuracy and Interpretability
in Fuzzy Rule-Based Modeling (J. Casillas, O. Cordon, F. Herrera, and
L. Magdalena, Eds. Heidelberg, Germany: Springer-Verlag, 2003). His current
research interests include physical design and testing for VLSI circuits, SoC
system integration and verification, and VLSI implementation for fuzzy-neural
networks and video signal processors.
Dr. Liu is a Member of Phi Tau Phi, Taiwan SOC Consortium, International
Union of Radio Science, Chinese Fuzzy Systems Association, Chinese Institute
of Electrical Engineers, and Taiwan Integrated Circuit Design Society. He has
been the Chairman of IEEE Circuits and Systems SocietyTaipei Chapter since
2002. He received Dragon Distinguished Paper Award from the Acer Founda-
tion in 1991 and 1997, the Best Paper Award from the CIEE in 1995 and 2002,
the Golden Silicon Award from the Macronix Foundation in 2001 and 2002,
MPC Chip Design Award from the CIC in 2002, the International Low Power
Design Contest Award from ACM in 2003, and the Research Award from the
National Science Council annually since 1988. He organized the Taiwan Stu-
dent VLSI Design Contest in 1998, 1999, and 2000. Since 1992, he has served
as a Member of the Steering Committee of VLSI Design/ CAD Symposium and
served as the General Chair in 1994. Since 1997, he has served as a member
of the Technical Program Committee of R.O.C. National Conference on Fuzzy
Theory and Its Applications. He served as a Member of the Program Committee
of the 1998 and 1999 IEEE Workshop on VLSI Signal Processing Systems.
He also served as a Member of the Technical Program Committee of the 1998
and 2000 IEEE Asia Pacific Conference on Circuits and Systems, and the First,
Second, and Third IEEE Asia Pacific Conference on ASICs. He has been a
Member of the International Steering Committee of the IEEE Asia-Pacific Con-
ference on Circuits and Systems since 2001. He will be the General Chair of the
2004 IEEE Asia-Pacific Conference on Circuits and Systems.