Determine the output frequency for a frequency division circuit that contains 12 flip-flops with
an input clock frequency of 20.48 MHz.
A. 10.24 kHz
B. 5 kHz
C. 30.24 kHz
D. 15 kHz
Answer: Option B
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B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
B. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1
Answer: Option D
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B. 2
C. 4
D. 8
Answer: Option C
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B. 4
C. 6
D. 7
Answer: Option D
B. ena
C. clr
D. prn
Answer: Option C
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8. The timing network that sets the output frequency of a 555 astable circuit contains ________.
A. three external resistors are used
10. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH
is called ________.
A. parity error checking
B. ones catching
C. digital discrimination
D. digital filtering
Answer: Option B
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B. Multivibrator
C. Bistable
D. Astable
Answer: Option A
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B. astable oscillator
14. What is the difference between the 7476 and the 74LS76?
A. the 7476 is master-slave, the 74LS76 is master-slave
19. Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown
below. Determine if the circuit is functioning properly, and if not, what might be wrong.
A. The circuit is functioning properly.
C. The input to flip-flop 3 (D2) is probably wrong; check the source of D2.
D. A bad connection probably exists between FF-3 and FF-4, causing FF-3 not to reset.
Answer: Option B
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B. 18 F
C. 18 pF
D. 18 nF
Answer: Option A
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21. Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input
data is read during the entire time the clock pulse is at a LOW level.
A. True
B. False
Answer: Option B
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B. J = 1, K = 0
C. J = 0, K = 1
D. J = 0, K = 0
Answer: Option D
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24. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while
the:
A. clock is LOW
B. slave is transferring
C. flip-flop is reset
D. clock is HIGH
Answer: Option D
The input is toggled into the flip-flop on the leading edge of the clock and is passed to
D.
the output on the trailing edge of the clock.
Answer: Option B
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26. What does the triangle on the clock input of a J-K flip-flop mean?
A. level enabled
B. edge-triggered
Answer: Option B
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27. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
A. constantly LOW
B. constantly HIGH
28.
The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their
________ state(s) at the ________.
A. opposite, active clock edge
29. An RC circuit used in a nonretriggerable 74121 one-shot has an REXT of 49 k and a CEXT of
0.2 F. The pulse width (tW) is approximately ________.
A. 6.9 s
B. 6.9 ms
C. 69 ms
D. 690 ms
Answer: Option B
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30. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
________.
A. the clock pulse is LOW
B. no active S or R input
C. only S is active
D. only R is active
Answer: Option B
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32. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R
input goes to 0, the latch will be ________.
A. SET
B. RESET
C. clear
D. invalid
Answer: Option B
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B. 3
C. 4
D. 5
Answer: Option D
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34. A 555 operating as a monostable multivibrator has a C1 = 0.01 F. Determine R1 for a pulse
width of 2 ms.
A. 200 k
B. 182 k
C. 91 k
D. 182
Answer: Option B
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35. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions
will cause it to change states?
A. CLK = NGT, D = 0
B. CLK = PGT, D = 0
C. CLOCK NGT, D = 1
D. CLOCK PGT, D = 1
C. triggering can take place anytime during the HIGH level of the CLK waveform
D. triggering can take place anytime during the LOW level of the CLK waveform
Answer: Option A
37. In a 555 timer, three 5 k resistors provide a trigger level of ________.
A. 1/4 VCC and a threshold level 1/2 VCC
38. Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?
A. active-HIGH
B. active-LOW
Answer: Option A
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39. The circuit that is primarily responsible for certain flip-flops to be designated as edge-
triggered is the:
A. edge-detection circuit.
B. NOR latch.
C. NAND latch.
D. pulse-steering circuit.
Answer: Option A
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40. With four J-K flip-flops wired as an asynchronous counter, the first output change of divider
#4 indicates a count of how many input clock pulses?
A. 16
B. 8
C. 4
D. 2
Answer: Option B
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41. What is the significance of the J and K terminals on the J-K flip-flop?
A. There is no known significance in their designations.
The J represents "jump," which is how the Q output reacts whenever the clock goes
B.
high and the J input is also HIGH.
C. The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
42. Why are the S and R inputs of a gated flip-flop said to be synchronous?
A. They must occur with the gate.
B. False
Answer: Option B
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D. Set up time
Answer: Option C
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45. An RC circuit used in a 74122 retriggerable one-shot has an REXT of 100 k and a CEXT of
0.005 F. The pulse width is ________.
A. 70 s
B. 16 s
C. 160 s
D. 32 s
Answer: Option C
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B. 17 pF
C. 170 pF
D. 1,700 F
Answer: Option A
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48. What is one disadvantage of an S-R flip-flop?
A. It has no enable input.
B. 4
C. 8
D. 16
Answer: Option D
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51. Which of the following best describes the action of pulse-triggered FF's?
A. The clock and the S-R inputs must be pulse shaped.
The data is entered on the leading edge of the clock, and transferred out on the
B.
trailing edge of the clock.
52. An invalid condition in the operation of an active-HIGH input S-R latch occurs when
________.
A. HIGHs are applied simultaneously to both inputs S and R
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1
Answer: Option A
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54. The output pulse width for a 555 monostable circuit with R1 = 3.3 k and C1 = 0.02 F is
________.
A. 7.3 s
B. 73 s
C. 7.3 ms
D. 73 ms
Answer: Option B
55. Edge-triggered flip-flops must have:
A. very fast response times.
56. As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:
A. very long.
B. very short.
D. of no consequence as long as the levels are within the determinate range of value.
Answer: Option B
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B. the D input is HIGH and the clock transitions from LOW to HIGH
B. toggle triggered
C. clock triggered
D. noise triggered
Answer: Option A
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59. A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when
the circuit is operated it produces erratic results. Close examination with a scope reveals the
presence of glitches. What causes the glitches, and how might the problem be corrected?
The PRESET and CLEAR terminals may have been left floating; they should be
A.
properly terminated if not being used.
The problem is caused by a race condition between the J and K inputs; an inverter
B.
should be inserted in one of the terminals to correct the problem.
A race condition exists between the Q and Q outputs to the AND gate; the AND gate
C.
should be replaced with a NAND gate.
A race condition exists between the clock and the outputs of the flip-flop feeding the
D.
AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.
Answer: Option D
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60. A 555 operating as a monostable multivibrator has a C1 = 100 F. Determine R1 for a pulse
width of 500 ms.
A. 45
B. 455
C. 4.5 k
D. 455 k
Answer: Option C
61. Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock
input.
A. True
B. False
Answer: Option B
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Using higher levels of abstraction and tailoring components to exactly fit the needs of
D.
the project
Answer: Option C
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63. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After
four input clock pulses, the binary count is ________.
A. 00
B. 11
C. 01
D. 10
Answer: Option A
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64. Latches constructed with NOR and NAND gates tend to remain in the latched condition due
to which configuration feature?
A. cross coupling
B. gate impedance
D. asynchronous operation
Answer: Option A
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C. flip-flop is reset
B. Library
C. Entity
D. Port map
Answer: Option A
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68. A gated S-R latch and its associated waveforms are shown below. What, if anything, is
wrong and what could be causing the problem?
B. The Q output should be the complement of the output; the S and R terminals are
reversed.
69. The output pulse width of a 555 monostable circuit with R1 = 4.7 k and C1 = 47 F is
________.
A. 24 s
B. 24 ms
C. 243 ms
D. 243 s
Answer: Option C
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70. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?
A. An invalid state will exist.
A. There is no problem.
72. A push-button switch is used to input data to a register. The output of the register is erratic.
What could be causing the problem?
A. The power supply is probably noisy.
B. two resistors
C. two capacitors
C. LOW
D. HIGH
Answer: Option D
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76. An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is
the latch in?
A.
B.
C.
D.
Answer: Option A
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77. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
A. No change will occur in the output.
78. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to
the first flip-flop is 32 kHz, the output frequency (fout) is ________.
A. 1 kHz
B. 2 kHz
C. 4 kHz
D. 16 kHz
Answer: Option B