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Revised copy No.

Table of contents:

Sr. Page
Contents No.
No.

A To write VHDL code, simulate with test bench, synthesis, implement on PLD

1 4 bit ALU for add, subtract, AND, NAND, XOR, XNOR, OR, & ALU 2
pass.

2 Universal shift register with mode selection input for SISO, SIPO, 5
PISO, & PIPO modes

3 FIFO memory 8

4 LCD interface 11

B To prepare CMOS layout in selected technology, simulate with and without


capacitive load, comment on rise, and fall time

5 Inverter, NAND, NOR gates, and Half Adder 15

6 2:1 multiplexer using logic gates and transmission gates 27

7 Single bit SRAM cell 30

8 D flip-flop 33

Reviewed by Approved by

Mr. K. J. Raut Dr. P. D. Khandekar


Course Coordinator H. O. D. (E&TC)

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Revised copy No. 2

EXPERIMENT NO: 01

TITLE OF EXPERIMENT : Design and Implementation of 4 bit ALU using


VHDL on PLD

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1.1 Aim: To write VHDL code for a 4 bit ALU to add, subtract, AND, NAND, XOR,
XNOR, OR, & ALU pass .Verify the result using FPGA board. Also write the Test
bench and verify by simulation.

1.2 Hardware/Software:
1. Computer with Xilinx software.
2. FPGA board with JTAG cable.

1.3 Procedure:
1. Write a VHDL code for 4 bit ALU.
2. Verify the functional simulation for the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA and verify the operation.
5. Observe the RTL schematic for the code.

1.4 A. Diagram of ALU:

Input A(3:0)

Input B(3:0)

4 bit ALU Result (3:0)

Overflow for carry or


Select Lines (2:0)
(So-S2) for mode borrow
selection

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1.5 Results:
1. Operation of ALU is verified on FPGA board as well as by simulation.
2. The FPGA LUTs utilized for ALU is ______out of _______.
3. Attach prints of design code, test bench code, simulation results, RTL schematic,
synthesis report, and ucf file.

1.6 Conclusion:
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
_____________________________________________________________________

1.7 Answer the following Questions:


1. What are the different modeling styles in VHDL?
2. What are different data types in VHDL?
3. What is the difference between STD_LOGIC and BIT?
4. Explain different attributes in VHDL. State examples.
5. Explain delay types in VHDL.

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EXPERIMENT NO: 02

TITLE OF EXPERIMENT : Design and Implementation of Universal Shift


Register using VHDL on PLD

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2.1 Aim: To write a VHDL code for Universal shift register with mode selection input
for SISO, SIPO, PISO, & PIPO modes. Write its test bench and verify the result using
FPGA board.

2.2 Hardware/Software:
1. Computer with Xilinx software.
2. FPGA board with JTAG cable.

2.3 Procedure:
1. Write a VHDL code for Universal Shift Register by any one modeling style.
2. Verify the functional simulation of the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA and verify the operation.
5. Generate the RTL schematic for each modeling style.

2.4 Diagram of Universal Shift Register:

SIN Pout (3:0)


Parallee
CLK
4 bit SOUT
LOAD
Universal
Shift
Pin(3:0)
Parallee register
Mode(1:0)
Parallee

2.5 Truth Table:


Load Mode Operation

X 00 PIPO

1 01 PISO

1 10 SIPO

X 11 SISO

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2.6 Results:
1. Operation of Universal Shift register is verified on FPGA board.
2. The FPGAs LUTs utilized for Universal Shift Register is _____out of ________.
3. Attach prints of design code, test bench code, simulation results, RTL schematic,
synthesis report, and ucf file.

2.7 Conclusion:
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________

2.8 Answer the following Questions:

1. Compare functions and procedures in VHDL.


2. What is configuration in VHDL?
3. State synthesizable and non-synthesizable statements.
4. What is test bench?
5. State two sequential and concurrent statements in VHDL.

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EXPERIMENT NO: 03

TITLE OF EXPERIMENT : Design and Implementation of FIFO Memory


using VHDL on PLD

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3.1 Aim: To write VHDL code for of FIFO Memory and write its test bench and verify
the result using FPGA board.

3.2 Hardware/Software:
1. Computer with Xilinx software.
2. FPGA board with JTAG cable.

3.3 Procedure:
1. Write a VHDL code for FIFO memory.
2. Verify the functional simulation for the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA and verify the operation.
5. Observe the RTL schematic for the code.

3.4 Diagram of FIFO Memory

Datain (3:0) Dataout (3:0)


ee ee

Clk
Empty
FIFO
rw Memory
(23 X 4) Full
rst

3.4 Results:
1. Operation of FIFO Memory is verified on FPGA board.
2. The FPGA LUTs utilized for FIFO Memory is _____out of ________.
3. Attach prints of design code, test bench code, simulation results, RTL schematic,
synthesis report, and ucf file.

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3.5 Conclusion:
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________

3.6 Answer the following Questions:


1. What is the difference between RAM and FIFO?
2. What are the different types of FSM? List FSM encoding techniques.
3. What is operator overloading?
4. What is resolution function?
5. What are the names of Xilinx synthesis tool and simulation tool?

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EXPERIMENT NO: 04

TITLE OF EXPERIMENT : Design and Interfacing of LCD With FPGA

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4.1 Aim: To write a VHDL code to interface LCD with FPGA, verify the functionality
by simulation, and implement using CPLD.

4.2 Hardware/Software:

1. Computer with Xilinx software


2. CPLD board with JTAG cable.
3. LCD module.

4.3 Procedure:

1. Write a VHDL code for interfacing LCD and display text.


2. Verify the functionality by simulation.
3. Download bit file on CPLD and verify the operation.
4. Observe the transmitted text on LCD.

4.4 Interfacing Diagram:

Data (7:0)
ee

Clk
RS
CPLD LCD
rst
XC9572pc84 16x2
-15 EN characters

Gnd RW

Gnd Vcc

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4.5 LCD Command Table

4.6 ASCII Code Table

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4.7 Results:
1. Functionality of LCD interface is verified by simulation and design is implemented
using CPLD board.
2. The macrocells utilized for LCD interfacing is _____out of ________.
3. Attach prints of design code, test bench code, simulation results, RTL schematic,
synthesis report, and ucf file.

4.7 Conclusion:
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________

4.8 Answer the following Questions:


1. Compare CPLD with respect to FPGA.
2. State names of two families of CPLDs and FPGAs.
3. What is UCF?
4. State programming modes of FPGAs.
5. What is the basic building block of FPGA?

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EXPERIMENT NO: 05 A

TITLE OF EXPERIMENT : Design of CMOS Inverter Layout and


Simulation

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5.1 Aim: Design CMOS Inverter Layout and verify the functionality by simulation.

5.2 Software: Microwind 3.0

5.3 Procedure:

Prepare the layout for CMOS inverter with WP=3.2Wn and perform functional
simulation with and without capacitive load.

Comment on the effect of no load and capacitive load on rise time and fall time.

5.4 Specifications:

Technology: 0.18um
Supply voltage: 2.0V

5.5 Circuit Diagram:

5.6 Layout Diagram:

Attach print of layout.

5.7 Simulation Results:

Attach prints of following results:


i) Transient analysis result without load.
ii) Transient analysis result with capacitive load.
iii) DC transfer characteristic.

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5.8 Conclusion:

Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________

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Revised copy No. 2

EXPERIMENT NO: 05 B

TITLE OF EXPERIMENT : Design of CMOS NAND Gate Layout and


Simulation

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5.1 Aim: Design CMOS NAND gate Layout and verify the functionality by simulation.

5.2 Software: Microwind 3.0

5.2 Procedure:

Prepare the layout for CMOS NAND gate and perform functional simulation with and
without capacitive load.
Comment on the effect of no load and capacitive load on rise time and fall time.

5.3 Specifications:

Technology: 0.18um
Supply voltage: 2.0V

5.4 Circuit Diagram:

5.6 Layout Diagram:

Attach print of layout.

5.7 Simulation Results:

Attach prints of following results:


i) Transient analysis result without load.
ii) Transient analysis result with capacitive load.
iii) DC transfer characteristic.

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5.8 Conclusion:

Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________

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Revised copy No. 2

EXPERIMENT NO: 05 C

TITLE OF EXPERIMENT : Design of CMOS NOR Gate Layout and verify


the functionality by simulation

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5.1 Aim: Design CMOS NOR gate Layout and verify the functionality by simulation.

5.2 Software: Microwind 3.0

5.3 Procedure:
Prepare the layout for CMOS NOR gate and perform functional simulation with and
without capacitive load.

Comment on the effect of no load and capacitive load on rise time and fall time.

5.4 Specifications:

Technology: 0.18um
Supply voltage: 2.0V

5.5 Circuit Diagram:

5.6 Layout Diagram:

Attach print of layout.

5.7 Simulation Results:

Attach prints of following results:


i) Transient analysis result without load.
ii) Transient analysis result with capacitive load.
iii) DC transfer characteristic.

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5.8 Conclusion:

Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________

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EXPERIMENT NO: 05 D

TITLE OF EXPERIMENT : Design of CMOS Half Adder Layout and verify


the functionality by simulation

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5.1 Aim: Design CMOS Half Adder Layout and verify the functionality by simulation.

5.2 Software: Microwind 3.0

5.3 Procedure:

Prepare the layout for CMOS Half Adder and perform functional simulation with and
without capacitive load.

Comment on the effect of no load and capacitive load on rise time and fall time.

5.4 Specifications:

Technology: 0.18um and Supply voltage: 2.0V

5.5 CMOS Circuit Diagram:

Sum = A . B_bar + A_bar . B and Carry = A . B

5.6 Gate-level Circuit Diagram:

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5.7 Layout Diagram:

Attach print of layout.

5.8 Simulation Results:

Attach prints of following results:


i) Transient analysis result without load.
ii) Transient analysis result with capacitive load.
iii) DC transfer characteristic.

5.9 Conclusion:

Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________

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Revised copy No. 2

EXPERIMENT NO: 6

TITLE OF EXPERIMENT: Design of CMOS 2:1 Multiplexer layout using


logic gates and transmission gates and verify
the functionality by simulation

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6.1 Aim: CMOS 2:1 Multiplexer layout design using logic gates and transmission gates
and verify the functionality by simulation

6.2 Software: Microwind 3.0

6.3 Procedure:

Prepare the layout for 2:1 multiplexer using transmission gates and logic gates. Do the
functional simulation and verify the results.
Comment on the effect of no load and capacitive load on rise time and fall time.

6.4 Specifications:

Technology: 0.18um
Supply voltage: 2.0V

6.5 Circuit diagram using logic gates:

6.6 Circuit diagram using transmission gates:

D0
S Y
D1

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6.7 Layout Diagram:

Attach print of layout.

6.8 Simulation Results:

Attach prints of following results:


i) Transient analysis result without load.
ii) Transient analysis result with capacitive load.
iii) DC transfer characteristic.

6.9 Conclusion:

Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________

6.10 Answer the following Questions:


1. State different masks required to fabricate CMOS layout.
2. State advantages and disadvantages of transmission gate.

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EXPERIMENT NO: 7

TITLE OF EXPERIMENT: Design of CMOS single bit SRAM cell layout


and verify the functionality by simulation

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7.1 Aim: Design of CMOS single bit SRAM cell layout and verify the functionality by
simulation

7.2 Software: Microwind 3.0

7.3 Procedure:

Prepare the CMOS layout of single bit SRAM cell. Do the functional simulation and
verify the results.
Comment on the effect of no load and capacitive load on rise time and fall time.

7.4 Specifications:

Technology: 0.18um
Supply voltage: 2.0V

7.5 Circuit Diagram:

7.6 Layout Diagram:

Attach print of layout.

7.7 Simulation Results:

Attach prints of following results:


iv) Transient analysis result without load.
v) Transient analysis result with capacitive load.
vi) DC transfer characteristic.

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7.8 Conclusion:

Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________

7.9 Answer the following Questions:


1. Compare SRAM with DRAM.
2. What are DRC, LVS, and RCX?

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EXPERIMENT NO: 8

TITLE OF EXPERIMENT: Design of CMOS D Flip Flop layout and verify


the functionality by simulation

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8.1 Aim: Design of CMOS D Flip Flop layout and verify the functionality by
simulation

8.2 Software: Microwind 3.0

8.3 Procedure:

Prepare the CMOS layout of D Flip Flop. Do the functional simulation and verify the
results.
Comment on the effect of no load and capacitive load on rise time and fall time.

8.4 Specifications:

Technology: 0.18um
Supply voltage: 2.0V

8.5 Circuit Diagram:

8.6 Layout Diagram:

Attach print of layout.

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8.7 Simulation Results:

Attach prints of following results:


vii) Transient analysis result without load.
viii) Transient analysis result with capacitive load.
ix) DC transfer characteristic.

8.8 Conclusion:

Comment on effect of no load and capacitive load on rise and fall time.
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________
______________________________________________________________________

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