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  • Color Plates

    Diunggah oleh

    Chaitanya Kumar
    42 tayangan4 halaman
    This document describes the layers and design rules for a 0.25 μm CMOS process. It includes: - A table listing the metal, well, polysilicon, contact/via, and transistor layers and their abbreviations. - Illustrations showing the dimensions of contacts, vias, transistor features, and the overlaps and spacings between layers. - Design rules specifying the minimum distances between wells, contacts, transistors, and other layers.

    Deskripsi Asli:

    DESIGN RULES GATES

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    This document describes the layers and design rules for a 0.25 μm CMOS process. It includes: - A table listing the metal, well, polysilicon, contact/via, and transistor layers and their abbreviations. - Illustrations showing the dimensions of contacts, vias, transistor features, and the overlaps and spacings between layers. - Design rules specifying the minimum distances between wells, contacts, transistors, and other layers.

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    © All Rights Reserved
    Unduh sebagai PDF, TXT atau baca online dari Scribd
    Tandai sebagai konten tidak pantas
    42 tayangan4 halaman

    Color Plates

    Diunggah oleh

    Chaitanya Kumar
    This document describes the layers and design rules for a 0.25 μm CMOS process. It includes: - A table listing the metal, well, polysilicon, contact/via, and transistor layers and their abbreviations. - Illustrations showing the dimensions of contacts, vias, transistor features, and the overlaps and spacings between layers. - Design rules specifying the minimum distances between wells, contacts, transistors, and other layers.

    Hak Cipta:

    © All Rights Reserved
    Unduh sebagai PDF, TXT atau baca online dari Scribd
    Tandai sebagai konten tidak pantas
    dari 4

    Layer Description Representation

    metal

    m1 m2 m3 m4 m5

    well

    nw

    polysilicon

    poly

    contacts & vias

    ct v12,v23,v34,v45 nwc pwc

    active area
    and FETs
    ndif pdif nfet pfet

    select

    nplus pplus prb

    Colorplate 1. CMOS layers and representations


    (for vanilla 0.25 m CMOS process)

    0.3 (contact to contact)

    m1 0.36
    m2

    via contact
    0.14 (poly to contact)
    poly

    0.09 (metal to contact)

    poly-m1
    poly-m1-m2 overlap overlap
    0.14 (ndif to contact)

    m1

    0.28 (transistor to contact) 0.35


    poly
    metal-to-poly
    n+ contact

    Colorplate 4. Design rules regarding contacts and vias.


    Overlapping layers are marked by merged colors.
    1.2

    well (n)
    0.6 m1 0.32 m2 0.4

    1.2

    0.4
    0.32
    active (n) 0.4

    0.3

    0.4 m4 0.4
    polysilicon m3
    0.36

    0.24
    0.4 0.4

    0.44

    m5 0.46
    0.44 n+

    0.1 0.44
    select 0.44
    p+
    contact via
    0.44
    0.3 0.35

    0.44 0.3 0.36

    p+
    poly
    0.14

    0.36

    transistor 0.44

    0.6
    well boundary
    n+ select p+ select
    n-well contact p-well contact

    implicit p-substrate

    Colorplate 5. Design rules regarding well contacts and


    select layers.

    n-well contact

    Vdd
    PMOS

    In Out

    poly-metal
    contact

    NMOS
    GND

    p-well contact

    Colorplate 6. m CMOS technology.

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