MOS-only M-2M DAC for Ultra-Low Voltage

Applications
Israel Sperotto Hamilton Klimach Sergio Bampi
Microelectronics Graduate Program Electrical Engineering Department Informatics Institute
Federal University of Rio Grande do Sul Federal University of Rio Grande do Sul Federal University of Rio Grande do Sul
Porto Alegre, RS, Brazil Porto Alegre, RS, Brazil Porto Alegre, RS, Brazil
Email: israel.mello@inf.ufrgs.br Email: hamilton.klimach@ufrgs.br Email: bampi@inf.ufrgs.br

AbstractThis work presents a study of the CMOS based
R2R ladder network (also called M2M) Digital-to-Analog
Converter (DAC) as a potential candidate for ultra-low voltage
(ULV) applications, i.e. supply voltages VDD lower than 200mV .
MOS transistors operate in subthreshold under such very low
VDD, and the circuit analysis must be done using an all-region
continuous MOSFET model. Simulation results in a commercial
130 nm process corroborate the presented analysis, showing that
it is possible to implement this DAC topology for 6 to 8 bits
operating under supply voltages from 70 mV to 140 mV.
I. I NTRODUCTION
The continuing scaling of CMOS technologies is the main
driving factor behind low voltage operation, rapidly achieving
sub-1 V supplies for process nodes below 130 nm. Current
battery-operated systems require ultra-low current operation,
that ranges from a few nanoamperes to a few microamperes,
depending on the function being executed. Also future self-
powered and self-sustaining electronic systems will require
ultra-low voltage (ULV) operation, since the physical or
chemical environmental strategies that can be used for energy
harvesting generates from 10s to a few 100s of millivolts [1].
And focusing on this perspective, data-converters that could
operate under ULV condition will also be a fundamental class
of electronic circuits [2].
The M2M DAC is a MOS-only version of the R2R ladder
network, that was proposed by Bult and Geelen in 1992 [3],
using a current division property of the MOS transistors. They
noted that two series-connected MOS transistors, with the
same size and gate voltage, equally divide the current applied
on their common terminal, regardless the voltage applied on
the other terminals or the operation region. Since then, this
topology was already published in other DAC applications [4],
[5].
The CMOS M2M ladder operates with transistors in triode
condition, and also can work with transistors in subthreshold,
being a very promising topology for ULV operation.
The paper is organized as follows. In section II the all-
region MOSFET model is reviewed. In section III the basic
structure of the M2M DAC is presented and analysed for any
operation region and the design methodology is presented. In
978-1-4799-8332-2/15/$31.00
2015
c IEEE
section IV the simulation results for the DACs are presented,
while section V presents our main conclusions.
II. MOSFET M ODEL AND M ISMATCH A NALYSIS
The M2M DAC network operates making a binary current
scaling where the division factors are related to the matching
among the MOS transistors that compose the ladder, defining
the entire DAC linearity. Since the linearity of the DAC defines
its effective resolution, a mismatch accurate analysis consistent
with the operation conditions of the MOSFETs is necessary.
The Advanced Compact Model (ACM) [6], is a physics-
based all-region MOSFET model that uses the inversion level
concept, and it provides the modelling foundation for our
analytical formulation. This model represents the drain current
of a transistor as the difference between a forward (IF ) and a
reverse (IR ) component
W
ID = IF IR = ISQ (if ir ) (1)
L
0
where ISQ = 21 Cox n2t is the sheet normalization current,
(W/L) is the aspect ratio, n is the slope factor, is low field
0
mobility, Cox is the oxide capacitance per unit of area and t
is the thermal voltage. Parameters if and ir are the normalized
forward and reverse currents, or inversion levels, at source
and drain, respectively.
The forward and reverse inversion levels are also related to
the terminal voltages as follows
VG VT nVS(D) =
h q  q i
= nt ln 1 + if (r) 1 + 1 + if (r) 2 (2)
where VG , VS and VD are the gate, source and drain voltages
refered to bulk, respectively, and VT is the threshold voltage.
A MOSFET mismatch model based on the ACM model
was proposed in [7], being more appropriate to the DAC
nonlinearity analysis than the traditional Pelgroms mismatch
model, that does not consider the subthreshold nonlinear nature
of MOSFETs in a proper way. The following equation presents
the dependency of the current mismatch on the transistor area,
the inversion levels and the technology parameters
I2D
   
1 Noi 1 1 + if 2
2 = W L N 2 i i ln
ID 1 + ir
+ BISQ (3)
f r
 Fig. 1: M2M Ladder Network.

where N = nCox 0
t /q is the carrier density at pinch-
off condition, Noi is the main mismatch model parameter,
related to the number of impurity atoms inside the depletion
volume under the channel area, and BISQ is a less significant
model parameter that accounts for variations in the specific Fig. 2: Inversion levels analysis.
normalization current ISQ .
III. C IRCUIT D ESCRIPTION AND D ESIGN M ETHODOLOGY
The ladder network shown in Fig. 1 is formed by a sequence
of M2M cells, one per bit, and finalized by a 2M termination.
In general this ladder is formed by cells with transistors having
the same geometry, simplifying the layout. Each cell divides its
input current by half, performing the DAC weighting through
successive binary divisions of the reference current IRef gen-
erated by VRef . The two drain connected transistors M2 and
M3 deviates the binary fraction of the current to Iout or I out
Fig. 3: Sensitivity analysis.
nodes, depending on the Si switch state, since these nodes are
tied to ground through a very low impedance connection. The
switches are implemented with transmission gates triggered
by an auxiliary digital circuit (Shift Register) that will allow if + i1
the perfect measurement of the converter. Finally, the current i2 = (5)
2
summing that results in the Iout node represents a binary
proportion of IRef , controlled by the digital data that sets Expanding this analysis one can determine the intermediate
the switches. The four identical MOSFETs on each cell leads inversion level (ii ) for any branch i of the ladder from if
to a very regular and compact layout. A detailed explanation (determined by VG ) and ir (determined by VRef ) using the
of this network can be found in [8]. following expression
The analysis of the resulting inversion levels of the ladder
ir + (2i 1)if
nodes can be done using a simplified version with only 2 ii = (6)
bits of resolution, as shown in Fig. 2, where if and ir 2i
are the inversion level of the transistors source and drain From this point a variability analysis can be performed
terminals, respectively. Note that all transistors have the same over the ladder using a small-signal model, since the drain
gate biasing, and since the lower transistors of the ladder have current mismatch in the branches can be considered small.
also the same source biasing, they present the same if level. Using eq. (3) and the forward and reverse inversion levels of
Since the current in the series transistors Ma and Mb is the the lower transistors of the ladder (M2 , M5 and M8 in Fig.
same, having both the same geometry, from eq. (1) one can 3), one can estimate the mismatch statistical contribution of
state the following relationship for the intermediate inversion these transistors in the current flowing in each branch (in Fig.
level i1 3 the drain current mismatch contribution of M5 is indicated
if + ir as ID ).
i1 = (4)
2 After that, the mismatch contribution of each branch can
Also, since the input current I is divided in two equal por- be propagated to the other branches, using the small-signal
tions by equally sized transistors (Ma and Mc ), the inversion approximation and considering the current division property
level of the source terminal of these transistors must be the of the MOS transistors [3]. Finally, the contributions from the
same (i1 ). This analysis can be done in the next cell (formed mismatch of all lower transistors can be combined in each
by Mda , Mdb , Mdc and Mdd ), resulting that the inversion level branch resulting an approximation of the drain current error,
of the intermediate node (i2 ) is given by which can be used to estimate the DAC non-linearity.
 For example, in Fig. 3 the M5 mismatch error ID propa-
gates through M3 and M6 , according to the current division
properties of both branches, resulting that the contribution that
flows in M6 is ID /3 and in M8 is ID /6.
This method was implemented in MatLab to create a tool
that can estimate the statistical error of an M2M DAC, in
terms of the standard-deviation of the output current Err ,
when related to the ideal linear behavior, showing this error
already in LSB (related to the intended resolution). This
estimation is performed for a given bias (VG and VRef ),
resolution (the depth of the ladder), and transistors size (W
and L).

IV. S IMULATION R ESULTS

The method was applied in two M2M DACs, with 6 (a) VRef = 70mV (if = 0.1)
and 8 bits, to be implemented in the IBM 130 nm process
using standard NMOS transistors (VT = 200mV for long
channel FETs). Two equal values of VG and VRef were chosen
to simplify our analysis, 70mV and 140mV , resulting the
inversion levels, if = 0.1 and if = 0.8, both in the weak
inversion range. The design keeps L = 10m as a way to
avoid short-channel effects [8].
The mismatch parameter BISQ on equation (3) was obtained
from the process PDK (3 %-um), and Noi can be estimated
from the AVT mismatch parameter of the Pelgroms model
[9], using
p C 0 AV
Noi = ox T (7)
q
resulting Noi = 7 1013 cm2 . (b) VRef = 140mV (if = 0.8)
The Fig. 4 presents the estimated error of both DACs, for
the two biasing voltages, related to the transistor area, and can Fig. 4: Maximum error as a function of the transistor area and
be used for design-space exploration. inversion levels.
As a way to validate our analytical results we simulated
TABLE I: Comparison between the two DACs designed in this
both M2M DACs using the Cadence-Virtuoso tool. Monte-
work.
Carlo (MC) simulation with 500 runs was performed, and the
standard deviation of the error (err (LSB)) was calculated Resolution 8-bit DAC 6-bit DAC
refered to the LSB. Supply 70mV /140mV 70mV /140mV
IN L (LSB) 0.47/0.4 0.4/0.35
Using Fig. 4 we choose the aspect ratio for the 6-bit Area 0.1mm2 0.0065mm2
25m
converter equal to W L = 10m , and the DAC area results
2
0.0065mm since this DAC has 26 transistors (six cells with
four transistors plus a termination with two). Analytical and be expected since this circuit presents very large parasitic ca-
simulated results can be seen in Fig. 5 for reference voltages pacitances. Table I shows a compilation of the two converters
VRef equal to 70mV and 140mV . proposed here. The INL presented in Table I is for one .
The 8-bits DAC was designed with the aspect ratio of Previously published ADC [10] working at similarly low
W 300m
L = 10m for all transistors, resulting a DAC total area of VDD supply has a minimum VDD of 200mV and 6-bit
0.1mm2 . Analytical and simulated results can be seen in Fig. resolution, which is a challenge addressed also in our DAC.
6 for reference voltages VRef equal to 70mV and 140mV . Normally the resolution of ADCs are limited by the internal
Since analytical and simulated results are similar, we sup- DAC and our work demonstrates that there are advancements
pose that our methodology can be used for trade-off estimation needed in the ULV operation of data converters.
and design-space exploration of M2M DACs operating under One final aspect that must be observed is that since the
ULV. MOSFET ladder operates using a reference voltage rather
Also, results corroborate that the M2M DAC is a promising than a current, the resulting current would be very sensitive
topology for ULV applications, being possible to implement to process variability. But this dependence does not imply
an 8-bit DAC with a reasonable area. High-speed should not nonlinearity and can be calibrated.
 (a) VRef = 70mV (if = 0.1)
(b) VRef = 140mV (if = 0.8)
Fig. 5: Comparison between analytical and simulated results
of a 6-bit converter.
V. C ONCLUSION
In this paper we presented a mismatch analysis of the M2M
ladder DAC operating under ULV biasing, which contributes
to a methodology that can be used for design-space exploration
and trade-off estimation. To test our methodology two DACs
were designed in a 130 nm process, with 6 and 8 bits, which
can operate with 70 and 140 mV. Monte-Carlo simulations
corroborate our analytical approach, indicating that M2M
ladders are a promising topology for ULV applications.
ACKNOWLEDGEMENT
The authors would like to thank CAPES, CNPq and the
IC-Brazil Program for supporting this work.
R EFERENCES
[1] J. M. Rabaey, F. Burghardt, D. Steingart, M. Seeman, and P. Wright,
Energy harvestingA systems perspective, in Proc. 2007 IEEE Intl.
Electron Devices Meeting, Piscataway, 2007.
[2] A. Kvitschal, C. C. Santos Jr., L. K. Slongo, R. M. da Ponte, and C.
Galup-Montoro, A 6-bit, 0.1V DAC based on an M2M ladder network
in IBM 130 nm CMOS, in Student Forum on Microelectronics, Aug.
2012.
[3] K. Bult, and G. Geelen, An inherently linear and compact MOST-only
current division technique, in IEEE J. Solid-State Circuits, vol. 27, no.
12, pp. 1730 - 1735, Dec. 1992.
(a) VRef = 70mV (if = 0.1)
(b) VRef = 140mV (if = 0.8)
Fig. 6: Comparison between analytical and simulated results
of a 8-bit converter.
[4] C. Hammerschmied, and Qiuting Huang, Design and implementation of
an untrimmed MOSFET-only 10-bit A/D converter with -79-dB THD, in
IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1148 - 1157, Aug. 1998.
[5] L. Wang, Y. Fukatsu, and K. Watanabe, Characterization of current-mode
CMOS R-2R ladder digital-to-analog converters, in IEEE Trans. Instr.
and Measurement, vol. 50, no. 6, pp. 1781 - 1786, Dec. 2001.
[6] A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro, An MOS transistor
model for analog circuit design, in IEEE J. Solid-State Circuits, vol.33,
no.10, pp.1510-1519, Oct.1998.
[7] C. Galup-Montoro, M.C. Schneider, H. Klimach, and A. Arnaud, A
compact model of MOSFET mismatch for circuit design, in IEEE J.
Solid-State Circuits, vol. 40, no. 8, pp. 1649-1657, Aug. 2005.
[8] H. Klimach, C. Galup-Montoro, and M. C. Schneider. An M2M digital-
to-analog converter design methodology based on a physical mismatch
model, in IEEE International Symposium on Circuits and Systems,
Seattle, May 2008.
[9] H. Klimach. Modelo do descasamento (mismatch) entre transistores
MOS. Ph.D. Thesis of the Federal University of Santa Catarina, Flo-
rianopolis, Brazil, Mar. 2008.
[10] D.C. Daly and A. P. Chandrakasan. A 6-bit, 0.2 V to 0.9 V Highly
Digital Flash ADC With Comparator Redundancy, in IEEE Journal of
Solid-State Circuits, vol. 44, no. 11 pp. 30303038, Nov. 2009.