ADSP-218xN Series
PERFORMANCE FEATURES Programmable 16-Bit Interval Timer with Prescaler
12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS 100-Lead LQFP and 144-Ball Mini-BGA
Sustained Performance
Single-Cycle Instruction Execution SYSTEM INTERFACE FEATURES
Single-Cycle Context Switch Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation
3-Bus Architecture Allows Dual Operand Fetches in All Inputs Tolerate up to 3.6 V Regardless of Mode
Every Instruction Cycle 16-Bit Internal DMA Port for High-Speed Access to On-
Multifunction Instructions Chip Memory (Mode Selectable)
Power-Down Mode Featuring Low CMOS Standby 4M-Byte Memory Interface for Storage of Data Tables
Power Dissipation with 200 CLKIN Cycle Recovery and Program Overlays (Mode Selectable)
from Power-Down Condition 8-Bit DMA to Byte Memory for Transparent Program and
Low Power Dissipation in Idle Mode Data Memory Transfers (Mode Selectable)
Programmable Memory Strobe and Separate I/O
INTEGRATION FEATURES Memory Space Permits Glueless System Design
ADSP-2100 Family Code Compatible (Easy to Use Programmable Wait State Generation
Algebraic Syntax), with Instruction Set Extensions Two Double-Buffered Serial Ports with Companding
Up to 256K Bytes of On-Chip RAM, Configured as Hardware and Automatic Data Buffering
Up to 48K Words Program Memory RAM Automatic Booting of On-Chip Program Memory from
Up to 56K Words Data Memory RAM Byte-Wide External Memory, e.g., EPROM, or through
Dual-Purpose Program Memory for Both Instruction and Internal DMA Port
Data Storage Six External Interrupts
Independent ALU, Multiplier/Accumulator, and Barrel 13 Programmable Flag Pins Provide Flexible System
Shifter Computational Units Signaling
Two Independent Data Address Generators UART Emulation through Software SPORT
Powerful Program Sequencer Provides Zero Overhead Reconfiguration
Looping Conditional Instruction Execution ICE-Port Emulator Interface Supports Debugging in
Final Systems
POWER-DOWN
CONTROL
FULL MEMORY MODE
MEMORY
PROGRAM DATA PROGRAMMABLE EXTERNAL
DATA ADDRESS I/O
GENERATORS MEMORY MEMORY ADDRESS
PROGRAM UP TO UP TO AND BUS
DAG1 DAG2 SEQUENCER 48K 24-BIT 56K 16-BIT FLAGS
re. EXTERNAL
he DATA
m BUS
gra
PROGRAM MEMORY ADDRESS
dia BYTE DMA
ck DATA MEMORY ADDRESS
blo
CONTROLLER
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ADSP-218xN Series
The EZ-KIT Lite includes the following features: units process 16-bit data directly and have provisions to
75 MHz ADSP-2189M support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division
Full 16-Bit Stereo Audio I/O with AD73322 Codec primitives are also supported. The MAC performs single-
RS-232 Interface cycle multiply, multiply/add, and multiply/subtract opera-
EZ-ICE Connector for Emulator Control tions with 40 bits of accumulation. The shifter performs
DSP Demonstration Programs logical and arithmetic shifts, normalization, denormaliza-
tion, and derive exponent operations.
Evaluation Suite of VisualDSP++
The shifter can be used to efficiently implement numeric
The ADSP-218x EZ-ICE Emulator provides an easier and format control, including multiword and block floating-
more cost-effective method for engineers to develop and point representations.
optimize DSP systems, shortening product development
cycles for faster time-to-market. ADSP-218xN series The internal result (R) bus connects the computational
members integrate on-chip emulation support with a 14-pin units so that the output of any unit may be the input of any
ICE-Port interface. This interface provides a simpler target unit on the next cycle.
board connection that requires fewer mechanical clearance A powerful program sequencer and two dedicated data
considerations than other ADSP-2100 Family EZ-ICEs. address generators ensure efficient delivery of operands to
ADSP-218xN series members need not be removed from these computational units. The sequencer supports condi-
the target system when using the EZ-ICE, nor are any adapt- tional jumps, subroutine calls, and returns in a single cycle.
ers needed. Due to the small footprint of the EZ-ICE con- With internal loop counters and loop stacks, ADSP-218xN
nector, emulation can be supported in final board series members execute looped code with zero overhead; no
designs.The EZ-ICE performs a full range of functions, explicit jump instructions are required to maintain loops.
including: Two data address generators (DAGs) provide addresses for
In-target operation simultaneous dual operand fetches (from data memory and
Up to 20 breakpoints program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access
Single-step or full-speed operation
data (indirect addressing), it is post-modified by the value
Registers and memory values can be examined of one of four possible modify registers. A length value may
and altered be associated with each pointer to implement automatic
PC upload and download functions modulo addressing for circular buffers.
Instruction-level emulation of program booting Five internal buses provide efficient data transfer:
and execution
Program Memory Address (PMA) Bus
Complete assembly and disassembly of instructions
Program Memory Data (PMD) Bus
C source-level debugging
Data Memory Address (DMA) Bus
Additional Information Data Memory Data (DMD) Bus
This data sheet provides a general overview of ADSP- Result (R) Bus
218xN series functionality. For additional information on
the architecture and instruction set of the processor, refer The two address buses (PMA and DMA) share a single
to the ADSP-218x DSP Hardware Reference and the ADSP- external address bus, allowing memory to be expanded off-
218x DSP Instruction Set Reference. chip, and the two data buses (PMD and DMD) share a
single external data bus. Byte memory space and I/O
ARCHITECTURE OVERVIEW memory space also share the external buses.
The ADSP-218xN series instruction set provides flexible Program memory can store both instructions and data, per-
data moves and multifunction (one or two data moves with mitting ADSP-218xN series members to fetch two oper-
a computation) instructions. Every instruction can be exe- ands in a single cycle, one from program memory and one
cuted in a single processor cycle. The ADSP-218xN assem- from data memory. ADSP-218xN series members can fetch
bly language uses an algebraic syntax for ease of coding and an operand from program memory and the next instruction
readability. A comprehensive set of development tools sup- in the same cycle.
ports program development.
In lieu of the address and data bus for external memory
The functional block diagram is an overall block diagram of connection, ADSP-218xN series members may be config-
the ADSP-218xN series. The processor contains three in- ured for 16-bit Internal DMA port (IDMA port) connec-
dependent computational units: the ALU, the multiplier/ tion to external systems. The IDMA port is made up of 16
accumulator (MAC), and the shifter. The computational
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ADSP-218xN Series
data/address pins and five control pins. The IDMA port SPORTs have independent framing for the receive and
provides transparent, direct access to the DSPs on-chip transmit sections. Sections run in a frameless mode or
program and data RAM. with frame synchronization signals internally or externally
An interface to low-cost byte-wide memory is provided by generated. Frame sync signals are active high or inverted,
the Byte DMA port (BDMA port). The BDMA port is with either of two pulsewidths and timings.
bidirectional and can directly address up to four megabytes SPORTs support serial data word lengths from 3 to
of external RAM or ROM for off-chip storage of program 16 bits and provide optional A-law and -law compand-
overlays or data tables. ing, according to CCITT recommendation G.711.
The byte memory and I/O memory space interface supports SPORT receive and transmit sections can generate
slow memories and I/O memory-mapped peripherals with unique interrupts on completing a data word transfer.
programmable wait state generation. External devices can SPORTs can receive and transmit an entire circular buffer
gain control of external buses with bus request/grant signals of data with only one overhead cycle per data word. An
(BR, BGH, and BG). One execution mode (Go Mode) interrupt is generated after a data buffer transfer.
allows the ADSP-218xN to continue running from on-chip SPORT0 has a multichannel interface to selectively
memory. Normal execution mode requires the processor to receive and transmit a 24 or 32 word, time-division mul-
halt while buses are granted. tiplexed, serial bitstream.
ADSP-218xN series members can respond to eleven inter- SPORT1 can be configured to have two external inter-
rupts. There can be up to six external interrupts (one edge- rupts (IRQ0 and IRQ1) and the FI and FO signals. The
sensitive, two level-sensitive, and three configurable) and internally generated serial clock may still be used in this
seven internal interrupts generated by the timer, the serial configuration.
ports (SPORT), the Byte DMA port, and the power-down
circuitry. There is also a master RESET signal. The two PIN DESCRIPTIONS
serial ports provide a complete synchronous serial interface ADSP-218xN series members are available in a 100-lead
with optional companding in hardware and a wide variety LQFP package and a 144-Ball Mini-BGA package. In order
of framed or frameless data transmit and receive modes of to maintain maximum functionality and reduce package size
operation. and pin count, some serial port, programmable flag, inter-
rupt and external bus pins have dual, multiplexed function-
Each port can generate an internal programmable serial
ality. The external bus pins are configured during RESET
clock or accept an external serial clock.
only, while serial port pins are software configurable during
ADSP-218xN series members provide up to 13 general- program execution. Flag and interrupt functionality is
purpose flag pins. The data input and output pins on retained concurrently on multiplexed pins. In cases where
SPORT1 can be alternatively configured as an input flag pin functionality is reconfigurable, the default state is shown
and an output flag. In addition, eight flags are programma- in plain text in Table 2, while alternate functionality is
ble as inputs or outputs, and three flags are always outputs. shown in italics.
A programmable interval timer generates periodic inter-
rupts. A 16-bit count register (TCOUNT) decrements
every n processor cycle, where n is a scaling value stored
in an 8-bit register (TSCALE). When the value of the count
register reaches zero, an interrupt is generated and the
count register is reloaded from a 16-bit period register
(TPERIOD).
Serial Ports
ADSP-218xN series members incorporate two complete
synchronous serial ports (SPORT0 and SPORT1) for serial
communications and multiprocessor communication.
Following is a brief list of the capabilities of the ADSP-
218xN SPORTs. For additional information on Serial
Ports, refer to the ADSP-218x DSP Hardware Reference.
SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
SPORTs can use an external serial clock or generate their
own serial clock internally.
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ADSP-218xN Series
Table 2. Common-Mode Pins
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ADSP-218xN Series
Memory Interface Pins signals at specific pins of the DSP during either of the two
ADSP-218xN series members can be used in one of two operating modes (Full Memory or Host). A signal in one
modes: Full Memory Mode, which allows BDMA operation table shares a pin with a signal from the other table, with the
with full external overlay memory and I/O capability, or active signal determined by the mode that is set. For the
Host Mode, which allows IDMA operation with limited shared pins and their alternate signals (e.g., A4/IAD3), refer
external addressing capabilities. to the package pinouts in Table 27 on page 40 and Table 28
The operating mode is determined by the state of the Mode on page 42.
C pin during RESET and cannot be changed while the
processor is running. Table 3 and Table 4 list the active
I/O
3-State Reset
Pin Name1 (Z)2 State Hi-Z3 Caused By Unused Configuration
XTAL O O Float
CLKOUT O O Float4
A131 or O (Z) Hi-Z BR, EBR Float
IAD120 I/O (Z) Hi-Z IS Float
A0 O (Z) Hi-Z BR, EBR Float
D238 I/O (Z) Hi-Z BR, EBR Float
D7 or I/O (Z) Hi-Z BR, EBR Float
IWR I I High (Inactive)
D6 or I/O (Z) Hi-Z BR, EBR Float
IRD I I BR, EBR High (Inactive)
D5 or I/O (Z) Hi-Z Float
IAL I I Low (Inactive)
D4 or I/O (Z) Hi-Z BR, EBR Float
IS I I High (Inactive)
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ADSP-218xN Series
Table 5. Unused Pin Terminations (Continued)
I/O
3-State Reset
Pin Name1 (Z)2 State Hi-Z3 Caused By Unused Configuration
D3 or I/O (Z) Hi-Z BR, EBR Float
IACK Float
D20 or I/O (Z) Hi-Z BR, EBR Float
IAD1513 I/O (Z) Hi-Z IS Float
PMS O (Z) O BR, EBR Float
DMS O (Z) O BR, EBR Float
BMS O (Z) O BR, EBR Float
IOMS O (Z) O BR, EBR Float
CMS O (Z) O BR, EBR Float
RD O (Z) O BR, EBR Float
WR O (Z) O BR, EBR Float
BR I I High (Inactive)
BG O (Z) O EE Float
BGH O O Float
IRQ2/PF7 I/O (Z) I Input = High (Inactive) or Program as
Output, Set to 1, Let Float5
IRQL1/PF6 I/O (Z) I Input = High (Inactive) or Program as
Output, Set to 1, Let Float5
IRQL0/PF5 I/O (Z) I Input = High (Inactive) or Program as
Output, Set to 1, Let Float5
IRQE/PF4 I/O (Z) I Input = High (Inactive) or Program as
Output, Set to 1, Let Float5
PWD I I High
SCLK0 I/O I Input = High or Low, Output = Float
RFS0 I/O I High or Low
DR0 I I High or Low
TFS0 I/O I High or Low
DT0 O O Float
SCLK1 I/O I Input = High or Low, Output = Float
RFS1/IRQ0 I/O I High or Low
DR1/FI I I High or Low
TFS1/IRQ1 I/O I High or Low
DT1/FO O O Float
EE I I Float
EBR I I Float
EBG O O Float
ERESET I I Float
EMS O O Float
EINT I I Float
ECLK I I Float
ELIN I I Float
ELOUT O O Float
1CLKIN, RESET, and PF30/Mode D A are not included in this table because these pins must be used.
2All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.
3Hi-Z = High Impedance.
4If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.
5If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function
as interrupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts,
and let pins float.
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ADSP-218xN Series
Interrupts The IFC register is a write-only register used to force and
The interrupt controller allows the processor to respond to clear interrupts. On-chip stacks preserve the processor
the eleven possible interrupts and reset with minimum over- status and are automatically maintained during interrupt
head. ADSP-218xN series members provide four dedicated handling. The stacks are 12 levels deep to allow interrupt,
external interrupt input pins: IRQ2, IRQL0, IRQL1, and loop, and subroutine nesting. The following instructions
IRQE (shared with the PF74 pins). In addition, SPORT1 allow global enable or disable servicing of the interrupts
may be reconfigured for IRQ0, IRQ1, FI and FO, for a total (including power-down), regardless of the state of IMASK:
of six external interrupts. The ADSP-218xN also supports ENA INTS;
internal interrupts from the timer, the byte DMA port, the DIS INTS;
two serial ports, software, and the power-down control cir-
cuit. The interrupt levels are internally prioritized and indi- Disabling the interrupts does not affect serial port auto-
vidually maskable (except power-down and reset). The buffering or DMA. When the processor is reset, interrupt
IRQ2, IRQ0, and IRQ1 input pins can be programmed to servicing is enabled.
be either level- or edge-sensitive. IRQL0 and IRQL1 are LOW-POWER OPERATION
level-sensitive and IRQE is edge-sensitive. The priorities ADSP-218xN series members have three low-power modes
and vector addresses of all interrupts are shown in Table 6. that significantly reduce the power dissipation when the
device operates under standby conditions. These modes are:
Table 6. Interrupt Priority and Interrupt Vector
Addresses Power-Down
Idle
Interrupt Vector Address
Source Of Interrupt (Hex) Slow Idle
Reset (or Power-Up with 0x0000 (Highest Priority) The CLKOUT pin may also be disabled to reduce external
PUCR = 1) power dissipation.
Power-Down 0x002C Power-Down
(Nonmaskable) ADSP-218xN series members have a low-power feature that
IRQ2 0x0004 lets the processor enter a very low-power dormant state
IRQL1 0x0008 through hardware or software control. Following is a brief
IRQL0 0x000C list of power-down features. Refer to the ADSP-218x DSP
SPORT0 Transmit 0x0010 Hardware Reference, System Interface chapter, for detailed
SPORT0 Receive 0x0014 information about the power-down feature.
IRQE 0x0018
Quick recovery from power-down. The processor begins
BDMA Interrupt 0x001C
executing instructions in as few as 200 CLKIN cycles.
SPORT1 Transmit or 0x0020
IRQ1 Support for an externally generated TTL or CMOS
SPORT1 Receive or IRQ0 0x0024 processor clock. The external clock can continue running
Timer 0x0028 (Lowest Priority) during power-down without affecting the lowest power
rating and 200 CLKIN cycle recovery.
Interrupt routines can either be nested with higher priority Support for crystal operation includes disabling the oscil-
interrupts taking precedence or processed sequentially. In- lator to save power (the processor automatically waits
terrupts can be masked or unmasked with the IMASK reg- approximately 4096 CLKIN cycles for the crystal oscilla-
ister. Individual interrupt requests are logically ANDed tor to start or stabilize), and letting the oscillator run to
with the bits in IMASK; the highest priority unmasked in- allow 200 CLKIN cycle start-up.
terrupt is then selected. The power-down interrupt is non- Power-down is initiated by either the power-down pin
maskable. (PWD) or the software power-down force bit. Interrupt
ADSP-218xN series members mask all interrupts for one support allows an unlimited number of instructions to be
instruction cycle following the execution of an instruction executed before optionally powering down. The power-
that modifies the IMASK register. This does not affect serial down interrupt also can be used as a nonmaskable, edge-
port autobuffering or DMA transfers. sensitive interrupt.
The interrupt control register, ICNTL, controls interrupt Context clear/save control allows the processor to
nesting and defines the IRQ0, IRQ1, and IRQ2 external continue where it left off or start with a clean context when
interrupts to be either edge- or level-sensitive. The IRQE leaving the power-down state.
pin is an external edge-sensitive interrupt and can be forced
and cleared. The IRQL0 and IRQL1 pins are external level
sensitive interrupts.
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ADSP-218xN Series
The RESET pin also can be used to terminate power- When the IDLE (n) instruction is used, it effectively slows
down. down the processors internal clock and thus its response
Power-down acknowledge pin (PWDACK) indicates time to incoming interrupts. The one-cycle response time
when the processor has entered power-down. of the standard idle state is increased by n, the clock divisor.
When an enabled interrupt is received, ADSP-218xN series
Idle members remain in the idle state for up to a maximum of n
When the ADSP-218xN is in the Idle Mode, the processor processor cycles (n = 16, 32, 64, or 128) before resuming
waits indefinitely in a low-power state until an interrupt normal operation.
occurs. When an unmasked interrupt occurs, it is serviced;
When the IDLE (n) instruction is used in systems that have
execution then continues with the instruction following the
an externally generated serial clock (SCLK), the serial clock
IDLE instruction. In Idle mode IDMA, BDMA, and auto-
rate may be faster than the processors reduced internal
buffer cycle steals still occur.
clock rate. Under these conditions, interrupts must not be
Slow Idle generated at a faster rate than can be serviced, due to the
The IDLE instruction is enhanced on ADSP-218xN series additional time the processor takes to come out of the idle
members to let the processors internal clock signal be state (a maximum of n processor cycles).
slowed, further reducing power consumption. The reduced
SYSTEM INTERFACE
clock frequency, a programmable fraction of the normal
Figure 1 shows typical basic system configurations with the
clock rate, is specified by a selectable divisor given in the
ADSP-218xN series, two serial devices, a byte-wide
IDLE instruction.
EPROM, and optional external program and data overlay
The format of the instruction is: memories (mode-selectable). Programmable wait state gen-
IDLE (N); eration allows the processor to connect easily to slow periph-
eral devices. ADSP-218xN series members also provide
where N = 16, 32, 64, or 128. This instruction keeps the
four external interrupts and two serial ports or six external
processor fully functional, but operating at the slower clock
interrupts and one serial port. Host Memory Mode allows
rate. While it is in this state, the processors other internal
access to the full external data bus, but limits addressing to
clock signals, such as SCLK, CLKOUT, and timer clock,
a single address bit (A0). Through the use of external hard-
are reduced by the same ratio. The default form of the in-
ware, additional system peripherals can be added in this
struction, when no clock divisor is given, is the standard
mode to generate and latch address signals.
IDLE instruction.
REV. 0 9
ADSP-218xN Series
Clock Signals RESET
ADSP-218xN series members can be clocked by either a The RESET signal initiates a master reset of the ADSP-
crystal or a TTL-compatible clock signal. 218xN. The RESET signal must be asserted during the
The CLKIN input cannot be halted, changed during oper- power-up sequence to assure proper initialization. RESET
ation, nor operated below the specified frequency during during initial power-up must be held long enough to allow
normal operation. The only exception is while the processor the internal clock to stabilize. If RESET is activated any time
is in the power-down state. For additional information, refer after power-up, the clock continues to run and does not
to the ADSP-218x DSP Hardware Reference, for detailed require stabilization time.
information on this power-down feature. The power-up sequence is defined as the total time required
If an external clock is used, it should be a TTL-compatible for the crystal oscillator circuit to stabilize after a valid VDD
signal running at half the instruction rate. The signal is is applied to the processor, and for the internal phase-locked
connected to the processors CLKIN input. When an exter- loop (PLL) to lock onto the specific crystal frequency. A
nal clock is used, the XTAL pin must be left unconnected. minimum of 2000 CLKIN cycles ensures that the PLL has
locked, but does not include the crystal oscillator start-up
ADSP-218xN series members use an input clock with a time. During this power-up sequence the RESET signal
frequency equal to half the instruction rate; a 40 MHz input should be held low. On any subsequent resets, the RESET
clock yields a 12.5 ns processor cycle (which is equivalent signal must meet the minimum pulse-width specification
to 80 MHz). Normally, instructions are executed in a single (tRSP).
processor cycle. All device timing is relative to the internal
instruction clock rate, which is indicated by the CLKOUT The RESET input contains some hysteresis; however, if an
signal when enabled. RC circuit is used to generate the RESET signal, the use of
an external Schmitt trigger is recommended.
Because ADSP-218xN series members include an on-chip
oscillator circuit, an external crystal may be used. The The master reset sets all internal stack pointers to the empty
crystal should be connected across the CLKIN and XTAL stack condition, masks all interrupts, and clears the MSTAT
pins, with two capacitors connected as shown in Figure 2. register. When RESET is released, if there is no pending
Capacitor values are dependent on crystal type and should bus request and the chip is configured for booting, the boot-
be specified by the crystal manufacturer. A parallel- loading sequence is performed. The first instruction is
resonant, fundamental frequency, microprocessor-grade fetched from on-chip program memory location 0x0000
crystal should be used. once boot loading completes.
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ADSP-218xN Series
MODES OF OPERATION
The ADSP-218xN series modes of operation appear in
Table 7.
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ADSP-218xN Series
MEMORY ARCHITECTURE Refer to Figure 3 through Figure 8, Table 8 on page 14, and
The ADSP-218xN series provides a variety of memory and Table 9 on page 14 for PM and DM memory allocations in
peripheral interface options. The key functional groups are the ADSP-218xN series.
Program Memory, Data Memory, Byte Memory, and I/O.
0X2000 0X2000
0X1FFF 0X1FFF 0X2000
0X1FFF
DM OVERLAY 1,2
EXTERNAL PM INTERNAL PM (EXTERNAL DM)
DM OVERLAY 0
(RESERVED)
0X0000 0X0000 0X0000
12 REV. 0
ADSP-218xN Series
0X2000 0X2000
0X1FFF 0X1FFF 0X2000
0X1FFF
DM OVERLAY 1,2
EXTERNAL PM INTERNAL PM (EXTERNAL DM)
DM OVERLAY 0,4,5
(INTERNAL DM)
0X0000 0X0000 0X0000
0X2000 0X2000
0X1FFF 0X1FFF 0X2000
0X1FFF DM OVERLAY 1,2
(EXTERNAL DM)
EXTERNAL PM INTERNAL PM
DM OVERLAY
0,4,5,6,7
(INTERNAL DM)
0X0000 0X0000 0X0000
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ADSP-218xN Series
Program Memory Program Memory (Host Mode) allows access to all internal
Program Memory (Full Memory Mode) is a 24-bit-wide memory. External overlay access is limited by a single exter-
space for storing both instruction opcodes and data. The nal address line (A0). External program execution is not
ADSP-218xN series has up to 48K words of Program available in host mode due to a restricted data bus that is
Memory RAM on chip, and the capability of accessing up only 16 bits wide.
to two 8K external memory overlay spaces, using the exter-
nal data bus.
Data Memory plete in one cycle. Accesses to external memory are timed
Data Memory (Full Memory Mode) is a 16-bit-wide space using the wait states specified by the DWAIT register and
used for the storage of data variables and for memory- the wait state mode bit.
mapped control registers. The ADSP-218xN series has up Data Memory (Host Mode) allows access to all internal
to 56K words of Data Memory RAM on-chip. Part of this memory. External overlay access is limited by a single exter-
space is used by 32 memory-mapped registers. Support also nal address line (A0).
exists for up to two 8K external memory overlay spaces
through the external data bus. All internal accesses com-
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ADSP-218xN Series
Memory-Mapped Registers (New to the ADSP-218xM
and N series) WAIT STATE CONTROL
15 14 13 12 11 10 9 8 7 6 2 e1r 0
5 4 3
ADSP-218xN series members have three memory-mapped 1 1 1 1 1 1 1 1 1 1
st
1 eg1i 1 1
1 1DM(0X3FFE)
registers that differ from other ADSP-21xx Family DSPs. l R
tr o
n
The slight modifications to these registers (Wait State Con- DWAIT IOWAIT3
Co
IOWAIT2 IOWAIT1 IOWAIT0
REV. 0 15
ADSP-218xN Series
SYSTEM CONTROL BDMA CONTROL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 DM(0X3FFF) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 DM (0x3FE3)
16 REV. 0
ADSP-218xN Series
DSP cycle. DSP accesses to external memory have priority Table 12. IDMA/BDMA Overlay Bits
over BDMA byte memory accesses.
IDMA/BDMA IDMA/BDMA
The BDMA Context Reset bit (BCR) controls whether the Processor PMOVLAY DMOVLAY
processor is held off while the BDMA accesses are occur-
ADSP-2184N 0 0
ring. Setting the BCR bit to 0 allows the processor to con-
ADSP-2185N 0 0
tinue operations. Setting the BCR bit to 1 causes the
ADSP-2186N 0 0
processor to stop execution while the BDMA accesses are
ADSP-2187N 0, 4, 5 0, 4, 5
occurring, to clear the context of the processor, and start
ADSP-2188N 0, 4, 5, 6, 7 0, 4, 5, 6, 7, 8
execution at address 0 when the BDMA accesses have
completed. ADSP-2189N 0, 4, 5 0, 4, 5, 6, 7
The BDMA overlay bits specify the OVLAY memory blocks The IDMA port has a 16-bit multiplexed address and data
to be accessed for internal memory. Set these bits as indi- bus and supports 24-bit program memory. The IDMA port
cated in. is completely asynchronous and can be written while the
Note: BDMA cannot access external overlay memory ADSP-218xN is operating at full speed.
regions 1 and 2. The DSP memory address is latched and then automatically
The BMWAIT field, which has four bits on ADSP-218xN incremented after each IDMA transaction. An external
series members, allows selection up to 15 wait states for device can therefore access a block of sequentially addressed
BDMA transfers. memory by specifying only the starting address of the block.
This increases throughput as the address does not have to
Internal Memory DMA Port (IDMA Port; Host Memory be sent for each memory access.
Mode)
The IDMA Port provides an efficient means of communi- IDMA Port access occurs in two phases. The first is the
cation between a host system and ADSP-218xN series IDMA Address Latch cycle. When the acknowledge is as-
members. The port is used to access the on-chip program serted, a 14-bit address and 1-bit destination type can be
memory and data memory of the DSP with only one DSP driven onto the bus by an external device. The address spec-
cycle per word overhead. The IDMA port cannot, however, ifies an on-chip memory location, the destination type spec-
be used to write to the DSPs memory-mapped control reg- ifies whether it is a DM or PM access. The falling edge of
isters. A typical IDMA transfer process is shown as follows: the IDMA address latch signal (IAL) or the missing edge of
the IDMA select signal (IS) latches this value into the
1. Host starts IDMA transfer. IDMAA register.
2. Host checks IACK control line to see if the DSP is
Once the address is stored, data can be read from, or written
busy.
to, the ADSP-218xNs on-chip memory. Asserting the
3. Host uses IS and IAL control lines to latch either the select line (IS) and the appropriate read or write line (IRD
DMA starting address (IDMAA) or the PM/DM and IWR respectively) signals the ADSP-218xN that a par-
OVLAY selection into the DSPs IDMA control regis- ticular transaction is required. In either case, there is a one-
ters. If Bit 15 = 1, the value of bits 70 represent the processor-cycle delay for synchronization. The memory
IDMA overlay; bits 148 must be set to 0. If Bit 15 = 0, access consumes one additional processor cycle.
the value of Bits 130 represent the starting address
Once an access has occurred, the latched address is auto-
of internal memory to be accessed and Bit 14 reflects
matically incremented, and another access can occur.
PM or DM for access. Set IDDMOVLAY and
IDPMOVLAY bits in the IDMA overlay register as Through the IDMAA register, the DSP can also specify the
indicted in Table 12. starting address and data format for DMA operation.
4. Host uses IS and IRD (or IWR) to read (or write) DSP Asserting the IDMA port select (IS) and address latch
internal memory (PM or DM). enable (IAL) directs the ADSP-218xN to write the address
onto the IAD140 bus into the IDMA Control Register
5. Host checks IACK line to see if the DSP has completed (Figure 13). If Bit 15 is set to 0, IDMA latches the address.
the previous IDMA operation. If Bit 15 is set to 1, IDMA latches into the OVLAY register.
6. Host ends IDMA transfer. This register, also shown in Figure 13, is memory-mapped
at address DM (0x3FE0). Note that the latched address
(IDMAA) cannot be read back by the host.
When Bit 14 in 0x3FE7 is set to zero, short reads use the
timing shown in Figure 34 on page 37. When Bit 14 in
0x3FE7 is set to 1, timing in Figure 35 on page 38 applies
for short reads in short read only mode. Set IDDMOVLAY
REV. 0 17
ADSP-218xN Series
and IDPMOVLAY bits in the IDMA overlay register as IDMA Port Booting
indicated in Table 12. Refer to the ADSP-218x DSP Hard- ADSP-218xN series members can also boot programs
ware Reference for additional details. through its Internal DMA port. If Mode C = 1, Mode B =
Note: In full memory mode all locations of 4M-byte 0, and Mode A = 1, the ADSP-218xN boots from the IDMA
memory space are directly addressable. In host memory port. IDMA feature can load as much on-chip memory as
mode, only address pin A0 is available, requiring additional desired. Program execution is held off until the host writes
external logic to provide address information for the byte. to on-chip program memory location 0.
18 REV. 0
ADSP-218xN Series
In addition to the programmable flags, ADSP-218xN series if the RESET pin is being used as a method of setting the
members have five fixed-mode flags, FI, FO, FL0, FL1, and value of the mode pins, the effects of an emulator reset must
FL2. FL0FL2 are dedicated output flags. FI and FO are be taken into consideration.
available as an alternate configuration of SPORT1. One method of ensuring that the values located on the mode
Note: Pins PF0, PF1, PF2, and PF3 are also used for device pins are those desired is to construct a circuit like the one
configuration during reset. shown in Figure 14. This circuit forces the value located on
the Mode A pin to logic high, regardless of whether it is
INSTRUCTION SET DESCRIPTION latched via the RESET or ERESET pin.
The ADSP-218xN series assembly language instruction set
has an algebraic syntax that was designed for ease of coding
and readability. The assembly language, which takes full
ERESET
advantage of the processors unique architecture, offers the
RESET
following benefits:
The algebraic syntax eliminates the need to remember ADSP-218xN
cryptic assembler mnemonics. For example, a typical 1k
arithmetic add instruction, such as AR = AX0 + AY0, MODE A/PF0
REV. 0 19
ADSP-218xN Series
Target System Interface Signals
1 2 When the EZ-ICE board is installed, the performance on
GND BG
some system signals changes. Design the system to be com-
3 4
EBG BR patible with the following system interface signal changes
5 6 introduced by the EZ-ICE board:
EBR EINT
7 8 EZ-ICE emulation introduces an 8 ns propagation
KEY (NO PIN) ELIN delay between the target circuitry and the DSP on the
9 10
ELOUT
RESET signal.
ECLK
11 12 EZ-ICE emulation introduces an 8 ns propagation
EE EMS
delay between the target circuitry and the DSP on the BR
13 14
RESET ERESET signal.
TOP VIEW EZ-ICE emulation ignores RESET and BR, when
single-stepping.
Figure 15. Target Board Connector for EZ-ICE
EZ-ICE emulation ignores RESET and BR when in
Pin spacing should be 0.1 0.1 inches. The pin strip header Emulator Space (DSP halted).
must have at least 0.15 inch clearance on all sides to accept EZ-ICE emulation ignores the state of target BR in certain
the EZ-ICE probe plug. modes. As a result, the target system may take control of
the DSPs external memory bus only if bus grant (BG) is
Pin strip headers are available from vendors such as 3M,
asserted by the EZ-ICE boards DSP.
McKenzie, and Samtec.
20 REV. 0
ADSP-218xN Series
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter1 Description Test Conditions Min Typ Max Unit
VIH Hi-Level Input Voltage2, 3 @ VDDEXT = 1.71 to 2.0 V, 1.25 V
VDDINT = max
@ VDDEXT = 2.1 to 3.6 V,
VDDINT = max
VIL Lo-Level Input Voltage2, 3 @ VDDEXT 2.0 V, 0.6 V
VDDINT = min
@ VDDEXT 2.0 V, 0.7 V
VDDINT = min
VOH Hi-Level Output Voltage2, 4, 5 @ VDDEXT = 1.71 to 2.0 V, 1.35 V
IOH = 0.5 mA
@ VDDEXT = 2.1 to 2.9 V, IOH 2.0 V
= 0.5 mA
@ VDDEXT = 3.0 to 3.6 V, IOH 2.4 V
= 0.5 mA
@ VDDEXT = 1.71 to 3.6 V, VDDEXT 0.3 V
IOH = 100 A6
VOL Lo-Level Output Voltage2, 4, 5 @ VDDEXT = 1.71 to 3.6 V, 0.4 V
IOL = 2.0 mA
IIH Hi-Level Input Current3 @ VDDINT = max, 10 A
VIN = 3.6 V
IIL Lo-Level Input Current3 @ VDDINT = max, 10 A
VIN = 0 V
IOZH Three-State Leakage @ VDDEXT = max, 10 A
Current7 VIN = 3.6 V8
IOZL Three-State Leakage @ VDDEXT = max, 10 A
Current7 VIN = 0 V8
IDD Supply Current (Idle)9 @ VDDINT = 1.8 V, 6 mA
tCK = 12.5 ns,
TAMB = 25C
IDD Supply Current (Dynamic)10 @ VDDINT = 1.8 V, 25 mA
tCK = 12.5 ns11,
TAMB = 25C
REV. 0 21
ADSP-218xN Series
ELECTRICAL CHARACTERISTICS (CONTINUED)
TFS1, A131, PF70) and Input only pins (CLKIN, RESET, BR, DR0, DR1,
PWD).
3Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR,
22 REV. 0
ADSP-218xN Series
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-218xN features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor-
mance degradation or loss of functionality.
REV. 0 23
ADSP-218xN Series
Environmental Conditions
REFERENCE
Table 14. Thermal Resistance SIGNAL
tMEASURED
tENA
Mini- tDIS
VOH V OH
LQFP BGA (MEASURED) (MEASURED)
Rating Description 1
Symbol (C/W) (C/W) VOH (MEASURED) 0.5V 2.0V
OUTPUT
Thermal Resistance CA 48 63.3 VOL (MEASURED) + 0.5V 1.0V
VOL VOL
(Case-to-Ambient) tDECAY
(MEASURED)
(MEASURED)
Thermal Resistance JA 50 70.7 OUTPUT STARTS
(Junction-to-Ambient) OUTPUT STOPS DRIVING
DRIVING
Thermal Resistance JC 2 7.4
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
(Junction-to-Case) THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
1Wherethe Ambient Temperature Rating (TAMB) is:
Figure 18. Output Enable/Disable
TAMB = TCASE (PD CA)
TCASE = Case Temperature in C
PD = Power Dissipation in W Output Disable Time
Output pins are considered to be disabled when they have
Test Conditions stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (tDIS) is the difference of tMEASURED and
tDECAY, as shown in Figure 18. The time is the interval from
INPUT 1.5V when a reference signal reaches a high or low voltage level
to when the output voltages have changed by 0.5 V from the
measured output high or low voltage.
2.0V
OUTPUT 1.5V
0.8V The decay time, tDECAY, is dependent on the capacitive load,
CL, and the current load, iL, on the output pin. It can be
Figure 16. Voltage Reference Levels for AC approximated by the following equation:
Measurements (Except Output Enable/Disable)
C L 0.5V
tDECAY = -------------------------
iL
I OL
from which
t DIS = t MEASURED t DECAY
24 REV. 0
ADSP-218xN Series
80
VDDEXT = 3.6V @ 40C
40
SOURCE CURRENT mA
VDDEXT = 2.5V @ +85C
Capacitive Loading
Figure 22 and Figure 23 on page 26 show the capacitive
loading characteristics of the ADSP-218xN.
REV. 0 25
ADSP-218xN Series
1000
VDD = 2.0V
POW ER, INTERNAL 1, 2, 3
60 VDD = 1.9V
55 m W VDD = 1.8V
V D D IN
9V
= 1. 45 m W
45 T
V D D IN V
42 m W = 1 .8
40 V D D IN
T 40 mW
38 mW 1V
= 1 .7
35 34 mW V D D IN T
10
30 30 mW
25
20 0
55 60 65 70 75 80 85 0 25 55 85
1/tCK M Hz TEMPERATURE C
NOTES
POW ER, IDLE 1, 2, 4 1. REFLECTS ADSP-218xN OPERATION IN LOWEST POWER
15.0 MODE. (SEE THE "SYSTEM INTERFACE" CHAPTER OF THE
14.0 ADSP-218x DSP HARDWARE REFERENCE FOR DETAILS.)
13 . 5 m W
13.0 2. CURRENT REFLECTS DEVICE OPERATING WITH NO
V
T
= 2 .0 INPUT LOADS.
12.0 V D D IN 12 m W
POWER (PIDLE) mW
V
= 1 .9 Figure 21. Typical Power-Down Current
11.0 V D D IN T
10 . 5 m W V 10 .5 m W
10.0 = 1 .8
9.5m W V D D IN T
9.0
8 .5 m W = 1.71 V 9m W 30
V D D IN T T = 85 C
8.0 VDD = 0V TO 2.0V
7 .5 m W
7.0 25
RISE TIME (0.4V2.4V) ns
6.0
5.0 20
55 60 65 70 75 80 85
1/tCK M Hz
15
POWER, IDLE n MODES2
12.0
12.0mW 10
10.5mW
10.0
9.5mW
5
POWER (PIDLEn) mW
8.5mW
8.0
VDD COR E = 1.9V
VDD COR E = 1.8V 0
5.2mW 0 50 100 150 200 250 300
6.0
4.9mW CL pF
4.2mW 4.7mW
4.0 3.8mW 4.3mW Figure 22. Typical Output Rise Time vs. Load Capacitance
3.4mW
(at Maximum Ambient Operating Temperature)
2.0
18
0.0
55 60 65 70 75 80 85
16
1/tCK M Hz
VALID OUTPUT DELAY OR HOLD ns
14
NOT ES
VALID F OR ALL TEMPERATURE GRADES. 12
1
POW ER R EFLEC TS D EVIC E O PERATING WITH NO OUT PUT 10
LOAD S.
2 8
TYPICAL POWER D ISSIPATION AT 1.8V O R 1.9V V DDINT AND
25C, EXCEPT WHER E SPECIFIED. 6
3
IDD MEASUREM ENT TAKEN W ITH ALL INSTRUCTIONS 4
EXECU TING FROM INTERNAL MEMO RY. 50% O F THE
INSTRUCTIONS ARE MU LTIFUNCTION (TYPES 1, 4, 5, 12, 13, 2
14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE NOMINAL
INSTRUCTIONS.
4 IDLE R EFERS TO STATE OF OPER ATION DURIN G EXECUTIO N 2
OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO 4
EIT HER V DD OR G ND.
6
0 50 100 150 200 250
CL pF
Figure 20. Power vs. Frequency
Figure 23. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
26 REV. 0
ADSP-218xN Series
Clock Signals and Reset
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
MODE A D
tMS tMH
RESET
tRSP
REV. 0 27
ADSP-218xN Series
Interrupts and Flags
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
28 REV. 0
ADSP-218xN Series
Bus RequestBus Grant
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
CMS, WR, tSD tSEC
IOMS
BG
tSDB
tSE
BGH
tSDBH
tSEH
REV. 0 29
ADSP-218xN Series
Memory Read
CLKOUT
A0A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tRP tRWR
tCRD
D0D23
tRDD tRDH
tAA
WR
30 REV. 0
ADSP-218xN Series
Memory Write
CLKOUT
A0A13
DMS, PMS,
BMS, CMS,
IOMS tWRA
WR
tDW
tWDE
RD
REV. 0 31
ADSP-218xN Series
Serial Ports
CLKOUT
tCC t CC tSCK
SCLK
tSCP
tSCS tSCH tSCP
DR
TFSI N
RFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDE tSCDH
DT
tTDE
tTDV
TFS OUT
ALTERNATE
FRAME
MODE
tRDV
RFSOUT
MULTICHANNEL
MODE,
FRAME DELAY 0 tTDE
(MFD = 0)
tTDV
TFSIN
ALTERNATE
FRAME
MODE
tRDV
RFSIN
MULTICHANNEL
MODE,
FRAME DELAY 0
(MFD = 0)
32 REV. 0
ADSP-218xN Series
IDMA Address Latch
IACK
tIKA tIALD
IAL
tIALP tIALP
IS
IAD150
tIASU tIASU
tIAH tIAH
tIALS
IRD OR
IWR
REV. 0 33
ADSP-218xN Series
IDMA Write, Short Write Cycle
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDH
tIDSU
IAD150 DATA
34 REV. 0
ADSP-218xN Series
IDMA Write, Long Write Cycle
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
IAD150 DATA
REV. 0 35
ADSP-218xN Series
IDMA Read, Long Read Cycle
IACK
tiKHR
tIKR
IS
tIRK
IRD
36 REV. 0
ADSP-218xN Series
IDMA Read, Short Read Cycle
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIRDE tIKDH
IAD150 PREVIOUS
DATA
tiRDV tIKDD
REV. 0 37
ADSP-218xN Series
IDMA Read, Short Read Cycle in Short Read Only Mode
Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode
IA CK
t IK R
t IK H R
IS
tIRP
IRD
tIR D E tIK D H
PR EVIO U S
IAD 15 0
DA TA
t IR D V tIK D D
L EG EN D :
IM P L IE S T H A T IS A N D IR D C A N B E
H EL D IN D E F IN IT EL Y B Y H O ST
Figure 35. IDMA Read, Short Read Cycle in Short Read Only Mode
38 REV. 0
ADSP-218xN Series
LQFP Package Pinout deassertion of RESET. The multiplexed pins DT1/FO,
The LQFP package pinout is shown in the illustration below TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
and in Table 27. Pin names in bold text in the table replace selectable by setting Bit 10 (SPORT1 configure) of the
the plain-text-named functions when Mode C = 1. A + sign System Control Register. If Bit 10 = 1, these pins have serial
separates two functions when either function can be active port functionality. If Bit 10 = 0, these pins are the external
for either major I/O mode. Signals enclosed in brackets [ ] interrupt and flag pins. This bit is set to 1 by default, upon
are state bits latched from the value of the pin at the reset.
94 PF0 [MODE A]
88 PF3 [MODE D]
93 PF1 [MODE B]
89 PF2 [MODE C]
96 PWDACK
98 A1/IAD0
100 A3/IAD2
99 A2/IAD1
90 VDDEXT
PWD
95 BGH
80 GND
92 GND
85 FL2
87 FL0
86 FL1
84 D23
82 D21
77 D17
83 D22
81 D20
79 D19
78 D18
76 D16
97 A0
91
A4/IAD3 1 75 D15
A5/IAD4 2 PIN 1 74 D14
IDENTIFIER
GND 3 73 D13
A6/IAD5 4 72 D12
A7/IAD6 5 71 GND
A8/IAD7 6 70 D11
A9/IAD8 7 69 D10
A10/IAD9 8 68 D9
A11/IAD10 9 67 VDDEXT
A12/IAD11 10 66 GND
A13/IAD12 11 65 D8
GND 12 ADSP-218xN 64 D7/IWR
CLKIN 13 63 D6/IRD
TOP VIEW
XTAL 14 (Not to Scale) 62 D5/IAL
VDDEXT 15 61 D4/IS
CLKOUT 16 60 GND
GND 17 59 VDD INT
VDDINT 18 58 D3/IACK
WR 19 57 D2/IAD15
RD 20 56 D1/IAD14
BMS 21 55 D0/IAD13
DMS 22 54 BG
PMS 23 53 EBG
IOMS 24 52 BR
CMS 25 51 EBR
29
DR1/FI 40
41
IRQL0+PF5 27
GND 28
IRQ2+PF7 30
DT0 31
32
RFS0 33
DR0 34
SCLK0 35
36
DT1/FO 37
TFS1/IRQ1 38
39
SCLK1 42
43
RESET 44
EMS 45
EE 46
ECLK 47
ELOUT 48
ELIN 49
50
IRQE+PF4 26
GND
IRQL1+PF6
ERESET
EINT
VDDEXT
RFS1/IRQ0
TFS0
REV. 0 39
ADSP-218xN Series
Table 27. LQFP Package Pinout Table 27. LQFP Package Pinout (Continued)
40 REV. 0
ADSP-218xN Series
Mini-BGA Package Pinout at the deassertion of RESET. The multiplexed pins
The Mini-BGA package pinout is shown in the illustration DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
below and in Table 28. Pin names in bold text in the table selectable by setting Bit 10 (SPORT1 configure) of the
replace the plain text named functions when Mode C = 1. System Control Register. If Bit 10 = 1, these pins have serial
A + sign separates two functions when either function can port functionality. If Bit 10 = 0, these pins are the external
be active for either major I/O mode. Signals enclosed in interrupt and flag pins. This bit is set to 1 by default upon
brackets [ ] are state bits latched from the value of the pin reset.
12 11 10 9 8 7 6 5 4 3 2 1
PF2 PF1
GND NC D12 D13 NC A9/IAD8 BGH NC WR NC D
[M ODE C] [M ODE B]
V D D E XT PF3 PF0 V D D E XT V D D E XT E
D10 GND GND GND FL 2 FL 0 A8/IAD7
[M ODE D] [M ODE A]
REV. 0 41
ADSP-218xN Series
Table 28. Mini-BGA Package Pinout Table 28. Mini-BGA Package Pinout
(Continued)
42 REV. 0
ADSP-218xN Series
Table 28. Mini-BGA Package Pinout
(Continued)
REV. 0 43
ADSP-218xN Series
OUTLINE DIMENSIONS
Dimensions in outline dimension drawings are shown in millimeters.
144-BALL MINI-BGA
(CA-144)
A1 CO RNER INDEX
10.10 TRI ANG LE
10.00 SQ
9.90 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
8.80 D
BSC E
SQ F
0.80 G
BSC H
BALL J
PITCH K
L
M
1.40
MAX 1.00
0.85
NOTES: 0.43
1. DIMENSIONS IN MILLIMETERS . 0.25
SEATING
2. ACTUAL POSITION OF THE BALL GRID IS 0.55 0.10 PLANE
WITHIN 0.15 OF ITS IDEAL POSITION, RELATIVE 0.50 MAX
TO THE PACKAGE EDGES. 0.45
3. ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 BALL
OF ITS IDEAL POSITION, RELATIVE TO THE DIAMETER
BALL GRID.
4. CENTER DIMENSIONS ARE NOMINAL. DETAIL A
16.20
16.00 SQ
15.80
14.05
14.00 SQ
13.95
1.60 MAX
12.00 TYP BSC
0.75
0.60 TYP
0.50 12 100 76
T YP 1 75
SEATING
PLANE
TO P V IEW
(PINS DOWN)
0.08
MAX LEAD 25 51
COPLANARITY 6 4 26 50
0 - 7
0.50 0.27
0.15 BSC (LEAD PITCH) 0.22 TYP (LEAD WIDTH)
0.05 0.17
NOTES:
1. DIMENSIONS IN MILLIMETERS.
2. THE ACTUAL POSITION OF EACH L EAD IS WITHIN 0.08 OF ITS
IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.
3. CENTER DIMENSIONS ARE NOMINAL.
44 REV. 0
ADSP-218xN Series
ORDERING GUIDE
Ambient
Part Instruction Package Package
Temperature
Number Rate (MHz) Description Option
Range
ADSP-2184NKST-320 0C to 70C 80 100-Lead LQFP ST-100
ADSP-2184NBST-320 40C to +85C 80 100-Lead LQFP ST-100
ADSP-2185NKST-320 0C to 70C 80 100-Lead LQFP ST-100
ADSP-2185NBST-320 40C to +85C 80 100-Lead LQFP ST-100
ADSP-2186NKST-320 0C to 70C 80 100-Lead LQFP ST-100
ADSP-2186NBST-320 40C to +85C 80 100-Lead LQFP ST-100
ADSP-2187NKST-320 0C to 70C 80 100-Lead LQFP ST-100
ADSP-2187NBST-320 40C to +85C 80 100-Lead LQFP ST-100
ADSP-2188NKST-320 0C to 70C 80 100-Lead LQFP ST-100
ADSP-2188NBST-320 40C to +85C 80 100-Lead LQFP ST-100
ADSP-2189NKST-320 0C to 70C 80 100-Lead LQFP ST-100
ADSP-2189NBST-320 40C to +85C 80 100-Lead LQFP ST-100
ADSP-2184NKCA-320 0C to 70C 80 144-Ball MBGA CA-144
ADSP-2184NBCA-320 40C to 85C 80 144-Ball MBGA CA-144
ADSP-2185NKCA-320 0C to 70C 80 144-Ball MBGA CA-144
ADSP-2185NBCA-320 40C to +85C 80 144-Ball MBGA CA-144
ADSP-2186NKCA-320 0C to 70C 80 144-Ball MBGA CA-144
ADSP-2186NBCA-320 40C to +85C 80 144-Ball MBGA CA-144
ADSP-2187NKCA-320 0C to 70C 80 144-Ball MBGA CA-144
ADSP-2187NBCA-320 40C to +85C 80 144-Ball MBGA CA-144
ADSP-2188NKCA-320 0C to 70C 80 144-Ball MBGA CA-144
ADSP-2188NBCA-320 40C to +85C 80 144-Ball MBGA CA-144
ADSP-2189NKCA-320 0C to 70C 80 144-Ball MBGA CA-144
ADSP-2189NBCA-320 40C to +85C 80 144-Ball MBGA CA-144
REV. 0 45
46
47
48
PRINTED IN U.S.A. C02666110/01(0)
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