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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2542278, IEEE
Transactions on Power Electronics
DC Electric Springs A Technology for Stabilizing
DC Power Distribution Systems
Kwan-Tat Mok, Student Member, IEEE, Ming-Hao Wang, Student Member, IEEE, Siew-Chong Tan Senior
Member, IEEE, and S. Y. (Ron) Hui, Fellow, IEEE
AbstractThere is a growing interest in using DC power
systems and microgrids for our electricity transmission and
distribution, particularly with the increasing penetration of pho-
tovoltaic power systems. This paper presents an electric active
suspension technology known as the DC electric springs for
voltage stabilization and power quality improvement. The basic
operating modes and characteristic of a DC electric spring with
different types of serially-connected non-critical loads will first
be introduced. Then, the various power delivery issues of the
DC power systems, namely bus voltage variation, voltage droop,
system fault, and harmonics, are briefly described. The operating
limits of a DC electric spring in a DC power grid is studied. It
is demonstrated that the aforementioned issues can be mitigated
using the proposed DC electric spring technology. Experiment
results are provided to verify the feasibility of the proposed
technology.
KeywordsSmart load, distributed power systems, power elec-
tronics, electric springs, DC grids, smart grid.
I. I NTRODUCTION
The direct current (DC) power systems developed by
Thomas Alva Edison was first adopted in the earliest commer-
cial and residential electric power transmission facility in New
York City in 1882 [1]. However, the DC electric utility service
lasted only for a very short span before been fully replaced by
the alternating current (AC) systems in the 19th century [2].
The reasons for the obsolescence of the DC power systems, on
one hand, were imputed to its inherent disadvantages of high
line losses in the low-voltage transmission and the augment
demand in the use of electric actuators during the second
industrial revolution [3]. On the other hand, the obvious merits
of the AC power systems on low-loss high-voltage power
transmission with the aid of voltage transformers and the
compatibility with induction motors have driven it to fully
dominating the electricity market over the last century.
However, with the recent rising demand for more efficient
and smarter power grids, and the advancement in power
electronic technologies, there is renewed interest in re-adopting
the DC power systems for certain emerging grid applications.
One such applications is the photovoltaic (PV) microgrid sys-
tems. Consider a microgrid facility comprising the photovoltaic
systems, fuel cells, batteries, and other capacitive alternatives
that are inherently of DC nature. The entire system can be fully
The authors are with Department of Electrical and Electronic Engineering,
The University of Hong Kong, Hong Kong. S. Y. R. Hui is also with De-
partment of Electrical and Electronic Engineering, Imperial College London,
U.K.
For future correspondence, please email: sctan@eee.hku.hk.
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VDC1 Rd1 VDC2 Rd2 VDC3 Rd3 VDC4 Rd4 VDC5
ES ES
VDC Rc1 Rc2
Irn1 Rc3 Rc4
Rnc1 Rnc2
Fig. 1. A branch of radial DC network with DC-ES installed.
integrated in the DC form without any DCAC (reciprocally
ACDC) conversion, which improves the total system power
efficiency [4][7]. Furthermore, traditional AC loads such as
induction motors can be made to behave as a DC load when
driven by variable speed drivers [6]. Most modern electronic
loads such as computers, servers in data centers, and light-
emitting diodes require DC power [4], [5], [8][10]. The direct
use of DC power systems can reduce the DCAC and ACDC
power conversion, which consequently offers higher efficiency
and reliability. Compared with AC grids, DC grids do not
require frequency and phase synchronization [6], [9], [11]. All
these advantages are promoting the use of DC grids in indus-
trial power systems [12][14], commercial buildings [15], [16],
residential homes [17], [18], telecommunication buildings
and data centers [19][22], electric vehicles [23], [24], air-
crafts [25], [26], ships [27], [28], spacecrafts [29], and low-
voltage (24 V) ceiling-grid applications [30], [31].
Recently, the integration of distributed generations (DG)
in DC microgrids has been reported in [4], [5], [17], [32]
[34]. The proposed architecture eliminates long transmission
and distribution lines, and consequently reduces transmission
losses, increases reliability, and curtails maintenance cost
and customer price [32]. This configuration can enhance the
scalability, perform remote electrification, and supply continu-
ous power when a voltage sag or blackout occurs in utility
grids [4]. Therefore, it is potentially of higher availability,
power efficiency and power density [33], [34]. However, up to
the present moment, the deficiencies of the DC power systems
such as (i) the power imbalance among power sources and
loads, (ii) the voltage flickers, (iii) the unstable bus voltage
oscillation due to constant power loads, and (iv) the bus voltage
fluctuation due to intermittent renewable energy sources are not
yet fully studied.
The issue of power imbalance among multiple DG sources,
and between sources and loads on DC microgrids has been
reported in [4], [5], [18], [32][36]. The traditional secondary
control (power sharing control) of AC power systems is used
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Transactions on Power Electronics
for the power balancing and the power flow control. Such a
control is inapplicable to DC grids as the power flow in DC
grids are not coupled through the utility frequency [32]. Hence,
alternative control strategies are required in the DC microgrids.
A hierarchical controller that serves as a centralized controller
to coordinate and maintain power balance between sources
and loads has been proposed for the DC microgrids [35].
However, as the hierarchical controller highly relies on the use
of a communication system, it could suffer from reliability
issues of cyber-attacks and possible communication failures.
The voltage droop control is proposed in which a local grid
voltage controller is used in each DG or storage units with
an assigned or predefined voltage droop reference [4], [5],
[32]. Hence, the power delivered to the grid can be shared
among the sources with no or minimal communication links.
This method is adopted in the decentralized control of a DC
microgrid with low bandwidth communication based on the
digital average current sharing technique [32]. However, tight
grid voltage regulation and power sharing ability cannot be
achieved simultaneously when using the droop control. The
gain-scheduling technique is proposed to optimize the droop
gain of each power source [4], [18], [36]. A coordinated droop
control technique can be further implemented on hybrid (AC
and DC) microgrids as reported in [5]. This method can control
the power of the sources in proportion to their power ratings
and it can also manage the power sharing between subgrids.
It is imperative to study and analyze the fault protection and
fault ride through of the DC power systems as the grid voltage
level has to be maintained within an acceptable range during
faults. Arcing-type mechanical circuit breakers are commonly
used in AC power systems. However, when it is applied in
DC grids, the absence of the zero-crossing property of the
DC current makes the current arc hard to be extinguished.
The direct control of the converters current in the process of
controlling the sources and loads allows fault clearance to be
performed [37], [38]. Although there are various studies on
the fault protection in DC microgrids, the research of fault on
the grid voltage dip is still limited.
The stability issues introduced by constant power loads
(CPL) in DC microgrids are also drawing some attentions [6],
[9], [39][44]. The CPL can be considered as a point-of-load
converter paired with a resistor [9]. The negative impedance
(in small-signal sense) of the CPL destabilizes the DC system,
which can be in the form of grid voltage oscillations [39].
Different approaches to eliminate such oscillations, including
load shedding [40], installation of filters [41], [42], and addi-
tion of bulk energy storage devices [43] have been proposed.
The amplitude death solution achieved by delay coupling and
circuit heterogeneity techniques has also been reported [9].
In view of conducting systems level stability analysis, the
Lyapunov linearization method and Brayton-Mosers mixed
potential theory have been proposed for deriving the stability
criterion for DC microgrids with multiple CPL [44].
The concept of electric springs (ES) is first proposed and
implemented in the AC power system for the stabilization
of the grid voltage. So far, three versions of ES have been
developed. The first two versions involve the use of an ES
connected in series with a non-critical load (such as thermal
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Vs
Force F
C Ves
Displacement
x
Non-critical
RNC
Load
(a) Illustration of a mechanical (b) Illustration of an electric spring.
spring.
Fig. 2. Comparison between a mechanical spring and an electric spring.
heaters) [45][48]. Consequently, the ES and the non-critical
load form a smart load that can adaptively consume active and
reactive power according to the intermittent power generation.
The third version of ES can be incorporated into an existing
bidirectional DCAC grid connected inverter commonly used
for solar and wind power systems without association to a non-
critical load [49], [50]. The additional functions of using ES
for stabilizing the voltage and frequency fluctuations, reduction
of energy storage requirements, and improving power quality
in AC power grids have been described in [45][49]. Recent
researches suggest that distributed ES can be more effective
than STATCOM in the voltage control of AC power grid [51].
The advantages of ES in AC power grids have also been
independently verified by other research groups [52][54]. So
far, all reports on ES have been related to the AC power
systems [45][48]. The research on the application of ES in
the DC power systems is limited.
In this paper, the feasibility of using DC electric springs
(DC-ES) for bus voltage stabilization and power balancing in
DC grids is reported. This is possibly the first attempt to use ES
in the regulation of the busbar voltage in a DC microgrid, and
voltage in the DC distribution lines. This work is an extension
of the work presented in [55]. Comparing the above mentioned
voltage control methods [4], [5], [17], [32], [37], where the
control schemes are applied on the power-supply sides, such as
on distributed generations and energy storage systems, the ES
technology is applied directly on the demand side where a non-
critical load participates in the supply-demand power balancing
process. This approach enables the ES-integrated smart load
to perform load shedding and load boosting to achieve the
automatic demand side management.
The DC-ES are serially-connected to a non-critical load as a
smart load. Like AC mains with a specified voltage tolerance,
it is anticipated that full DC power grids will be subjected
to a similarly tight voltage tolerance. Achieving good DC bus
voltage regulation will be necessary for the future DC power
systems. The ES can possibly be used for (i) regulating the
DC bus voltage within the required limits while enduring the
fluctuations of intermittent energy sources or deep voltage sags
due to system faults; and (ii) performing load boosting and
shedding functions to match the power consumption of the
DC loads with the renewable power generation. An example
of a radial DC network is shown in Fig. 1. VDC is the supply
side voltage. Renewable energy sources and DC loads are
connected to the network. It should be noted that the distributed
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Transactions on Power Electronics

Battery Battery
Capacitor
NC Load NC Load Without NC Load

(a) First version of electric springs (b) Second version of electric springs (c) Third version of electric springs
(Series-type without energy storage). (Series-type with energy storage). (Shunt-type with energy storage).
Fig. 3. Different versions of electric springs.

line impedances between any two points on the DC network Distribution Line
must be considered in the analysis. VDC Rd Ld Vbus

II. AC AND DC E LECTRIC S PRINGS

Is Battery
The concept of ES originates from that of mechanical spring. ES Bi-directional Battery
Shown in Fig. 2(a), a force F is exerted on the mechanical Supply Ves Port DC-DC Port
spring with a spring constant k in such a way that the length Side Critical
Voltage Load
of the spring is reduced by x. According to Hookes law, Non-critical Electric Spring
Rc
F = kx (1) Load Ro or Po Vo

A capacitor in the electrical systems can have a similar

behavior as that of a mechanical spring in the mechanical
system. Shown in Fig. 2(b) is a capacitor C that is connected
in series with a non-critical (NC) load. The stability of the
power source voltage level can be regulated by controlling the
amount of charges stored in the capacitor, where
{
CVes inductive mode
q= (2)
CVes capacitive mode
Both mechanical and electric springs are used to stabilize a
system. The most common application of mechanical springs
is for mitigating the vibration of systems such as automotive
vibration dampers [56][58]. On the contrary, ES are primarily
used to stabilize an AC electrical power system and it can be
realized by a DCAC inverter that is connected in series with
an NC load. The fluctuating power of the power system can
be absorbed by adaptively adjusting the power consumption of
the NC load.
So far, three versions of ES have been developed for the
AC power system and they are shown in Fig. 3. The first two
versions of ES are connected in series with NC loads (series-
type ES) to form smart loads that are adaptive to the variation
of power generation, with the first version (ES-1) handling only
reactive power [45] and the second version (ES-2) handling
both active and reactive power [47]. The third version of ES
(ES-3) is incorporated as bi-directional grid-connected ACDC
power converters (shunt-type ES) without association to the
NC loads [49]. The ES-2 and ES-3 require battery storages
to handle the active power as shown in Fig. 3(b) and 3(c),
respectively. Since previous research works are only focused
on the application of ES on AC power systems, this work
studies the possibility on applying the concept of ES on DC
power systems. Seeing that there is no reactive power on DC
Supply Side Demand Side
Fig. 4. The basic configuration of DC electric springs.
networks and hence ES-1 is inapplicable, in this paper, we
propose the use of series-type ES with energy storages (ES-
2) to achieve automatic demand side power management in
DC power systems. With the inclusion of energy storages, ES
can be considered as one type of distributed energy storage
systems. Compared with traditional distributed energy storage
systems which adopt the configuration of a bi-directional
converter that connects the energy storages in shunt to the
power grid, the configuration of the series-type ES involves
an NC load that is in series connection. A reliability issue
exists in that the NC load is not functional if there is a failure
on the DC-ES. Hence, a normal-close output by-pass relay is
connected to the output port of the ES such that the DC-ES
can be by-passed if a fault happens on the power converter of
the DC-ES. The core advantage of the series-type ES over the
traditional distributed energy storage systems is that the energy
capacity required for balancing demand and supply side power
of a power system can be greatly reduced [48]. It is because the
series-type ES can (i) control the amount of power consumed
by the NC load and (ii) manipulate the power level of the
energy storage attached to the DC-ES. The distributed energy
storage systems can only achieve the latter function because
of the absence of the controllability of the NC load power.
The basic configuration of DC electric springs (DC-ES) is
shown in Fig. 4, where the DC-ES is installed in a simple DC
power system with a supply side voltage VDC and a bus voltage
Vbus . A bi-directional DC-DC power converter is adopted as a

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2542278, IEEE
Vbus > 0 0V
Isl
Ves ES Ves ES
Non-critical
Vo Vo
load
0V Vbus < 0
(a) DC-ES installed on positive (b) DC-ES installed on negative
DC bus. DC bus.
Fig. 5. Series-type ES connected to a NC in series.
part of the DC-ES. There are two power ports on that converter,
namely, the ES port and the battery port. The ES port is
connected in series to the NC load and is tied to the bus bar
of the DC network. The battery port is connected to an energy
storage system such as batteries. When there is a fluctuation
on the supply side voltage, the DC-ES can adjust a suitable ES
voltage (Ves ) in such a way that (i) the power consumption of
the NC load adjust adaptively and (ii) the fluctuating energy is
either delivered to or absorbed by the energy storage system
tied to the battery port of the DC-ES. As a result, the demand
side power can follow the fluctuation of the supply voltage in
order to keep the bus voltage to be stable.
III. DC-ES A NALYSIS W ITHOUT C ONSIDERATION OF
D ISTRIBUTION L INE
This section includes an analysis of the characteristics of
DC-ES in different regions of operation. The basic configura-
tions of series-type ES installed on positive and negative DC
buses are shown in Fig. 5(a) and 5(b), respectively. The polarity
definitions of the ES voltage and NC voltage are shown in
the figures. The positive direction of the smart load current
(same as ES current and NC load current) is directed to the
ground level (0 V). Meantime, it is assumed that the DC bus
voltage Vbus is constant and equal to a nominal reference value
Vbus Ref . Hence, the property of distribution lines are not taken
into consideration in this section. Generally, DC NC loads can
be classified into four types, namely,
1. Positive constant-resistive loads,
2. Negative constant-resistive loads,
3. Positive constant-power loads,
4. Negative constant-power loads.
The definition of positive loads implies they are power sinks
and electric power is consumed by the loads. All loads
consuming energy are classified into this category. Conversely,
negative loads represent power sources and electric power is
delivered by the negative loads. Power generators such as
renewable energy sources are classified into this category.
The resistance of constant-resistive loads is unchanged for
any applied voltage. Passive loads such as thermal heaters are
examples of positive constant-resistive loads. For the constant-
power loads, the load power is unchanged for any applied
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Transactions on Power Electronics
voltage. A DCDC switching mode power supply with power
regulation control is a typical example. There are two types of
Isl DC buses (positive or negative) and four types of DC NC loads.
Hence, there are theoretically eight possible configurations of
a smart load. The characteristic and operating regions of these
smart loads will be discussed.
Non-critical
load
A. Constant-Resistive Non-critical Loads Connected to DC-ES
With constant-resistive loads, there are four possible config-
urations ((i) positive load on a positive DC bus, (ii) positive
load on a negative DC bus, (iii) negative load on a positive DC
bus, and (iv) negative load on a negative bus). Consider that
the NC load shown in Fig. 5(a) and 5(b) is a constant-resistive
load of resistance Ro , the relationship among the smart load
current Isl , ES voltage Ves , NC load voltage Vo and DC bus
voltage Vbus is
Vbus = Ves + Vo
(3)
= Ves + Isl Ro
Using (3), the ES power Pes , the NC load power Po , and the
smart load power Psl (summation of the ES power and the NC
load power) can be expressed as
Ves (Vbus Ves )
Pes = Ves Isl = (4)
Ro
(Vbus Ves )
2
Po = Vo Isl = (5)
Ro
and
Vbus (Vbus Ves )
Psl = Vbus Isl = (6)
Ro
Equation (4) indicates that there is a vertex of ES power Pes
when the ES voltage is equal to half of the DC bus voltage.
Hence, the ES receives maximum power at Ves = Vbus /2
with a positive constant-resistive load and delivers maximum
power at Ves = Vbus /2 with a negative constant-resistive
load. Similarly, (5) indicates that there is a vertex of the NC
load power Po when the ES voltage is equal to the DC bus
voltage. Hence, the NC load consumes minimum (zero) power
at Ves = Vbus when its resistance is positive and it delivers
minimum (zero) power at Ves = Vbus when its resistance is
negative. From (6), it is observed that the smart load power Psl
decreases linearly with respect to the ES voltage for positive
constant-resistive load and increases linearly with respect to
the ES voltage for negative constant-resistive load.
It is emphasized that equations (3) (6) are valid for either
positive or negative DC bus voltage and either positive or
negative constant-resistive NC loads. In case of a positive DC
bus voltage and a positive constant-resistive NC load, we have
{
> |Insl | : Ves < 0 or Ves > 2Vbus Ref
|Isl | (7)
< |Insl | : 0 < Ves < 2Vbus Ref
{
> 0 : 0 < Ves < Vbus Ref
Pes (8)
< 0 : Ves < 0 or Ves > Vbus Ref
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Transactions on Power Electronics

4 2 4 2
Region 2 Region 3 Region 4 Region 1 Region 2 Region 3
3 1.5 3 1.5

Smart Load Current (pu)

Smart Load Current (pu)

2 Pnsl 1 2 Region 4 1

1 P 0.5 1 0.5
Power (pu)

Power (pu)
es_max
0 0 0 0
Region 1
1 0.5 1 0.5
Pes_min
2 1 2 P 1
Pes Pes nsl
Isl Isl
3 Po 1.5 3 Po 1.5
Psl Psl
4 2 4 2
1 0.5 0 0.5 1 1.5 2 2.5 3 1 0.5 0 0.5 1 1.5 2 2.5 3
Electric Spring Voltage (pu) Electric Spring Voltage (pu)
(a) Positive constant-resistive loads on positive-voltage DC bus. (b) Negative constant-resistive loads on positive-voltage DC bus.

4 2 4 2
Region 2 Region 3 Region 4 Region 2 Region 3
3 1.5 3 1.5

Smart Load Current (pu)

Smart Load Current (pu)

2 Pnsl 1 2 Region 1 Region 4 1

1 P 0.5 1 0.5
Power (pu)

Power (pu)
es_max Pes_min
0 0 0 0
Region 1
1 0.5 1 0.5
Pnsl
2 1 2 1
Pes Pes
Isl Isl
3 Po 1.5 3 Po 1.5
Psl Psl
4 2 4 2
3 2.5 2 1.5 1 0.5 0 0.5 1 3 2.5 2 1.5 1 0.5 0 0.5 1
Electric Spring Voltage (pu) Electric Spring Voltage (pu)
(c) Positive constant-resistive loads on negative-voltage DC bus. (d) Negative constant-resistive loads on negative-voltage DC bus.
Fig. 6. Characteristics of a smart load implemented by a DC-ES with a constant-resistive non-critical load connected in series.

{
> Pnsl : Ves < 0 or Ves > 2Vbus
Po
< Pnsl : 0 < Ves < 2Vbus Ref
and { power are negative with larger magnitude than that in region
> Pnsl : Ves < 0
Psl
< Pnsl : Ves > 0
where Insl and Pnsl are the nominal smart load current and
nominal smart load power, respectively, and they are calculated
using (3) and (6) with ES being turned off (Ves = 0 V).
Figure 6(a) shows the smart load current, the ES power, the
NC load power, and the smart load power versus the ES voltage
under the per unit base of Vbus , Insl and Pnsl , respectively. The
graph is divided into four regions indicating there are four
modes of operation. In region one, the ES voltage is smaller
than zero. The smart load current is always higher than the
nominal value. The ES power is negative indicating that the ES
is delivering power to the system. The NC load power and the
smart load power are higher than the nominal values. In region
two, the smart load current is smaller than the nominal value.
The ES power is positive, which means the ES is absorbing
power from the system. Both the NC load power and the smart
load power are smaller than their respective nominal value
Pnsl . In region three, the smart load current becomes negative.
Ref The ES power is negative. The NC load power is smaller than
(9) the nominal value. The smart load power is negative. In region
four, the smart load current, the ES power and the smart load
three. However, the NC load power is larger than the nominal
(10) value. Table I summarizes the conditions of the system in those
four regions.
Using the similar approach, different operating regions can
be obtained for the positive constant-resistive NC load with
negative DC bus, the negative constant-resistive NC load with
positive DC bus and the negative constant-resistive NC load
with negative DC bus. The derivation of equations will not
be discussed in this paper and the summaries are shown in
Table II, III and IV and their characteristics are shown in
Fig. 6(b), 6(c), and 6(d), respectively.
B. Constant-Power Non-Critical Loads Connected to DC-ES
Similarly, there are four possible configurations of a smart
load implemented by a DC-ES with a serially-connected
constant-power NC load. Consider that the NC loads shown in
Fig. 5(a) and 5(b) are CPL with a value Po . The relationship
between the smart load current, the ES voltage and the DC
bus voltage is

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Transactions on Power Electronics

4 3 4 3

3 3
Region 3 Region 4 2 Region 1 Region 2 2

Smart Load Current (pu)

Smart Load Current (pu)

2 2
1 1
1 1
Power (pu)

Power (pu)
0 0 0 0

1 1
Region 1 Region 2 1 1
2 2
Pes Pes Region 3 Region 4
Isl 2 Isl 2
3 Po 3 Po
Psl Psl
4 3 4 3
1 0.5 0 0.5 1 1.5 2 2.5 3 1 0.5 0 0.5 1 1.5 2 2.5 3
Electric Spring Voltage (pu) Electric Spring Voltage (pu)
(a) Positive constant-power loads on positive-voltage DC bus. (b) Negative constant-power loads on positive-voltage DC bus.

4 3 4 3

3 3
Region 1 2 2

Smart Load Current (pu)

Smart Load Current (pu)

2 2
1 Region 1 1
1 1
Power (pu)

Power (pu)
Region 2 Region 3
0 0 0 0
Region 2 Region 3
1 1
1 1
2 2
Pes Region 4 Pes Region 4
Isl 2 Isl 2
3 Po 3 Po
Psl Psl
4 3 4 3
3 2.5 2 1.5 1 0.5 0 0.5 1 3 2.5 2 1.5 1 0.5 0 0.5 1
Electric Spring Voltage (pu) Electric Spring Voltage (pu)
(c) Positive constant-power loads on negative-voltage DC bus. (d) Negative constant-power loads on negative-voltage DC bus.
Fig. 7. Characteristics of a smart load implemented by a DC-ES with a constant-power NC load connected in series.

{
> 0 : 0 < Ves < Vbus Ref
Pes (15)
Vbus = Ves + Vo < 0 : Ves < 0 or Ves > Vbus Ref

Po (11)
= Ves + and
Isl {
> Pnsl : 0 < Ves < Vbus Ref
Using (3), the ES power and the smart load power can be Psl (16)
< Pnsl : Ves < 0 or Ves > Vbus Ref
expressed as
Figure 7(a) shows the smart load current, ES power, NC load
Ves Po power and smart load power versus ES voltage under the per
Pes = (12)
(Vbus Ves ) unit base of Vbus Ref , Po and Insl , respectively. Insl is the
nominal smart load current calculated using (11) when Ves =
and 0 V. The graph is divided into four regions indicating there
Vbus Po are four modes of operations. In region one, the ES voltage
Psl = (13) is smaller than zero. The smart load current is always smaller
(Vbus Ves )
than the nominal value Insl . The ES power is negative, which
Equations (11) (13) are valid for either positive or negative means the ES is delivering power to the system. In region two,
DC bus voltage and either positive or negative constant-power the smart load current is greater than the nominal value Insl .
NC loads. In the case of positive DC bus voltage and positive The ES power is positive, which means the ES is absorbing
constant-power NC load, we have power from the system. The smart load power is larger than
the nominal value Po . In region three and four, both the ES
{ power and the smart load power are negative. The smart load
> |Insl | : 0 < Ves < 2Vbus Ref
|Isl | (14) current becomes negative, with the magnitude larger than the
< |Insl | : Ves < 0 or Ves > 2Vbus Ref nominal smart load current in region three and smaller than

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Transactions on Power Electronics

TABLE I. M ODES OF O PERATION OF DC-ES ON P OSITIVE DC B US TABLE VIII. M ODES OF O PERATION OF DC-ES ON N EGATIVE DC
WITH A P OSITIVE C ONSTANT-R ESISTIVE NC L OAD B US WITH A N EGATIVE C ONSTANT-P OWER N ON - CRITICAL L OAD
Region Ves range |Isl | Pes Po Psl Region Ves range |Isl | Pes Psl
1 Ves < 0 > |Insl | <0 > Pnsl > Pnsl 1 Ves < 2Vbus Ref < |Insl | > 0 > Pnsl
2 0 < Ves < Vbus Ref < |Insl | >0 < Pnsl < Pnsl 2 2Vbus Ref < Ves < Vbus Ref > |Insl | > 0 > Pnsl
Vbus Ref < Ves 3 Vbus Ref < Ves < 0 > |Insl | < 0 < Pnsl
3 < |Insl | <0 < Pnsl < Pnsl
and Ves < 2Vbus Ref 4 0 < Ves < |Insl | > 0 > Pnsl
4 2Vbus Ref < Ves > |Insl | <0 > Pnsl < Pnsl

TABLE II. M ODES OF O PERATION OF DC-ES ON P OSITIVE DC B US

WITH A N EGATIVE C ONSTANT-R ESISTIVE NC L OAD Similarly, the various modes of operations can be obtained
for the positive constant-power NC load with negative DC bus,
Region Ves range |Isl | Pes Po Psl
the negative constant-power NC load with positive DC bus
1 Ves < 0 > |Insl | >0 < Pnsl < Pnsl and the negative constant-power NC load with negative DC
2 0 < Ves < Vbus Ref < |Insl | <0 > Pnsl > Pnsl
Vbus Ref < Ves bus. The summaries are shown in Table VI, VII and VIII and
3 < |Insl | >0 > Pnsl > Pnsl
and Ves < 2Vbus Ref their characteristics are shown in Fig. 7(b), 7(c), and 7(d),
4 2Vbus Ref < Ves > |Insl | >0 < Pnsl > Pnsl respectively.
TABLE III. M ODES OF O PERATION OF DC-ES ON N EGATIVE DC B US
WITH A P OSITIVE C ONSTANT-R ESISTIVE NC L OAD IV. I SSUES ON DC P OWER S YSTEMS
Region Ves range |Isl | Pes Po Psl The previous analysis assumes that the DC bus voltage
1 Ves < 2Vbus Ref > |Insl | <0 > Pnsl < Pnsl is constant. In a practical DC power system, the DC bus
2
2Vbus Ref < Ves
< |Insl | <0 < Pnsl < Pnsl voltage is disturbed and the DC-ES will regulate the DC bus
and Ves < Vbus Ref
3 Vbus Ref < Ves < 0 < |Insl | >0 < Pnsl < Pnsl
voltage within the permitted limits. This section is focused
4 0 < Ves > |Insl | <0 > Pnsl > Pnsl on identifying the possible issues related to DC bus voltage
disturbance. The DC power system shown in Fig. 1 can be
TABLE IV. M ODES OF O PERATION OF DC-ES ON N EGATIVE DC B US considered as a simplified model of a practical DC power
WITH A N EGATIVE C ONSTANT-R ESISTIVE NC L OAD system. There are several non-ideal factors that exist in the
Region Ves range |Isl | Pes Po Psl system. First, parasitic resistances exist along distribution lines.
1 Ves < 2Vbus Ref > |Insl | >0 < Pnsl > Pnsl Second, the DC source VDC is a finite power source. Third,
2
2Vbus Ref < Ves
< |Insl | >0 > Pnsl > Pnsl
loads on the DC bus can introduce harmonic disturbance into
and Ves < Vbus Ref the bus. Fourth, equipment or system faults can happen. By
3 Vbus Ref < Ves < 0 < |Insl | <0 > Pnsl > Pnsl
4 0 < Ves > |Insl | >0 < Pnsl < Pnsl
considering these factors, different types of disturbances on
the DC bus voltage are possible and will be discussed. The
TABLE V. M ODES OF O PERATION OF DC-ES ON P OSITIVE DC B US DC-ES is to alleviate the effects of these disturbances which
WITH A P OSITIVE C ONSTANT-P OWER N ON - CRITICAL L OAD may affect the voltage stability of the DC bus.
Region Ves range |Isl | Pes Psl
1) Unstable DC Bus Voltage: The DC bus voltage level
1 Ves < 0 < |Insl | < 0 < Pnsl
varies with time as shown in Fig. 8(a). The causes of the
2 0 < Ves < Vbus Ref > |Insl | > 0 > Pnsl variation include (i) unstable supply side voltage, (ii) inter-
3 Vbus Ref < Ves < 2Vbus Ref > |Insl | < 0 < Pnsl mittency of renewable energy sources, and (iii) load power
4 2Vbus Ref < Ves < |Insl | < 0 < Pnsl variation [45]. The time-scale of the variation can vary widely.
2) Droop Effect: Due to the presence of distribution line
TABLE VI. M ODES OF O PERATION OF DC-ES ON P OSITIVE DC B US impedance, there is voltage drop along the distribution net-
WITH A N EGATIVE C ONSTANT-P OWER N ON - CRITICAL L OAD
work. Hence, the voltage level at each point of the DC bus is
Region Ves range |Isl | Pes Psl different. The droop effect will increasingly reduce the voltage
1 Ves < 0 < |Insl | > 0 > Pnsl level as the distribution line point moves further away from
2 0 < Ves < Vbus Ref > |Insl | < 0 < Pnsl the power source. Moreover, the voltage drop varies with
3 Vbus Ref < Ves < 2Vbus Ref > |Insl | > 0 > Pnsl
4 Vbus < Ves < |Insl | > 0 > Pnsl
the loading condition. As shown in Fig. 8(b), a heavy load
condition can pull down the voltage level at certain location
TABLE VII. M ODES OF O PERATION OF DC-ES ON N EGATIVE DC of the network below the allowable limits, whereas there is no
B US WITH A P OSITIVE C ONSTANT-P OWER N ON - CRITICAL L OAD such issue with a light load. Note that in AC power systems,
Region Ves range |Isl | Pes Psl
the droop effect can be mitigated using distributed capacitors
to provide reactive power support. However, this approach
1 Ves < 2Vbus Ref < |Insl | < 0 < Pnsl
2 2Vbus Ref < Ves < Vbus Ref > |Insl | < 0 < Pnsl cannot be applied on DC power systems. Various droop control
3 Vbus Ref < Ves < 0 > |Insl | > 0 > Pnsl schemes have been proposed [4], [5], [32], in which the control
4 0 < Ves < |Insl | < 0 < Pnsl approaches make use of this droop effect to control the power
sharing among distributed power sources while the bus voltage
level is maintained within the allowable limits.
that in region four. Table V summarizes the conditions of the 3) Equipment or System Fault: The voltage level on the
system in these three regions. DC bus can suddenly drop if there is a short circuit due to

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Power Generation Connected with

renewables
Vbus Vbus
Vbus;max
Vbus;max
Vbus;min
Vbus;min

O
Light Load Condition
Location
O
Time Heavy Load Condition
(a) An unstable DC bus voltage. (b) Droop effect of a radial DC network due to the existence of
distribution line resistance.
Vbus
Vbus
Vbus;max
Vbus;max
Vbus;min
Vbus;min

O
System Fault Time O
fault Clear Tac Time
(c) A sudden DC bus voltage drop caused by equipment or system (d) DC bus voltage with substantial harmonic component.
faults.
Fig. 8. Different issues in DC power systems.

equipment or system faults [37], [38], as illustrated in Fig. 8(c). the DC-ES voltage and the DC source voltage for different
When a fault occurs, there will be an instantaneous voltage types of smart loads, and (ii) determining the operating limits
drop on the DC bus, which may exceed the allowable minimum of the DC-ES in a given set of system specifications.
level. The fault will be cleared by pre-designed protection Consider the DC electrical system shown in Fig. 4, of which
circuits that isolate the fault location. Once returning to normal, the distribution line inductance Ld is neglected in the following
the DC bus voltage level will be higher than the nominal value steady-state analysis. There is a distribution resistance Rd
as part of the loads would have been disconnected from the between the supply side and the load side. The load side power
DC bus. Pbus , which is the summation of the smart load power Psl and
4) Harmonic Issue: Harmonic noise can be generated by the critical load power Pc = Vbus 2 /Rc , is
loads or power sources [59], [35]. For instance, an AC motor
driving circuit implemented by power inverter connected to a Pbus = Vbus Ibus = Psl + Pc (17)
DC bus can inject harmonic current into the DC system with
a harmonic frequency double the synchronous frequency of Using (17), the supply side voltage is
the motor. In addition, a power rectifier connected to the DC
Rd
power system can inject harmonic currents at twice the utility VDC = Vbus + Rd Is = Vbus + (Psl + Pc ) (18)
frequency. Figure 8(d) shows a DC bus voltage containing a Vbus
substantial harmonic components with frequency of 1/Tac . If In practice, the permitted range of the ES voltage will be
the amplitude of harmonic content is too large, the ripple on bounded by the given rated ES voltage, the rated smart load
the DC bus can exceed the voltage limits of the busbar. current and the allowable range of the NC voltage. They are
V.DC-ES A NALYSIS W ITH C ONSIDERATION OF Ves rated min Ves Ves rated max
D ISTRIBUTION L INE R ESISTANCE Vo rated min Vo Vo rated max (19)
The analysis here considers the distribution line resistances Isl rated min Isl Isl rated max
of the system and the practical operating range of the DC-
ES, which is limited by its electrical specifications and the The permitted range of the ES voltage can be found using the
operating limits of the NC load. Thus, the ability of the DC- constraint in (19) and can be expressed as
ES in regulating the busbar voltage is limited. This section is
focused on (i) analyzing the variation of the DC bus voltage, Ves min Ves Ves max (20)

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Transactions on Power Electronics

TABLE IX. T HE POLARITY OF THE FIRST PARTIAL DERIVATIVE OF

SUPPLY SIDE VOLTAGE WITH A CONSTANT- RESISTIVE NC LOAD
VDC min VDC VDC max , the DC bus voltage is regulated
to Vbus Ref by the DC-ES. Hence, the DC bus voltage can be
Vbus Ro VDC /Ves
expressed as
Positive Positive Negative
Positive Negative Positive
Negative Positive Positive
f1 (Rd , Rc , Ro , Ves min , VDC ) : VDC < VDC min
Negative Negative Negative Vbus = Vbus Ref : VDC min VDC VDC max

f1 (Rd , Rc , Ro , Ves max , VDC ) : VDC > VDC max

Once the permitted range of the ES voltage is found, the (26)

operating limits of the system can be analyzed in two parts: (i) Equation (26) suggests that the DC bus voltage changes with
using a constant-resistive NC load and (ii) using a constant- respect to VDC and can be represented as a piecewise function
power NC load. Here, it is assumed that the DC-ES is operated of VDC . When VDC < VDC min , the DC bus voltage drops be-
with a suitable control to regulate the DC bus voltage to low Vbus Ref . When VDC min VDC VDC max , the DC bus
Vbus Ref and the ES is within the range defined in (20). voltage will be regulated to Vbus Ref . When VDC > VDC max ,
the DC bus voltage rises above Vbus Ref .
The ES voltage changes with VDC and it can be expressed
A. Constant-Resistive Non-Critical Load quantitatively by rearranging (21) as
If the NC load is constant-resistive, by using (6) and (18),
the supply side voltage can be expressed as Ves = f2 (Rd , Rc , Ro , Vbus , VDC )
[ ] [ ( ) ]
Rd Vbus (Vbus Ves ) Ro Rc Rd + Rd Ro (27)
VDC = Vbus + + Pc (21) = Vbus 1 + VDC
Vbus Ro Rd Ro Rc

The first-order partial derivative of the supply side voltage with From (23), (24) and (27), the ES voltage can be represented
respect to the ES voltage is VDC /Ves = (Rd Vbus )/Ro , as
which is dependent on Rd , Ro and Vbus and independent of
Ves . This implies the supply side voltage changes monotoni-
Ves max : VDC < VDC min


cally and linearly with the ES voltage. Table IX summarizes f2 (Rd , Rc , Ro , Vbus Ref , VDC ) : VDC min VDC ,
the four conditions. Ves =

VDC VDC max
The following discussion is based on a positive constant-
Ves min : VDC > VDC max
resistive NC load (Ro > 0 ) with positive supply side voltage
(Vbus > 0V). The operating ES voltage limits can be derived (28)
from (3) and (19) as Equation (28) shows that Ves changes with VDC and can
be represented as a piecewise function of VDC . When the
Ves rated min Ves Ves rated max VDC < VDC min , the ES voltage reaches its maximum
Vbus Vo rated max Ves Vbus Ref Vo rated min
Ref Ves max . When VDC min VDC VDC max , the ES voltage
Vbus Ref Ro Isl rated max Ves Vbus Ref Ro Isl rated min changes according to (27) with Vbus = Vbus Ref . When
(22) VDC > VDC max , the ES voltage reaches its minimum Ves min .
From (21) and Table IX, VDC /Ves < 0 and the supply Equation (26) and (28) can be used to predict the value of DC
side voltage decreases monotonically with the ES voltage. bus voltage and ES voltage when a positive constant-resistive
Hence, the minimum and maximum supply side voltage levels NC is used.
that allow the DC bus voltage to be maintained at Vbus Ref
when using the DC-ES with the constraint defined in (22) are
respectively B. Constant-Power Non-Critical Load
[ ]
Rd Vbus (Vbus Ves,max ) With a constant-power NC load and according to (13) and
VDC min = Vbus + + Pc (23) (18), the supply side voltage can be expressed as
Vbus Ro
and [ ]
[ ] Rd Vbus Po Vbus 2
VDC = Vbus + + (29)
Rd Vbus (Vbus Ves,min ) Vbus (Vbus Ves ) Rc
VDC max = Vbus + + Pc (24)
Vbus Ro
The partial derivative of supply side voltage with respect to the
By rearranging (21), we have 2
ES voltage is VDC /Ves = (Rd Po )/((Vbus Ves ) ), which
Vbus = f1 (Rd , Rc , Ro , Ves , VDC ) implies that the supply side voltage increases monotonically
( ) with ES voltage when Po > 0, and vice versa.
Ro Rc Rd Ves (25)
= VDC + The following discussion uses the positive constant-power
Ro Rc + Rc Rd + Rd Ro Ro
NC load as an example. This leads to VDC /Ves > 0 and
From (23), (24) and (25), VDC = VDC min when Ves = Ves max the supply side voltage increases monotonically with the ES
and VDC = VDC max when Ves = Ves min . Also, when voltage. Since Po > 0 W and Vbus > 0 V, the operating ES

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10

voltage limits can be derived from (11) and (19) as a half-bridge inverter1 that is shown in Fig. 9 and is controlled
by a low-cost commercial digital signal processing controller
Ves rated min Ves Ves rated max TMS320F28069 (Texas Instruments Inc.). The actual experi-
Vbus Ref Vo rated max Ves Vbus Ref Vo rated min ment setup is shown in Fig. 10. Since the DC-ES is connected
to an NC load in series, a control circuitry is required for
Vbus Ref Ro Isl rated max Ves Vbus Ref Ro Isl rated min the DC-ES to handle the reliability issues of the ES-integrated
(30) smart load. The circuitry is used to ensure that (i) the NC load
Hence, the minimum and maximum supply side voltage that can bypass the ES and is directly tied to the DC bus in the
allows the DC bus voltage to be maintained at Vbus Ref within event of a fault in the DC-ES and that (ii) an emergency shut-
the constraints defined in (30) are respectively down mechanism can be activated automatically to minimize
[ ] the damage of the DC-ES. A bypass relay SWbp is connected
Rd Vbus Po Vbus 2 across the ES port of the DC-ES as shown in Fig. 9. The relay
VDC min = Vbus + + (31) is closed during the deactivation of the DC-ES.
Vbus (Vbus Ves min ) Rc
Regarding the protection issue of the DC-ES, the emergency
and shut-down mechanism as shown in Fig. 11 involves four digital
input signals (F AU LT , RLY CT RL, P W M H CT RL and
[ ] P W M L CT RL) and three digital output signals (RLY ,
Rd Vbus Po Vbus 2
VDC max = Vbus + + (32) P W M H and P W M L). The input signal P W M H CT RL
Vbus (Vbus Ves max ) Rc and P W M L CT RL are the complimentary PWM signals
used to control the high-side MOSFET S1 and low-side MOS-
The DC bus voltage can be expressed by rearranging (29) as FET S2 of the bi-directional half-bridge converter. The input
shown in (33). signal RLY CT RL is used to control the status of the bypass
From (31), (32) and (33), VDC = VDC min when Ves = reply SWbp . The output signal P W M H, P W M L and RLY
Ves min and VDC = VDC max when Ves = Ves max . Then, the are the corresponding signals after handling the emergency
DC bus voltage can be expressed as shut-down mechanism. The signal F AU LT is the indication
of the existence of a fault in the DC-ES that is triggered by

f3 (Rt , Rc , Ro , Ves min , VDC ) : VDC < VDC min the protection circuit. This fault signal is in logic zero status
Vbus = Vbus Ref : VDC min VDC VDC max during the normal operation. When there is a fault on the

f3 (Rt , Rc , Ro , Ves max , VDC ) : VDC > VDC max DC-ES, such as ES port over-voltage and battery port under
voltage, the signal F AU LT is in logic one status. Figure 12
(34) shows the operating waveforms of the digital control signals
The ES voltage can be expressed by rearranging (29) as involved. During the deactivation of the DC-ES, RLY CT RL
is in logic zero status such that the DC-ES is bypassed and
Ves = f4 (Rd , Rc , Ro , Vbus , VDC ) the NC load is directly connected to the DC bus. After the
(Rc Vbus )VDC + (Rc Vbus 2 + Rd Vbus 2 + Po Rc Rd ) activation of the DC-ES, RLY CT RL is in logic one status
= and the complimentary PWM signals are delivered to S1 and
(Rc )VDC + (Rc Vbus + Rd Vbus )
(35) S2 through the signal P W M H CT RL and P W M L CT RL.
When a fault occurs, the signal F AU LT is in logic one status
such that the signal P W M H and P W M L will set low and
From (31), (32) and (35), the ES voltage is
the relay SWbp is closed. It is noted that the PWM signal
P W M H and P W M L should be set low before the closing of

Ves min : VDC < VDC min the relay SWbp . This prevents a short circuit condition which

f4 (Rd , Rc , Ro , Vbus : VDC min VDC ,
Ref , VDC ) will damage MOSFET S1 and S2 . The time delay generated
Ves =

VDC VDC max by the RC delay circuit as shown in Fig. 11 should be higher

Ves max than the propagation delay of the isolation gate driver circuit
: VDC > VDC max
as shown in Fig. 9. Here, the time delay generated is set as
(36)
3.65 s while the propagation delay is measured as 2.0 s.
Equation (34) and (36) can be used to predict the values of
The experiment is divided into three parts. Part one verifies
DC bus voltage and ES voltage when a positive constant-power
the analysis of the operating limits of the DC-ES as explained
NC is used.
1 Note that with the half-bridge topology acting as a DC-ES, there is
potentially a problem with the battery management in that the energy charged
to the upper side (BAT 1) and low side (BAT 2) of the battery bank is
VI. E XPERIMENT R ESULTS not balanced during the operation of the DC-ES. BAT 1 is discharged and
BAT 2 is charged when the DC-ES delivers a positive output voltage. This is
The objectives of the following experiments are to demon- conversely true when it delivers a negative output voltage. In an actual DC-
ES product adopting the half-bridge topology, a specialized charge-balance
strate different modes of the DC-ES operation and to validate control scheme would be required in the battery management system. On the
the operating limits of a DC-ES in a given system against other hand, the issue is easily resolved with the use of the full-bridge inverter
the theoretical derivations. The DC-ES is implemented using as the DC-ES.

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11

TABLE X. S YSTEM S PECIFICATIONS OF THE E XPERIMENT IN PART

O NE WITH A C ONSTANT-R ESISTIVE NC L OAD
Description Parameter Value
Nominal DC bus voltage Vbus Ref 48 V
Distribution line resistance Rd 0.37
Critical load resistance Rc 14.05
Non-critical load resistance Ro 15.128
Rated ES minimum voltage Ves rated min 60 V
Rated ES maximum voltage Ves rated max 60 V
Rated smart load minimum current Isl rated min 12 A
Rated smart load maximum current Ies rated max 12 A
Rated non-critical load minimum voltage Vo rated min 60 V
Rated non-critical load maximum voltage Vo rated max 60 V

A. Part One Operating Limits of DC-ES

The electrical block diagram of the experiment setup is
shown in Fig. 4. The nominal DC bus voltage is Vbus Ref =
48 V. In this experiment, the DC source voltage VDC is varied.
Fig. 10. The actual experiment setup.
The ES voltage Ves and the DC bus voltage Vbus are recorded.
Both constant-resistive and constant-power NC loads are used
FAULT in this experiment.
1) Positive Constant-Resistive Non-Critical Load: The spec-
RLY ifications of the experiment is shown in Table X. Substituting
RLY_CTRL the parameters shown in Table X into (22) yields
PWMH
PWMH_CTRL 24V Ves 60V (37)
PWML which implies Ves min =24 V and Ves max = 60 V. The min-
PWML_CTRL
imum and the maximum supply side voltage that the DC bus
can still be regulated to the nominal value (Vbus Ref = 48 V)
Fig. 11. The schematic diagram of the emergency shut-down control. can be derived from (23) and (24), which gives VDC,min =
48.97 V and VDC,max = 51.03 V. The predicted values of the
DC bus voltage and the ES voltage can be derived from (26)
PWML_CTRL
and (28). Therefore,


1.05VDC + 1.54 : VDC < 48.97 V
GL
Vbus = 48 V : 48.97 VDC 51.03 V

1.05VDC 0.62 : VDC > 51.03 V
RLY
(38)
and
Gate driver delay

FAULT RC circuit delay

60 V : VDC < 48.97 V
Ves = 40.89V DC + 206.22 : 48.97 VDC 51.03 V

24 V : VDC > 51.03 V
(39)
Fig. 12. Waveforms of the emergency shut-down circuit. The experiment is to verify the predicted values of Vbus
and Ves using (38) and (39). During the experiment, the DC
source voltage is adjusted from 48 V to 52 V and the DC-ES
in Section V. Part two demonstrates the functionality of the is turned on to regulate the DC bus voltage. The calculated
DC-ES in regulating the DC bus voltage as discussed in and experiment results are shown in Fig. 13, in which the the
Section IV-1. Part three demonstrates the use of the DC-ES experiment data are marked as Vbus and Ves . The experiment
for alleviating the droop effect as described in Section IV-2. results are in good agreement with the analytical ones.

Vbus = f3 (Rd , Rc , Ro , Ves , VDC )

2
Rc VDC + Rc Ves + Rd Ves (Rc VDC + Rc Ves + Rd Ves ) 4(Rc + Rd )(Rc VDC Ves + Rd Rc Po ) (33)
=
2(Rc + Rd )

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Transactions on Power Electronics

12

Rd
Vbus DC Bus
VBAT
IRFP31N50L
VOH Lo C1 62
VDC GH S1

...

...
600 H 1500 F BAT1
12 V SWbp
Ves Co
140 F
VOL
Rc
IRFP31N50L 62
C2

...

...
Ro or Po GL S2 1500 F BAT2
Vo

Power Ground
Power Stage ES Ground

12 V VBAT
1 k 1N5819 GH
1 NC V+ 8 VOH
12 V
2 LD1 OUT 7 FAULT Protection

100 nF

100 F

4.7 k
3 LD2 OUT 6 47 Circuit VOL
1N4007 PWMH 1N4148 4 NC GND 5

TLP250
240 1 k
2N2222
12 V
12 V URF108
1 k
FAULT
2N2222 1N4148 RLY 1 NC V+ 8 1N5819 GL RLY
2 LD1 OUT 7 RLY_CTRL
3 LD2 OUT 6 Emergency
1 k
PWMH
100 F

100 nF

4.7 k
4 NC GND 5 47 Shutdown PWMH_CTRL
PWML 1N4148 Circuit
TLP250 PWML
2N2222 PWML_CTRL
1 k
5 V 1 nF TES 1-0521
5V 5 V(ISO1)
VIN VIN
GND1 GND2 1 F
TMS320F28069 Piccolo
20 k
1 F 19 k VOH
DSP Control Card 10 k 5 V 5 V(ISO1)
ADC 20 k 1 k
10 k
(Sensed ES Voltage) VOL
OPA2350
GPIO
RLY_CTRL (Relay Control) 1 nF ISO 124U
PWMH_CTRL PWM1A 5 V 1 nF TES 1-0521
5V 5 V(ISO2)
VIN VIN
PWML_CTRL PWM1B GND1 GND2 1 F
20 k
1 F 19 k
10 k 5 V 5 V(ISO2) VOH
Switching frequency fs ADC
Operated at 20 kHz (Sensed Bus Voltage) 20 k 1 k
OPA2350 10 k

1 nF ISO 124U
Control Stage

Fig. 9. The full schematic diagram of the DC-ES used in the experiment.

2) Positive Constant-Power Non-Critical Load: The predicted values of the DC bus voltage can be derived from
constant-power NC load is implemented using a DCDC (34), which is shown in (41).
buck converter with its input port connected in series with There are two set of possible solutions in (33). One of
the DC-ES while its output port is connected to an electronic them is far from the nominal DC bus voltage and is therefore
load. The specifications of the experiment are shown in neglected. The ES voltage can be derived from (36). Hence,
Table XI. Substituting these parameters into (30) yields


10 V : VDC < 50.04 V
24 V Ves 10V (40) 699VDC 3.4104
Ves = 14VDC 700 : 50.04 VDC 50.73 V

24 V
which implies that Ves min = 24 V and Ves max = 10 V. : VDC > 50.73 V
The minimum and the maximum supply side voltage that (42)
the DC bus can still be regulated to the nominal value The experiment is similar to that in Section VI-A1, but the DC
(Vbus Ref = 48 V) can be determined according to (31) and source voltage is adjusted from 49 V to 52 V. The calculated
(32), as VDC,min = 50.04 V and VDC,max = 50.73 V. The and experiment results are shown in Fig. 14 and they are in

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Transactions on Power Electronics

13

Vdc min Vdc max Vdc min Vdc max

49 65 49 20
60
55 Vbus 15
48.75 48.75

50 Ves
Vbus 45 Vbus 10
48.5 Ves 40 48.5
Ves 5
Vbus 35
DC Bus Voltage (V)

DC Bus Voltage (V)

48.25 30 48.25
Ves

ES Voltage (V)

ES Voltage (V)
0
25
20
48 48 5
15
10
10
47.75 5 47.75
0 15
47.5 5 47.5
10 20
15
47.25 47.25
20 25
25
47 30 47 30
48 48.25 48.5 48.75 49 49.25 49.5 49.75 50 50.25 50.5 50.75 51 51.25 51.5 51.75 52 49 49.25 49.5 49.75 50 50.25 50.5 50.75 51 51.25 51.5 51.75 52
Power Source Voltage (V) Power Source Voltage (V)

Fig. 13. Experiment results of the system under an unstable supply side Fig. 14. Experiment results of the system under an unstable supply side
voltage variation with a constant-resistive non-critical load. Vbus : calculated voltage variation with a constant-power non-critical load. Vbus : calculated DC
DC bus voltage; Ves : calculated ES voltage; Vbus : measured DC bus voltage; bus voltage; Ves : calculated ES voltage; Vbus : measured DC bus voltage;
Ves : measured ES voltage. Ves : measured ES voltage.

TABLE XI. S YSTEM S PECIFICATIONS OF THE E XPERIMENT IN PART TABLE XII. S YSTEM S PECIFICATIONS OF THE E XPERIMENT IN PART
O NE WITH A C ONSTANT-P OWER NC L OAD T WO
Description Parameter Value Description Parameter Value
Nominal DC bus voltage Vbus Ref 48 V Nominal DC bus voltage Vbus Ref 48 V
Distribution line resistance Rd 0.37 Distribution line resistance Rd 0.33
Critical load resistance Rc 14.05 Critical load resistance Rc 14
Non-critical load power Po 150.78 W Constant-resistive NC load resistance Ro 15.6
Rated ES minimum voltage Ves rated min 60 V Constant-power NC load power Po 147 W
Rated ES maximum voltage Ves rated max 60 V ES minimum voltage (for Ro ) Ves min 24 V
Rated smart load minimum current Isl rated min 0A ES maximum voltage (for Ro ) Ves max 60 V
Rated smart load maximum current Ies rated max 12 A ES minimum voltage (for Po ) Ves min 24 V
Rated non-critical load minimum voltage Vo rated min 38 V ES maximum voltage (for Po ) Ves max 10 V
Rated non-critical load maximum voltage Vo rated max 72 V

1) Positive Constant-Resistive Non-Critical Load: The spec-

good agreement.
ifications of the experiment is shown in Table XII. The nominal
DC source voltage can be derived from
B. Part Two Unstable Supply Voltage
This experiment verifies the use of DC-ES in regulating (Ro //Rc ) + Rd
VDC nom = Vbus Ref (44)
the DC bus voltage as discussed in Section IV-1. The system (Ro //Rc )
configuration is shown in Fig. 9, of which the DC voltage
as VDC nom = 50.18 V.
source VDC is replaced by a programmable DC power source.
Such a power source is programmed with a fluctuating voltage The experiment is divided into two parts. In the first part,
to simulate the unstable supply side voltage source, which is the DC-ES is turned off and the supply side voltage with a
expressed as fluctuating profile is applied to the DC system for 200 seconds.
VDC = VDC nom + VDC (43) In the second part, the DC-ES is activated and the same
fluctuating profile is applied for the same time length. The
where VDC nom is the nominal supply side voltage that allows experiment results for the whole period of 400 s are shown in
the DC bus voltage to be Vbus Ref without activating the DC- Fig. 15(a). The transient waveforms of the system during the
ES, and VDC is a random fluctuating voltage. Two cases are moment of the activation of the DC-ES at t = 200 s is zoomed
studied in this experiment: (i) positive constant-resistive NC in and shown in Fig. 15(b) in which the settling time of the
load and (ii) positive constant-power NC load. bus voltage is around 400 ms. Figure 16 shows the enlarged

0.49VDC + 0.035 200VDC + 9.7 10 VDC + 7.5 10 12
3 4
: VDC < 50.04 V
Vbus = 48 V : 50.04 V VDC 50.73 V (41)


0.49VDC + 0.035 200VDC + 4.1 103 VDC 2.4 104 + 5 : VDC > 50.73 V

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Transactions on Power Electronics

14

(a) Experiment results under an unstable supply side voltage variation (b) The transient response during the activation of the DC-ES at
with a constant-resistive non-critical load for the whole period of 400 s. t = 200 s with a constant-resistive NC load. The settling time of the
bus voltage is around 400 ms.
Fig. 15. Experiment results under an unstable supply side voltage variation with a constant-resistive non-critical load.

ES Off ES On

T2 T4
T1 T3 T5 T6 T7 T8 T9

Supply Side
Voltage (V)

Bus Voltage (V)

ES Voltage (V)

Smart Load
Power (W)

Time (Sec)

Fig. 16. Enlarged experiment waveforms based on the raw data exported from the oscilloscope corresponding to Fig. 15(a).

experiment waveforms based on the raw data exported from
the oscilloscope corresponding to Fig. 15(a), where the smart
load power is calculated as the product of the instantaneous
bus voltage and the instantaneous smart load current. The
measurements show that without activating the DC-ES (t =
0 to 200 s), the DC bus voltage fluctuates between 48.5 to
51 V. With DC-ES being activated (t = 201 to 400 s), the DC
bus voltage can be regulated, except during the short periods
of T3 and T7 . It is noted that during the periods T1 , T5 and
T9 , the ES voltage is positive and lower than Vbus Ref , and the
DC-ES is operating in region 2 of Fig. 6(a). During the periods
T6 , T7 and T8 , the ES voltage is negative and the DC-ES is
operating in region 1. During the periods T2 , T3 and T4 , the
ES voltage is positive and varies between Vbus Ref to Ves max
and the DC-ES is operating in region 3. Since the maximum
ES voltage is limited at 60 V, the DC-ES cannot be operated in
region 4. In T3 , the ES voltage reaches its minimum, Ves min ,
and it reaches its maximum, Ves max in T7 . Therefore, the DC

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Transactions on Power Electronics

15

(a) Experiment results under an unstable supply side voltage variation (b) The transient response during the activation of the DC-ES at
with a constant-power non-critical load for the whole period of 400 s. t = 200 s with a constant-power NC load. The settling time of the
bus voltage is around 400 ms.
Fig. 17. Experiment results under an unstable supply side voltage variation with a constant-power non-critical load.

ES Off ES On

50.4
Supply Side
Voltage (V)

50.3
50.2
50.1
50
49.9
49.8
0 50 100 150 200 250 300 350 400
Bus Voltage (V)

48.2
48.1
48
47.9
47.8
47.7
0 50 100 150 200 250 300 350 400
ES Voltage (V)

10
5
0
-5
-10
-15
-20
0 50 100 150 200 250 300 350 400
180
Smart Load
Power (W)

160
140
120
100
80
0 50 100 150 200 250 300 350 400
Time (Sec)

Fig. 18. Enlarged experiment waveforms based on the raw data exported from the oscilloscope corresponding to Fig. 17(a).

bus voltage cannot be regulated in these two periods of time. DC source voltage can be derived from
This set of results indicates that, like the mechanical spring, ( )
Po Vbus Ref Vbus Ref
each ES has its limit. This problem can be solved by using VDC = Rd + + (45)
more distributed ES over the distributed line to support the Vbus Ref Rc Rd
voltage regulation. as VDC nom = 50.14 V. The experiment is similar to that
described in Section VI-B1 except that a constant-power NC
load is adopted. The DC-ES is turned off for the first 200
seconds and then turned on for the next 200 seconds. The
2) Positive Constant-Power Non-Critical Load: The specifi- experiment results of the whole period of 400 s are recorded
cations of the experiment are shown in Table XII. The nominal in Fig. 17(a). The transient response of the system during the

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Node1 Node2
Rd1 Rd2 Rd3
VDC R1 R3
R2
Fig. 19. System configuration for droop effect experiment.
moment of the activation of the DC-ES at t = 200 s is shown
in Fig. 17(b), where the settling time of the bus voltage is
around 400 ms. The enlarged waveforms of Fig. 17(a) are
shown in Fig. 18. It can be seen that without activating the DC-
ES (t = 0 to 200 s), the DC bus voltage fluctuates between 49.9
and 50.3 V. With DC-ES being activated (t = 201 to 400 s),
the DC bus voltage can be regulated at all times. Since the
application of negative voltage on the constant-power load (the
buck converter) is prohibited, the DC-ES can only be operated
either in region 1 (Ves < 0) or region 2 (0 < Ves < Vbus )
according to Fig. 7(a).
C. Part Three Droop Effect
This experiment verifies the effectiveness of using DC-ES
for alleviating the droop effect along a radial DC network.
The configuration of the experiment is shown in Fig. 19. The
parameters used in this experiment are Rd1 = Rd2 = Rd3 =
Rd4 = 0.2 , R1 = R3 = 25 , R2 = 10 , and R4 =
25 (in light load condition) or R4 = 12 (in heavy load
condition). The DC source voltage is chosen as VDC = 50.5 V.
The nominal DC bus voltage is Vbus Ref = 48 V and a 5 %
allowable variation is chosen. The experiment results are given
in Fig. 20. Without activating the DC-ES, the voltage at all
four nodes on the DC bus are within the permissible range
when the load R4 is a light load with a resistance of 25 .
However, when the load R4 is a heavy load with a resistance
of 12 , the voltage of node 3 and node 4 drop to 45 V
and 44.25 V, respectively, which exceed the permissible lower
limit (45.6 V). With the DC-ES activated and the load R4 in a
heavy load condition, the voltage at all nodes on the DC bus
can be boosted and retained within the the permissible limit.
The experiment confirms the DC-ES can be used to alleviate
the droop effect of DC bus voltages.
VII. C ONCLUSIONS
In this paper, the concept of DC electric springs (ES) is
firstly introduced to cope with several issues of DC power
grids. The DC-ES is proposed as an active suspension system.
Similar to their AC counterparts, the DC-ES can provide
dynamic voltage regulation for the DC bus. The DC-ES
connected in series with different types of non-critical loads
to form a smart load have been analyzed and their operating
modes have been identified and explained. Furthermore, the
operating limits of the DC-ES under a given set of system
parameters is studied, which provides quantitative analytical
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Transactions on Power Electronics
16
Node3 Node4 procedures to estimate the theoretical limits of ES. The paper
provides a fundamental study on the DC-ES including the
Rd4
characteristics, the modes of operation, and the operating
limits. The theoretical analysis and the performance of the DC-
R4 ES have been practically verified.
ACKNOWLEDGMENT
This project is supported in part by the Hong Kong Research
Grant Council under the Theme-based project T23-701/14-N.
R EFERENCES
[1] R. Lobenstein and C. Sulzberger, Eyewitness to DC history, Power
and Energy Magazine, IEEE, vol. 6, no. 3, pp. 8490, May 2008.
[2] G. Neidhofer, Early three-phase power, Power and Energy Magazine,
IEEE, vol. 5, no. 5, pp. 88100, Sep. 2007.
[3] B. C. Beaudreau, World Trade: A Network Approach. iUniverse, 2004.
[4] H. Kakigano, Y. Miura, and T. Ise, Distribution voltage control for DC
microgrids using fuzzy control and gain-scheduling technique, IEEE
Trans. Power Electron., vol. 28, no. 5, pp. 22462258, May 2013.
[5] P. Loh, D. Li, Y. K. Chai, and F. Blaabjerg, Autonomous operation
of hybrid microgrid with AC and DC subgrids, IEEE Trans. Power
Electron., vol. 28, no. 5, pp. 22142223, May 2013.
[6] A. Kwasinski and C. Onwuchekwa, Dynamic behavior and stabiliza-
tion of DC microgrids with instantaneous constant-power loads, IEEE
Trans. Power Electron., vol. 26, no. 3, pp. 822834, Mar. 2011.
[7] C. Gellins, Are we at the threshold of a new era of DC power systems?
EPRIs DC Power Prod., Deliv., Jun. 2006.
[8] N. Hatziargyriou, Microgrids [guest editorial], IEEE Power Energy
Mag., vol. 6, no. 3, pp. 2629, May 2008.
[9] S. Huddy and J. Skufca, Amplitude death solutions for stabilization of
DC microgrids with instantaneous constant-power loads, IEEE Trans.
Power Electron., vol. 28, no. 1, pp. 247253, Jan. 2013.
[10] A. Kwasinski, Quantitative evaluation of DC microgrids availability:
Effects of system architecture and converter topology design choices,
IEEE Trans. Power Electron., vol. 26, no. 3, pp. 835851, Mar. 2011.
[11] R. Balog and P. Krein, Bus selection in multibus DC microgrids,
IEEE Trans. Power Electron., vol. 26, no. 3, pp. 860867, Mar. 2011.
[12] B. Johnson and R. Lasseter, An industrial power distribution system
featuring UPS properties, in Proc. IEEE Power Electron. Specialists
Conf. (PESC), Jun. 1993, pp. 759765.
[13] W. Tang and R. Lasseter, An LVDC industrial power distribution
system without central control unit, in Proc. IEEE Power Electron.
Specialists Conf. (PESC), vol. 2, 2000, pp. 979984 vol.2.
[14] M. Baran and N. Mahajan, DC distribution for industrial systems:
opportunities and challenges, IEEE Trans. Ind. Applicat., vol. 39, no. 6,
pp. 15961601, Nov. 2003.
[15] A. Sannino, G. Postiglione, and M. Bollen, Feasibility of a DC network
for commercial facilities, in Proc. IEEE Ind. Applicat. Conf., vol. 3,
Oct. 2002, pp. 17101717 vol.3.
[16] D. Salomonsson and A. Sannino, Low-voltage DC distribution system
for commercial power systems with sensitive electronic loads, IEEE
Trans. Power Del., vol. 22, no. 3, pp. 16201627, Jul. 2007.
[17] Y. K. Chen, Y. C. Wu, C. C. Song, and Y. S. Chen, Design and
implementation of energy management system with fuzzy control for
DC microgrid systems, IEEE Trans. Power Electron., vol. 28, no. 4,
pp. 15631570, Apr. 2013.
[18] H. Kakigano, Y. Miura, T. Ise, T. Momose, and H. Hayakawa, Fun-
damental characteristics of DC microgrid for residential houses with
cogeneration system in each house, in Proc. IEEE Power and Energy
Soc. General Meeting, Jul. 2008, pp. 18.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2542278, IEEE
Transactions on Power Electronics

17

51
50.5
50
49.5
49

Bus Voltage (V)

48.5
48
47.5
47
46.5
46
45.5
45 Light load without ES
Heavy load without ES
44.5 Heavy load with ES
44
Source Node1 Node2 Node3 Node4
Location

Fig. 20. Experiment results showing the voltage level of each node.

[19] R. Simanjorang, H. Yamaguchi, H. Ohashi, K. Nakao, T. Ninomiya,
S. Abe, M. Kaga, and A. Fukui, High-efficiency high-power DC-DC
converter for energy and space saving of power-supply system in a data
center, in Proc. IEEE Appl. Power Electron. Conf. and Expo. (APEC),
Mar. 2011, pp. 600605.
[20] S. Roy, Reliability considerations for data centers power architectures,
in Proc. IEEE Telecommun. Energy Conf. (INTELEC), Oct. 2001, pp.
406411.
[21] F. Bodi, DC-grade reliability for ups in telecommunications data
centers, in Proc. IEEE Telecommun. Energy Conf. (INTELEC), Sep.
2007, pp. 595602.
[22] K. Mistry, E. Silverman, T. Taylor, and R. Willis, Telecommunications
power architectures: distributed or centralized, in Proc. IEEE Telecom-
mun. Energy Conf. (INTELEC), Oct. 1989, pp. 10.1/110.111 vol.1.
[23] A. Emadi, K. Rajashekara, S. Williamson, and S. Lukic, Topological
overview of hybrid electric and fuel cell vehicular power system
architectures and configurations, IEEE Trans. Veh. Technol., vol. 54,
no. 3, pp. 763770, May 2005.
[24] J. Duarte, M. Hendrix, and M. Simoes, Three-port bidirectional
converter for hybrid fuel cell systems, IEEE Trans. Power Electron.,
vol. 22, no. 2, pp. 480487, Mar. 2007.
[25] A. Emadi and M. Ehsani, Aircraft power systems: technology, state of
the art, and future trends, IEEE Aerosp. Electron. Syst. Mag., vol. 15,
no. 1, pp. 2832, Jan. 2000.
[26] H. Zhang, F. Mollet, C. Saudemont, and B. Robyns, Experimental
validation of energy storage system management strategies for a local
DC distribution system of more electric aircraft, IEEE Trans. Ind.
Electron., vol. 57, no. 12, pp. 39053916, Dec. 2010.
[27] A. Monti, D. Boroyevich, D. Cartes, R. Dougal, H. Ginn, G. Monnat,
S. Pekarek, F. Ponci, E. Santi, S. Sudhoff, N. Schulz, W. Shutt, and
F. Wang, Ship power system control: a technology assessment, in
Proc. IEEE Elect. Ship Tech. Symp., Jul. 2005, pp. 292297.
[28] B. Zahedi and L. Norum, Modeling and simulation of all-electric
ships with low-voltage dc hybrid power systems, IEEE Trans. Power
Electron., vol. 28, no. 10, pp. 45254537, Oct. 2013.
[29] M. R. Patel, Spacecraft Power Systems. CRC Press, 2005.
[30] J. Busch, Direct powered DC lighting technologies, in Proc. Green
Building Power Forum, Jun. 2009.
[31] J. Akins, Low-voltage DC interconnection, in Proc. Green Building
Power Forum, Jun. 2009.
[32] S. Anand, B. G. Fernandes, and M. Guerrero, Distributed control to
ensure proportional load sharing and improve voltage regulation in low-
voltage DC microgrids, IEEE Trans. Power Electron., vol. 28, no. 4,
pp. 19001913, Apr. 2013.
[33] A. Kwasinski and P. Krein, Optimal configuration analysis of a
microgrid-based telecom power system, in Proc. IEEE Telecommun.
Energy Conf. (INTELEC), Sep. 2006, pp. 18.
[34] H. Ikebe, Power systems for telecommunications in the IT age, in
Proc. IEEE Telecommun. Energy Conf. (INTELEC), Oct. 2003, pp. 1
8.
[35] J. Guerrero, J. Vasquez, J. Matas, L. de Vicua, and M. Castilla,
Hierarchical control of droop-controlled AC and DC microgrids - a
general approach toward standardization, IEEE Trans. Ind. Electron.,
vol. 58, no. 1, pp. 158172, Jan. 2011.
[36] H. Kakigano, Y. Miura, and T. Ise, Low-voltage bipolar-type DC
microgrid for super high quality distribution, IEEE Trans. Power
Electron., vol. 25, no. 12, pp. 30663075, Dec. 2010.
[37] P. Cairoli, I. Kondratiev, and R. A. Dougal, Coordinated control of
the bus tie switches and power supply converters for fault protection
in DC microgrids, IEEE Trans. Power Electron., vol. 28, no. 4, pp.
20372047, Apr. 2013.
[38] M. Baran and N. Mahajan, Overcurrent protection on voltage-source-
converter-based multiterminal DC distribution systems, IEEE Trans.
Power Del., vol. 22, no. 1, pp. 406412, Jan. 2007.
[39] E. Jamshidpour, B. Nahid-Mobarakeh, P. Poure, S. Pierfederici,
F. Meibody-Tabar, and S. Saadate, Distributed active resonance sup-
pression in hybrid DC power systems under unbalanced load condi-
tions, IEEE Trans. Power Electron., vol. 28, no. 4, pp. 18331842,
Apr. 2013.
[40] R. Balog, W. Weaver, and P. Krein, The load as an energy asset in
a distributed architecture, in Proc. IEEE Elect. Ship Tech. Symp., Jul.
2005, pp. 261267.
[41] P. Liutanakul, A. B. Awan, S. Pierfederici, B. Nahid-Mobarakeh, and
F. Meibody-Tabar, Linear stabilization of a DC bus supplying a
constant power load: A general design approach, IEEE Trans. Power
Electron., vol. 25, no. 2, pp. 475488, Feb. 2010.
[42] X. Feng, Z. Ye, K. Xing, F. Lee, and D. Borojevic, Impedance
specification and impedance improvement for DC distributed power
system, in Proc. IEEE Power Electron. Specialists Conf. (PESC),
vol. 2, 1999, pp. 889894 vol.2.
[43] D. Gadoura, V. Grigore, J. Hatonen, J. Kyyra, P. Vallittu, and T. Suntio,
Stabilizing a telecom power supply feeding a constant power load, in
Proc. IEEE Telecommun. Energy Conf. (INTELEC), 1998, pp. 243248.
[44] W. Du, J. Zhang, Y. Zhang, and Z. Qian, Stability criterion for cascaded
system with constant power load, IEEE Trans. Power Electron., vol. 28,
no. 4, pp. 18431851, Apr. 2013.
[45] S. Y. Hui, C. K. Lee, and F. F. Wu, Electric springs - a new smart grid
technology, IEEE Trans. Smart Grid, vol. 3, no. 3, pp. 15521561,
2012.
[46] S. Y. R. Hui, C. K. Lee, and F. F. Wu, Power control circuit and

0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2542278, IEEE
Transactions on Power Electronics
method for stabilizing a power supply, Oct. 3 2011, US Patent App.
13/251,823.
[47] S. C. Tan, C. K. Lee, and S. Hui, General steady-state analysis and
control principle of electric springs with active and reactive power
compensations, IEEE Trans. Power Electron., vol. 28, no. 8, pp. 3958
3969, Aug. 2013.
[48] C. K. Lee and S. Y. Hui, Reduction of energy storage requirements
in future smart grid using electric springs, IEEE Trans. Smart Grid,
vol. 4, no. 3, pp. 12821288, Sep. 2013.
[49] C. K. Lee and S. Y. R. Hui, Input AC voltage control bi-directional
power converters, May 31 2013, US Patent App. US2013/0322139.
[50] K. T. Mok, T. Yang, S. C. Tan, C. K. Lee, and S. Y. R. Hui, Distributed
grid voltage and utility frequency stabilization via shunt-type electric
springs, in Proc. IEEE Energy Convers. Congr. and Expo. (ECCE),
Sep. 2015, pp. 37743779.
[51] X. Luo, Z. Akhtar, C. K. Lee, B. Chaudhuri, S. C. Tan, and S. Hui,
Distributed voltage control with electric springs: Comparison with
STATCOM, IEEE Trans. Smart Grid, vol. 6, no. 1, pp. 209219, Jan.
2015.
[52] K. R. Krishnanand, S. M. F. Hasani, J. Soni, and S. K. Panda,
Neutral current mitigation using controlled electric springs connected
to microgrids within built environment, in Proc. IEEE Energy Convers.
Congr. and Expo. (ECCE), Sep. 2014.
[53] X. Che, T. Z. Wei, Q. Huo, and D. Jia, A general comparative analysis
of static synchronous compensator and electric spring, in Proc. IEEE
Transp. Electrification Asia-Pacific (ITEC Asia-Pacific), Aug. 2014, pp.
15.
[54] J. Soni, K. R. Krishnanand, and S. K. Panda, Load-side demand
management in buildings using controlled electric springs, in Proc.
eScholarship Building Efficiency and Sustainability in the Tropics
(SinBerBEST), Jun. 2014, pp. 53765381.
[55] K. T. Mok, M. H. Wang, S. C. Tan, and S. Y. Hui, DC electric springs
- an emerging technology for DC grids, in Proc. IEEE Appl. Power
Electron. Conf. and Expo. (APEC), Mar. 2015, pp. 684690.
[56] T. Mayama, Y. Takabayashi, and S. Wakui, Anti-vibration
apparatus, exposure apparatus using the same, device manufacturing
method, and anti-vibration method, 2001. [Online]. Available:
https://www.google.com/patents/US6322060
[57] M. Vikram, M. Gehringer, and R. Patil, Dual degree of freedom
vibration damper (DDVD) for driveline noise and vibration issue
resolution, SAE Technical Paper, 2015.
[58] E. Vitaliani, D. Di Rocco, and M. Sopouch, Modelling and simula-
tion of general path centrifugal pendulum vibration absorbers, SAE
Technical Paper, 2015.
[59] C. S. Leu and Q. T. Nha, A half-bridge converter with input current
ripple reduction for DC distribution systems, IEEE Trans. Power
Electron., vol. 28, no. 4, pp. 17561763, Apr. 2013.
Kwan-Tat Mok (S14) received the B.Eng. (Hons.)
and M.Phil. degrees in electronic and information
engineering from the Hong Kong Polytechnic Uni-
versity, in 2009 and 2012, respectively. In 2007, he
worked as an Engineering Trainee in Solomon Sys-
tech Limited, Hong Kong, for a one-year internship
program. From September 2011 to February 2013,
he was an Embedded System Engineer in Cwlinux
Limited, Hong Kong. From July to August 2015, he
was a visiting postgraduate student in Department of
Electrical and Electronic Engineering, Imperial Col-
lege London. He is currently a Ph.D. candidate in Power Electronics Research
Group, Department of Electrical and Electronic Engineering, The University
of Hong Kong. His research interests include smart grid technologies, electric
springs and power converters for light-emitting diodes.
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18
Ming-Hao Wang (S15) received the B.Eng. and
M.Sc. degrees in electrical and electronic engineer-
ing from the Huazhong University of Science and
Technology, Wuhan, China and The University of
Hong Kong, Hong Kong, in 2012 and 2013, respec-
tively. He is currently a Ph.D. candidate in Power
Electronics Research Group, Department of Elec-
trical and Electronic Engineering, The University
of Hong Kong, Hong Kong. His research interests
include smart grid technologies, DC power systems,
electric springs and power electronics.
Siew-Chong Tan (M06SM11) received the
B.Eng. (Hons.) and M.Eng. degrees in electrical and
computer engineering from the National University
of Singapore, Singapore, in 2000 and 2002, respec-
tively, and the Ph.D. degree in electronic and infor-
mation engineering from the Hong Kong Polytechnic
University, Hong Kong, in 2005.
From October 2005 to May 2012, he worked as
Research Associate, Postdoctoral Fellow, Lecturer,
and Assistant Professor in Department of Electronic
and Information Engineering, Hong Kong Polytech-
nic University, Hong Kong. From January to October 2011, he was Senior
Scientist in Agency for Science, Technology and Research (A*Star), Sin-
gapore. He is currently an Associate Professor in Department of Electrical
and Electronic Engineering, The University of Hong Kong, Hong Kong. Dr.
Tan was a Visiting Scholar at Grainger Center for Electric Machinery and
Electromechanics, University of Illinois at Urbana-Champaign, Champaign,
from September to October 2009, and an Invited Academic Visitor of
Huazhong University of Science and Technology, Wuhan, China, in December
2011. His research interests are focused in the areas of power electronics and
control, LED lightings, smart grids, and clean energy technologies.
Dr. Tan serves extensively as a reviewer for various IEEE/IET transactions
and journals on power, electronics, circuits, and control engineering. He is
an Associate Editor of the IEEE Transactions on Power Electronics. He is a
coauthor of the book Sliding Mode Control of Switching Power Converters:
Techniques and Implementation (Boca Raton: CRC, 2011).
S. Y. (Ron) Hui (M87SM94F03) received his
BSc (Eng) Hons at the University of Birmingham
in 1984 and a D.I.C. and PhD at Imperial College
London in 1987. Presently, he holds the Philip Wong
Wilson Wong Chair Professorship at the University
of Hong Kong and a part-time Chair Professorship
at Imperial College London.
He has published over 300 technical papers, in-
cluding more than 200 refereed journal publications.
Over 55 of his patents have been adopted by industry.
He is an Associate Editor of the IEEE Transactions
on Power Electronics and IEEE Transactions on Industrial Electronics, and
an Editor of the IEEE Journal of Emerging and Selected Topics in Power
Electronics. His inventions on wireless charging platform technology underpin
key dimensions of Qi, the worlds first wireless power standard, with freedom
of positioning and localized charging features for wireless charging of con-
sumer electronics. In Nov. 2010, he received the IEEE Rudolf Chope R&D
Award from the IEEE Industrial Electronics Society and the IET Achievement
Medal (The Crompton Medal). He is a Fellow of the Australian Academy of
Technological Sciences & Engineering and is the recipient of the 2015 IEEE
William E. Newell Power Electronics Award.