Microelectronics Journal 46 (2015) 956962

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

A recongurable LNA with single switched input matching network

for S-band (WiMAX/WLAN) applications
Hossein Eslahi a,n, Ali Jalali a, Saman Nateghi a, Jalil Mazloum b
a
Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran
b
Electrical Engineering Department, Shahid Sattari Aeronautical University, Tehran, Iran

art ic l e i nf o a b s t r a c t

Article history: In this paper a recongurable Low Noise Amplier (LNA) which works at 2.4 GHz and 3.5 GHz frequency
Received 4 December 2014 bands is presented. In discrete approach for designing recongurable circuits the switch is an undeniable
Received in revised form part. But the number of switches can make many problems such as amount of noise factor. Here, a LNA
15 May 2015
has been introduced which has only one switch and is designed with discrete tuning technique that can
Accepted 25 June 2015
show good performance at mentioned frequencies. Besides, the input matching network uses a circuit
that presents relatively xed real part in input impedance, and therefore, input matching is satised.
Keywords: Using current reuse technique causes the overall gain is set in high amount. LNA is designed using
Recongurable LNA 0:18 m CMOS technology and results of simulator express that its gain is 20:07 dB and 21:08 dB, s11 is
Noise gure
22:8 dB and 28:86 dB, s22 has
18:16 dB and 27:37 dB values, NF is 2:6 dB and 3:1 dB, and IP3 is
Power consumption
equal to 2 dB m and 2:1 dB m in 2:4 GHz and 3:5 GHz, respectively. The proposed LNA consumes
Input and output matching
Discrete tuning 11 mA from a 1:8 V supply voltage.
Frequency bands & 2015 Elsevier Ltd. All rights reserved.

1. Introduction
Today, because of the progress in wireless communications,
several standards such as Bluetooth, Wireless Local Area Network
(WLAN), Global Positioning System (GPS), WiMAX, etc are intro-
duced. So there is necessity to implement devices that support
multiple standards. But, using many parallel single band RF front-
ends to implement such devices will increase power consumption,
chip area and implementation costs. Therefore, a novel approach
formed in designer's mind was to design and to implement multi-
standard radio frequency circuits which are called "Recongurable
Circuits". In this approach, the performance of conventional
circuits is reconstructed in a way that new structures will support
more than one frequency band. First, designers focused on
recongurable receivers and many structures have been suggested
for satisfying this approach. Parallel receivers, recongurable
receivers with several single band receivers which are selected
by means of switches ([1]) and receivers with several LNAs in
input stages ([1,2]) are examples of recongurable receivers but
none of them can cause low area and cost. Finally, a receiver was
introduced which uses a recongurable LNA in its rst stage. In
fact, this topology was an improved case of receiver with several
LNAs. In other words, in this receiver, a recongurable LNA was
n
Corresponding author.
employed instead of several single band LNAs and hence, the
designer eyesight changed from recongurable receiver design
toward recongurable LNA design and many topologies are intro-
duced for recongurable LNA so far [1,3].
Two approaches are introduced for designing recongurable
circuits: discrete tuning and continuous tuning. In discrete tuning
technique, switches are used for frequency selection. Therefore,
the number of switches are used in circuits is very important.
Since every switch can produce noise, there is a trade-off between
the number of switches and amount of noise factor. On the other
hand, number of switches must select at minimum number. Also,
switch effects on input matching network and can disturb the
reliability of circuit. In [1], a recongurable LNA has been proposed
which works at 0.9 GHz and 2 GHz and frequency is selected when
the gate-source capacitor is changed by means of a switch. But,
changing in C gs capacitance will decrease the overall gain and
subsequently for compensating this effect, current must be
increased. Besides, in that work more than one switch is used in
input and output matching network. In [3], in order to change
frequency band and achieve good parameters, several switches are
used and hence, the suggested topology is not suitable for
implementation of recongurable LNA because of its poor noise
gure and quality. In [4], a LNA with wideband input matching
network has been designed that uses a switchable tank circuit as
load. By making change in tank switchable inductor value, reso-
nance frequency of output tank is changed and therefore the

http://dx.doi.org/10.1016/j.mejo.2015.06.017
0026-2692/& 2015 Elsevier Ltd. All rights reserved.
 H. Eslahi et al. / Microelectronics Journal 46 (2015) 956962
operating frequency of LNA is selected. This LNA covers 2.4 GHz,
3.5 GHz and 5.8 GHz frequency bands. However, using wideband
circuits in input may affect the performance of noise.
Second method for designing recongurable LNA is continuous
tuning technique. In this approach, there are structures that have
ability to continuously change the operating frequency and con-
sequently LNAs that are designed by this technique will have
better quality than discrete tuning LNAs and can cover more
frequency bands. But, designing with this method requires deploy-
ing superior mathematical algorithms which complicate the
design procedure. One example is presented in [5] in which
changing triode resistor value of input matching network will
cause continuous shifting in frequency. This LNA is designed for
2.45.2 GHz frequency range.
In this paper, a recongurable LNA is proposed for 2.4 GHz and
3.5 GHz frequencies designed with discrete tuning technique. The
main idea of this paper is using only one switch in total topology
for frequency shifting. Since the existence of a switch in LNA
circuit increases NF and its negative effect will be higher if it is in
input matching network, so the noise performance in suggested
LNA is comparable with many other papers which use more
switches in input matching network [6] or load [7,8]. This can be
an innovative plan to implement recongurability in LNA by use of
only one switch. Moreover, the proposed LNA has high gain and
suitable parameters in two operating frequencies.
This paper is organized as follows. In Section 2, the suggested
recongurable LNA is introduced. Then proposed recongurable
LNA is analyzed and gain, noise gure, input and output matching
equations are extracted from LNA schematic in Section 3. Simula-
tion results are presented and analyzed in Section 4. Finally, the
conclusion is expressed in Section 5 as a summarization of whole
of this paper.
2. Recongurable LNA
2.1. Base structure
LNA is the most important block in receiver and must have
good noise performance, suitable linearity, low power consump-
tion and good input and output impedance matching. Therefore,
designers have to choose the structures that obtain the best
tradeoff between these parameters. Generally, there are several
structures for implementing this important block. The rst type of
these structures focuses on satisfying the input impedance match-
ing. For example, in [9] four types of this architecture have been
explained. The rst structure is resistive termination so that for
satisfying the input impedance matching one resistor is used in
parallel with input port. Unfortunately, using resistor in input
directly affects on noise structure and signicantly increases noise
factor. It is proved that in this case the noise factor is expressed by
[10]:
Total output noise power
F 1
Total output noise due to the input source
P ni
F 2 2
KTBGa
In Eq. (2), P ni is noise power at the output due to internal noise
source, Ga is overall gain and B is bandwidth. In the best case, this
structure shows noise gure about 6 dB which is a high amount.
Second structure used in many references is shunt-series feedback
that more than one resistor is used in input network. For this
structure noise gure is found to be about 7 dB. Besides, since two
or more resistors are used in input, power consumption becomes
unusual amount.
957
But, the main structure which is used in many references is
ICDS (Inductively-Degenerated Common Source). This structure
uses an inductor in source of rst stage of cascode and leads to
better linearity and shows better reverse isolation, wide band-
width and proper Gain rather than previous structures. Usually,
different techniques are used for improving this structure and
obtaining better parameters. For example, there are techniques
that consider noise factor as main parameter in design and
implementation and translations on ICDS. In general, there are
approximately seven techniques that focus on noise structure.
These structures were completely reviewed at [911] but four
main techniques are CNM (Classical Noise Matching), SNIM
(Simultaneous Noise and Input Matching), PCNO (Power-Con-
strained Noise optimization) and PCSNIM (Power-Constrained
Simultaneous Noise and Input Matching). The last technique
(PCSNIM) provides better result in noise structure and power
consumption and generally forms base architecture in many LNA.
In this technique an external capacitor is placed in parallel with
gate-source capacitor. Although this capacitor leads to decrease
overall gain but prevents of increase amount of inductor in source
of ICDS in low frequency applications. This fact is completely
explained in [9]. This is another benet which appears in
PCSNIM.
In this paper, ICDS structure with PCSNIM form base proposed
structure but for decreasing adverse effects due to external capacitor
in PCSNIM technique, several meaningful changes are applied in input
network. These changes are explained in the next parts.
2.2. Current reuse technique
In conjunction with ICDS, current reuse technique is combined
with base structure to obtain high gain. Current reuse technique
converts the cascode to cascade topology and therefore without
any increase in dc current for both cascode transistors ( M 1 ,M 2 ), it
can increase the overall gain (see Fig. 1a and b). On the other hand,
in cascode topology, gain is counted by:
Aveq Gmeg  Z out 3
where, Aveq is total gain, Gmeg is transconductance in cascode
topology and Z out is output impedance. But in new topology, when
structure is changed from cascode to cascade by current reuse
technique, the total gain is expressed by:
Aveq Av1  Av2 4
Or:
Aveq g m1 Ld  g m2 Z out 5
Here, Av1 is the rst stage gain by M 1 and Av2 is the second stage
gain by M 2 . This event is happened in this way: current reuse
technique is performed by capacitors C d and C s as are shown in
Fig. 1a. C d and C s have large values and are short connected in AC
analysis and therefore, source of M 2 is grounded, and drain of M 1
is connected to gate of M 2 . Consequently, the AC signal passes
from drain of M 1 to gate of M 2 and overall gain will be equal to the
product of M 1 s gain and M 2 s gain and hence, overall gain will be
increased. Effect of current reuse technique on cascade topology is
shown in Fig. 1b.
2.3. Output impedance matching network
The schematic of proposed recongurable LNA is shown in
Fig. 2. To have good output impedance matching, shunt peaking
technique is used in output tank circuit. This technique is a way for
bandwidth extension at output in which an inductor L1 is
connected in series with a resistor R1 , and both connected to
output LC resonant circuit (consist of C t and Lt ) in shunt. Moreover,
958 H. Eslahi et al. / Microelectronics Journal 46 (2015) 956962

Vdd 2.4. Input impedance matching network

Output The most important section in LNA is input matching network,

LC Tank
because any circuit which is placed at input generates noise and
Co
the generated noise is directly appeared at input and increases
Output Noise Figure (NF) value. Therefore, there is a tradeoff between
Bias
M2
Voltage input impedance matching and noise performance. This tradeoff is
very important during recongurable LNA design since designers
Cs
Cd have to simultaneously satisfy noise and impedance matching. At
Ld
input matching network, a self-matching capacitor C self is used to
simplify obtaining good impedance matching when frequency is
Cc changed. Using this capacitor, as is shown later, results in an
Input Matching
M1
Network approximately xed real part of input impedance Z in when
frequency shifts. Since the center frequency is indirectly propor-
Input
Ls tional to C gs1 (Eqs. (6) and (21)), making change in external
capacitor C ex (in shunt with C gs1 ), will cause change in center
frequency. This effect appears because central frequency is indir-
ectly in proportion with gate-source capacitor.
Vdd gm
o 6
Output
C gs
LC Tank
But, if C gs1 increases the overall gain will decrease. In Section 3
this adverse effect will be clearly observable when the equation of
M2 Output
transconductance expresses. On the other hand, when the self-
Input Matching
M1 Ld matching capacitor is used in conjunction with external capacitor,
Network
this undesirable result will not happen.
Input
Therefore, it is better that other techniques are used to satisfy
Ls
recongurability. One approach is changing the gate inductor Lg
that causes to change in resonant frequency. This approach will be
Fig. 1. Combination of current reuse and cascode (a), inuence of current reuse on described in next section.
cascode at AC mode. In Section 3, proposed topology will be noticed in details and
equations for each parameter will express. By focus on these
equations, previous descriptions are better perceived. This point
Vdd
must be repeat that unlike recent topologies for recongurable
LNA that use of discrete tuning approach and have more than one
Lt(low) Ct(low) switch, proposed topology in Fig. 2 uses just one switch. This
means minimum number of switches so that form one of benets
R1
of this topology.
Lf
Lt(up) Ct(up)
L1

Co 3. Analysis of recongurable LNA

Output
In this section, proposed recongurable LNA in Fig. 2 is
M2
analyzed and the main parameters including gain, NF, input and
Vb
output matching (s11 , s22 ) are extracted.
Cs
Cd
Rb Ld

3.1. Recongurability in proposed LNA

Cc Lg1 Lg2
M1 The small signal model for Fig. 2 is shown in Fig. 3. This model
Port1
Cex is proposed when C s and C d are large capacitors. By analyzing
Ms input stage in Fig. 3, Z in is extracted as (7):
Vbs

g Ls Lg 1
Z in m j Ls 7
C tot :k1 k1 jC tot k1
Cself
Ls
Lg Vout

Fig. 2. Proposed recongurable LNA.

Zout
Rs Cex Cgs1 Gm1.Vgs1 Ld Lf Cgs2 Gm2.Vgs2

to satisfy output matching at both operating frequencies, two LC

resonant circuits are connected together in series in a way that Vin Cself
Ltup and C tup operate at higher band and Ltlow and C tlow operate Ls
at lower band. By using this tank, the number of required switches
will be decreased. Output impedance which obtains in this net-
work is introduced at next section. Fig. 3. Small signal model for Fig. 2.
 H. Eslahi et al. / Microelectronics Journal 46 (2015) 956962 959

Fig. 4. Input impedance matching at 2.4 GHz and 3.5 GHz. Fig. 7. NF of recongurable LNA at 2.4 GHz and 3.5 GHz.

Fig. 5. Output impedance matching at 2.4 GHz and 3.5 GHz. Fig. 8. IIP3 value of recongurable LNA in 2.4 GHz.

Fig. 6. Gain at 2.4GHz and 3.5 GHz. Fig. 9. IIP3 value of recongurable LNA in 3.5 GHz.

At operating frequency the Eqs. (12) and (13) have to satisfy

where: (this will be illustrated in Section 3.3:
C self
k1 1
2 Lg C self 8 g m Ls
C tot RealfZ in g Rs 4 50 12
C tot  k1


C tot C gs1 C ex 9 Lg 1
ImfZ in g 0 4 j Ls 0 13
k1 jC tot k1
The value of Lg is changed with conditions of M s .
When the switch turns off, Lg has the highest value and equals to From (13), resonant frequency found to be:
s
Lg Lg1 Lg2 10 1
0   14
C tot Lg Ls Ls C self
2 Lg Ls C t C self
when M s is on, gate inductor will have lower value and will equal to

Since the last part in denominator of fraction is very small

Lg Lg2 11 rather than other parts, this part can be removed and, therefore,
960 H. Eslahi et al. / Microelectronics Journal 46 (2015) 956962

the approximate resonant frequency can be expressed as (15):
s frequency is increasing and input impedance matching is provided.
1
0   15
C tot Lg Ls Ls C self
By focusing on (15), it can be seen that the resonant frequency
is reversely proportional to Lg and hence, at input network, a
switch M s in shunt with Lg1 can be used in order to change
resonant frequency of input matching network. When the switch
(M s ) is on, Lg1 is removed from input matching network and Lg has
the least value according to (8) and in this condition LNA work at
higher frequency (3.5 GHz) because 0 is reversely proportional to
Lg . If the M s is off, this switch is eliminated and Lg has more value
than previous condition (equal to (7)), thus, amount of 0 is
decreased and, in this case, LNA works at lower band (2.4 GHz). By
this technique the recongurability is satised and proposed LNA
works at two frequencies.
It should be noticed that changing in Lg has no bad effect on
gain and Gm1 and also guarantees the input impedance matching
in operating frequencies. When the equations of gain and trans-
conductance are explained in next subsections, these results can
be clearly visible.
3.2. Gain
LNA's rst role is amplication of weak received signal from
antenna, so, LNA should have adequate gain. Furthermore, high
gain of LNA will degrade the noise contribution of other blocks in
receiver chain.
By analyzing this model, the gain is expressed as (16):
 
Av  Gm1  jLeq  g  Z out 16
m2
the real part of input impedance will be approximately xed when
Also when frequency decreases, numerator and denominator in (11)
will change in a similar way to each other and both will increase and
therefore, real part will remain xed. This phenomenon happens
because of existence of C self in input network.
To have zero's imaginary part, Lg value should be changed by
means of M s . Based on (14) making change in Lg value will shift
frequency too. The input matching for both frequency bands can be
satised when C ex , C self and Ls are carefully set. To count Ls we can
use Eqs. (11) and (12) and the nal equation is expressed as (22):
q
Ls
5 1
jcj2
 k1 22
o C tot
Here, is approximately equal to unit, is the coefcient of
channel thermal noise, is the coefcient of gate noise and c is
correlation coefcient between gate and drain noises [10]. And in
PCSNIM technique which has been explained in [9] the equation
for Ls is equal to:
q
5 1
jcj2
Ls 23
o C tot
Since C tot is placed in denominator, Ls has lower amount com-
pared with when external capacitor is not used. But in Eq. (22) shows
that C tot is appeared in k, too. Therefore, in this case amount of Ls has
lower number than what is presented in [9]. This expresses that
proposed topology in this paper can provide more less Ls .

where the rst stage transconductance Gm1 is equal to (17): 3.4. Noise gure

g m1
Gm1 g m1 Q in    17 Since LNA is the rst block in receiver chain, it is necessary to
gm1 Ls Rs C tot C self
2 C tot C self Lg have low noise because its noise is amplied when crosses at
Approximate transconductance can be written as (18): subsequent blocks (such as mixer) and disturbs the desired signal
g m1 at the end of the receiver. Thus, one of the most important
Gm1     18 parameters for designing LNA is Noise gure (NF). The noise factor
gm1 Ls Rs C tot C self
written by (1) and, NF is given as (24):
And the output impedance Z out is equal to (19):
NF 10 log F 24
sLT R1 sL1
Z out   19
R1 s Lg L1 s2 R1 Lt C t s3 L1 Lt C t Noise of devices which are placed at the input of LNA is very
important because it is directly appeared at input. Not only input
When LNA works at lower band, C tlow and Ltlow are used in
matching network noise, but also noise in M 1 , M s and inductors
(19). In upper band, C tup and Ltup are used in (19). It can be seen
Lg , Lf and Ld are important too. Noise contributions of other
from (15) that the LNA overall gain is equal to the product of rst
sections consist of M 2 and output tank are divided on LNA's gain
stage gain (M 1 ) and second stage gain (M 2 ) and therefore LNA has
and are degraded, hence, they can be neglected. By noise analysis
high gain.
and using explanations in [11], Noise Factor equation, when M s is
off, expressed as (25):
3.3. Input impedance and impedance matching

2  2
Rg Rl 4 g 1
2 L C
For obtaining good impedance matching, Eqs. (20) and (21) F 1 gm1 k2 k3 k2 m2 2 2 2eq gs2 25
Rs t g m t Leq
have to satisfy:
Z in
Rs
s11 20 Table 1
Z in Rs
simulation results foe proposed recongurable LNA.

20 log s11 o
10 21
Parameter Value
To satisfy (21), the real part of Z in must be equal to source resistor
2.4 GHz 3.5 GHz
Rs 50 and the imaginary part must be equal to zero. In these
conditions, the return loss at input port has its lowest value and input s11 dB
22.86
28.86
impedance matching is guaranteed. From (11), it can be seen that the s22 dB
18.16
27.37
real part is directly proportional to g m1 . On the other hand, g m1 is s21 dB 20.07 21.08
IP3dB m
6.2
5.1
indirectly proportional to frequency [11]. Hence, if frequency
NFdB 2.6 3.1
increases, then the numerator in (11) will decrease. Of course, the ImA 11 11
denominator is decreased when frequency is increased and therefore
 H. Eslahi et al. / Microelectronics Journal 46 (2015) 956962 961

Table 2
Comparison between simulation results of proposed topology with some previous topologies.

Reference Parameter

Freq(GHz) Tuning Gain(dB) NF(dB) s11 (dB) IIP3(dB m) P dc mw V dd V Technology (m) Number of switches

[1] 0.92 Discrete 12.912.4 2.552.3
14.5 to
17.2 9.67.7 26.518.8 1.8 0.18 3
[3] 3.16 Discrete 15.518.2 3.45,2
12 
7 Not reported 1.8 0.18 7
2.43 17.518 o 3.5
[4] 2.43.5 Discrete 1413.9 2.3- 3.2 Not reported
15 to
10 58a 1.8 0.18 3
[5] 2.45.2 Continuous 2319 2 4.2 Not reported
3(@ 3 GHz) 17 1.2 0.13
[8] 2.45.4 Discrete 2224 2.23.1
14 to
30
16 to
21 4.6 1 0.13 6
[6] 2.87.8 Discrete 14.216.1 2.45.3
8.6 to
35.4
1.2 to
5 6.4 1.2 0.13 3
[12] 1.82.4 Continuous 2628 3.23.8 o
12 Not reported 9.6 1.2 0.13
This work 2.43.5 Discrete 20.0721.08 2.6 3.1
22.8 and
28.85
6.2 to
5.1 19.8 1.8 0.18 1

[1,5,6,8] are measurement results and [3,4,12] are simulation results.

In the [8], the authors use a two stage LNA and an Output Buffer for measurement.
[6] is a two stage amplier.
In [12], the proposed LNA is based on two cascaded amplier stages with an active output LC resonator load.
a
This value is equal to sum of the power consumption in designed LNA and mixer in that reference.

where: proposed Circuit. By focusing on s22 gure, this point can be seen

  2  that s22 values in two frequencies are changed when the condi-

Rs t Ls 2 Ls Lg
C1tot tion of M s changes. In fact, when M s switched on, LC resonant
k2 26 circuit which is designed to act in lower band cannot correctly
Rs
operate in new frequency and hence, s22 value will decrease. Also,
1 the reason of decreasing in s22 value at upper operating frequency
k3
2 27
when M s is off is similar to what was mentioned.
1R t Ls
s jLs Lg jC1 The diagram of gain in lower and upper frequency bands is
tot
presented at Fig. 6. By using current reuse technique, it can be seen
Leq Ld Lf 28 that the recongurable LNA shows suitable gain in two operating
frequencies. The LNA's gain is equal to 20:07 dB in lower band and
In (25), Rg is gate resistor (and in [9] was expressed that it is 21:08 dB in higher band. As it can be seen in Fig. 6, gain value in
equal to R12n
sheet W
2 L ), Rl is presenting dissipation of inductor Lg and Rs is upper band is a little more than its value in lower band because
source resistor. When M s is on, this switch presents a triode when M s is switched on, it has effect on Gm1 . But, this effect was
resistor that generates noise, and therefore, increases NF. In this not shown in the equations.
condition, noise of this resistor enters to (25) and Noise Factor will The NF value is represented in Fig. 7. Simulation results express
be given by (29): 2:6 dB in lower band and 3:1 dB in upper band and it can be seen

2  2 that NF value in upper band is larger than lower band, as explained in
Rg Rl Rsw 4 g 1
2 L C
F 1 gm1 k2 k3 k2 m2 2 2 2eq gs2 Section 3. This increase in NF is due to triode resistor of M s .
Rs t g m t Leq
For linearity analyzing, simulated IIP3 is presented in
29 Figs. 8 and 9. IIP3 is equal to
6:2 dB m and
5:1 dB m in lower
In (29), Rsw is representing the triode resistor of M s . In the band and upper band, respectively. As it can be seen in simulation
simulation results, inuence of M s on NF value is visible. To results, the suggested recongurable LNA presents good linearity
overcome this unwanted effect, dimensions of this switch are in both operating frequencies.
selected in the highest possible value, and hence, triode resistor To improve linearity, the current and subsequently, power
decreases. Moreover, it can be seen from (25) and (29) that if consumption can be increased. But, paying attention to tradeoffs
1
2 Leq C gs2 is zero NF will have the lowest value. Therefore, the between power consumption, linearity, gain and input matching
value of inductors Ld and Lf should be correctly selected during during simulation steps is very important. Usually, it is very
LNA design procedure. In the next section, the results of simulation difcult to simultaneously optimize all of these parameters.
are presented and evaluated. The simulation results for the proposed recongurable LNA are
summarized in Table 1 and to evaluate these results, a comparison
is done in Table 2 between suggested topology and some previous
4. Simulation results topologies that are introduced in other references. As it is seen in
Table 2, proposed LNA has better results in most of the elds.
The proposed recongurable LNA as is shown in Fig. 2 was
designed and simulated in 0:18 m RF CMOS technology. This LNA
consumes 11 mA from 1:8 V supply voltage. 5. Conclusion
The return loss at input port s11 in 2.4 GHz and 3.5 GHz is shown
in Fig. 4. As these gure presents, the proposed recongurable LNA In this paper, a recongurable LNA is presented that is designed for
has return loss less than
10 dB for both frequency bands. s11 is 2.4 GHz and 3.5 GHz frequency bands. In proposed structure, current

22:8 dB in 2.4 GHz and
28:85 dB in 3.5 GHz. It means that the reuse technique is combined with cascode topology and the resultant
(15) is satised and input impedance matching has been guaranteed. topology represents high gain. In the input, a matching network is
Simulation results for output impedance matching are also used that can satisfy input impedance matching at two frequency
shown in Fig. 5. From this gure, it can be seen that s22 has bands by use of only one switch in order to reduce NF and implement

18:16 dB and
27:37 dB values in 2.4 GHz and 3.5 GHz, respec- recongurable LNA. By using this network, the real part of Z in is
tively. Therefore, output impedance matching is satised in approximately xed when frequency is changed. The most important
962 H. Eslahi et al. / Microelectronics Journal 46 (2015) 956962
character of this suggested circuit is using just one switch to
implement and satisfy recongurable LNA. Consequently, s11 is better
guaranteed. Proposed recongurable LNA is designed and simulated
in 0:18 m RF CMOS technology. Simulation results show that this
recongurable LNA presents better results than previous topologies in
most of the elds. With consumption of 11 mA from 1:8 V supply
voltage, the input impedance matching s11 is
22:8 dB and

28:85 dB, s22 is equal to
18:16 dB and
27:37 dB, the value
of NF is 2:6 dB and 3:1 dB, and at last, IP3 is
2 dB m and

2:1 dB m in 2.4 GHz and 3.5 GHz bands, respectively.
Acknowledgment
The authors would like to thanks Mr. Ojaroodi for his helps and
invaluable supports during proposed paper designing and simulation.
References
[1] T.M. Mustaffa, A Recongurable Low Noise Amplier for a Multi-standard
Receiver, Victoria University, Australia, 2009, Ph.D. thesis.
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