Ivan Marsic Rutgers University 224

CPU CPU
packets Memory NFE Memory NFE
Processor Processor

Line Card Line Card Line Card CPU CPU Line Card
#1 #4 #1 Memory Memory #4

Line Card Line Card Line Card CPU CPU Line Card
#2 #5 #2 Memory Memory #5

Line Card Line Card Line Card CPU CPU Line Card
#3 #6 #3 Memory Memory #6

(a) (b)

CPU
packets Memory

Line Card Fwd Fwd Line Card

#1 Engine Engine #4

Line Card Fwd Fwd Line Card

#2 Engine Engine #5

Line Card Fwd Fwd Line Card

#3 Engine Engine #6

(c)
Figure 4-5: The basic architectures of packet-switching processors. (a) Central CPU
processor; (b) Parallel network-front-end processors; (c) Switching fabric. The curved line
indicates the packet path, from input to output port.

Second-Generation Routers: Network Front-end (NFE) Processors. The main limitation of

the architecture in Figure 4-5(a) is that the central CPU must process every packet, ultimately
limiting the throughput of the system. To increase the system throughput, the architecture in
Figure 4-5(b) implements parallelism by placing a separate CPU at each interface. That is, the
link-layer is still implemented in individual Line Cards, but the network-layer function is
distributed across several dedicated CPUs, known as network front-end (NFE) processors. A
local forwarding decision is made in a NFE processor, and the packet is immediately forwarded
to its outgoing interface. The central CPU is needed to run the routing algorithm and for
centralized system management functions. It also computes the forwarding table and distributes it
to the NFE processors.
The architecture in Figure 4-5(b) has higher performance than a first-generation design because
the network-layer function is distributed over several NFE processors that run in parallel; and
because each packet need only traverse the bus once, thus increasing the system throughput.
Figure 4-7 highlights the datapath of second-generation routers. However, the performance is still
limited by two factors. First, forwarding decisions are made in software, and so are limited by the
speed of the NFE processor, which is a general purpose CPU. But general purpose CPUs are not
well suited to applications in which the data (packets) flow through the system; CPUs are better
suited to applications in which data is examined multiple times, thus allowing the efficient use of