Via Fill, Via Plug, Via Cap, Via-In-Pad, etc So whats

the difference and why do I care?

Increases in printed circuit board density and the need for higher electrical performance have resulted in
several design challenges. Some of these challenges are related to the proximity of the vias to the surface
mount (SMT) and ball grid array (BGA) lands. To reduce inductance and increase density, via pads are
being placed close to the SMT/BGA lands. Many designers are searching for methods to resolve these
issues while meeting cost objectives.

Figure 1: Via Cap (left) and Via Fill plated-through via (right)

This application note will cover the most common methods used to reduce the SMT/BGA land to via pad
distance while reducing the risk of solder loss down the via during printed circuit assembly. Some can
even be used to put the vias directly in the SMT/BGA lands (Via In Pad). These methods are also used on
some designs to reduce solder shorts as well as improve vacuum hold down during in-circuit test (ICT).
Various materials will be discussed as well as industry common practices using these materials. The intent
is to arm the reader with the information necessary to determine which method is appropriate for their
application.

Materials:
The ability to place a via closer to the SMT/BGA land is generally a function of the soldermask and filling
materials, not the PCB laminate or prepreg materials. This section will briefly describe the common
materials used for soldermask, via plugging, and via filling.

Primary Soldermask: The primary soldermask is the first application of liquid photoimageable (LPI)
soldermask to the PCB generally applied by flood, roller, or curtain coat. It is later printed (exposed),
developed, and cured. It usually covers the entire board surface except for holes, lands and grounding rails.
This soldermask material contains about 60-75% solids (non-volatiles) when applied to the PCB. Some
shrinkage & thinning is expected during the curing process. Merix uses Enthone DSR-3241CRI for LPI
soldermask.

Secondary Soldermask: The second application of soldermask is usually processed by using an imaged
screen mesh. The soldermask is applied to selective areas on the PCB usually to cover the non-ICT vias.
This soldermask material contains about 75-90% solids when applied to the PCB. It has more solids than
LPI soldermask, however is still expected to shrink during the curing process. Merix currently uses PC-
401 and UVP-100 depending on the surface finish of the board.

Non-conductive Fill Material: Via Fill materials contain 99-100% solids and are designed to completely
fill the via and undergo little to no shrinkage during curing. They usually have a lower CTE than PCB
resin making them useful for pre-filling blind and buried vias prior to sequential lamination. These

2003, Merix Corporation

materials have a much better ability to fill high aspect ratio vias (up to 14:1 aspect ratio) compared to the
conductive fill materials (limited to 6:1 aspect ratio). This also makes them useful for filling plated-
through vias as well. Merix currently uses Peters PP-2795 for non-conductive via fill which has a CTE of
40 ppm/degree C.

Conductive Fill Material: Conductive fill material is generally loaded with a combination of copper,
silver, and/or gold. It is intended to provide electrical conductivity through the hole as well as an improved
thermal conductivity over that of the PCB material. Generally has a lower CTE than the PCB resin.
Limited to 6:1 aspect ratio (based on FHS) to fill with essentially no voids. The conductive materials
usually have a much higher cost than non-conductive materials. Merix currently uses DuPont CB-100
series materials for conductive via fill which has a CTE of about 78 ppm/ degree C.

Methods:
IPC-T-50 does not cover the definitions of plugging, capping, or filling of vias. It is our experience that
different companies have their own terminology for these processes. One companys definition of "plugging"
may be a secondary coating of soldermask while another companys definition is to fill the via completely
and plate over the top. This section will use the most common terminology in the industry. Regardless of
the term used, it is very important to communicate in detail your expectation to the fabricator so there is no
misunderstanding.

Via Plug: Via plugging is one of the most commonly used terms on fabrication drawings when vias need
to be partially or fully filled with some type of material. Most often this term is interpreted as Via Cap (see
below). Via Plug has been used in connection by various designers for all of the plugging/filling methods.
Therefore we recommend using one of the following terms and/or clearly define in a customer specification
or on the fabrication drawing what is required.

ICT pad

Encroach Encroach

Figure 2: Via Encroachment. Top side of BGA (left), Bottom side of BGA (right).

Soldermask Encroachment: Soldermask encroachment is when the primary soldermask (LPI) has an
opening for a via that is larger than the FHS (finished hole size), however smaller than the via pad diameter
(See Figure 2). This is commonly used to reduce the amount of solder shorts during assembly. It is the
least expensive alternative as it only affects the primary soldermask artwork. No secondary soldermask or
other filling material is required. There are many designs where soldermask encroachment without via
plugging is sufficient for high yields during assembly.

Merix standard via encroachment is an opening in the soldermask that is 0.006 (150 micron) larger than
the drill diameter. This allows for some coverage of the via pad, however does not put primary soldermask
in the via hole. It also allows soldermask registration to be focused on the lands and not the holes.

2003, Merix Corporation

The preferred method to communicate the requirements for soldermask encroachment is:

1. The primary soldermask (top & bottom) data files should contain:
Features to be left uncovered (lands, ICT pads, etc.): Aperture same size as external layer pad
(also called "master pad") or the desired opening diameter.
Via pads to be encroached by primary soldermask: Aperture same size as FHS (smaller than
external layer pad) or no opening.

2. The fabrication drawing should contain a note similar to:

Soldermask apertures equal to the FHS (or no opening) are to have the primary soldermask
encroached onto the via pad. Soldermask apertures equal to the external layer pad diameter or
larger to remain uncovered (standard fabrication compensation).

Figure 3: Cross Section and surface view of standard Via Cap process. Notice that the primary
soldermask is encroached onto the pad and the Via Cap is larger than the soldermask encroachment.

Via Cap: A secondary soldermask application that covers vias and via pads on top or bottom sides of the
board (not both) after the conductor surface finish is applied. It only puts a small amount of soldermask in
the barrel of the hole (See Figure 3). It is intended to cover the via pad and most of the vias will have
soldermask spanning the opening of the hole. Since the coating must be thin to prevent the solder-paste
stencil from standing off from the lands, a small percentage of the caps may be broken. The soldermask
will still coat the pad and top portion of the hole barrel, however may allow some air to pass through on a
small percentage of vias (<5%). The smaller the via diameter, the higher the percentage of vias will remain
fully capped.

It is most common to Via Cap the vias on the BGA side of the board. Designs that have BGAs on both
sides of the board may have Via Capping on both sides (however not on the same via). The vias associated
with the top side BGA may be capped on the top side while the vias for bottom side BGA may be capped
on the bottom side of the board. If there are vias in common to both BGAs, then select only one side to
cap. The primary soldermask will be encroached on the via cap side of the board. The other side of the
board will either be encroached or left open depending on the aperture size in the data. If the aperture is
less than the external layer pad, then it will be encroached. If the aperture is equal to or larger than the
external layer pad, then it will be left uncovered.

In-circuit test (ICT) points should contain an opening in the soldermask the same size as the via pad. Most
boards requiring Via Cap do not cover all vias on either side of the board. For this reason it is

2003, Merix Corporation

recommended to supply a Via Cap layer in the data files. If Via Capping is done on both sides of the
board, a file for each side should be included in the data.

Via Capping should be done after the final surface finish. There is a long-term reliability risk for
developing opens in the vias if the capping is done prior to surface finish (HASL, OSP, Immersion Silver,
etc. (Contact Merix Applications Engineering for more information).

The preferred method to communicate the requirements for via capping is:

1. The primary soldermask (top & bottom) data files should contain:
Features to be uncovered (lands, ICT pads, etc.): Aperture same size as external layer pad
(master pad) or the desired opening.
Via pads to be encroached by primary soldermask: Aperture same size as FHS (smaller than
external layer pad).
Vias to be capped: No aperture in the data. (can also be encroached if via cap file is supplied)

2. The via cap data file(s) should contain:

Aperture the same size as FHS (or external layer pad) in the same location as the vias to be
capped.
- One file is required if capping is done on one side of the board only.
- Two files are required if some vias are capped on the top side and others capped on the
bottom side of the board. The vias to be capped from the top should be contained in the top
side via cap file. The vias to be capped from the bottom should be contained in the bottom
side via cap file. No vias should exist in both files.

3. The fabrication drawing should contain a note similar to:

Soldermask apertures equal to the FHS are to have the primary soldermask encroached onto the
via pad. Soldermask apertures equal to the external layer pads shall be left open (standard
fabrication compensation). Cap vias with secondary soldermask from the top side per (viacap.top)
file and from the bottom side per (viacap.bot) file.

Note: The naming of the files is arbitrary, but all data files should be listed in the Readme.txt file with
a description of what each file is to be used for. (See Guidelines for Tooling Interface).

Figure 4: Flooding / Tenting with LPI soldermask. Not recommended.

Flooded or Tented Vias: This method provides no aperture in the primary soldermask for the vias on the
top and/or bottom side of the board. The vias are neither capped nor encroached during primary
soldermask application (See Figure 4). Since the LPI soldermask has a relatively low percentage of solids,
it will shrink and crack during the cure process providing a location to entrap chemistry and fluxes. Merix

2003, Merix Corporation

does not recommend this process for most applications due to reliability and assembly issues. The
reliability issues are reduced when the surface finish is nickel/gold and the LPI is put on after the
nickel/gold surface finish. (Contact Merix Applications Engineering for more information).

Figure 5: Via Fill examples. Non-conductive (left), Conductive (right).

Via Fill: Refers to the filling of a via with a conductive or non-conductive fill material. The intent is to
completely fill the the via with a material with essentially no voids such that the surfaces are nearly flat.
This material is usually plated over with copper during the through hole plating process for the non-filled
holes. There are 2 main categories of materials used for the filling: conductive and non-conductive (See
Figure 5). In most applications the non-conductive material will meet the needs of the application and is
usually less expensive than the materials filled with silver or gold. Via Fill can be used for blind and buried
vias as well as plated through holes. Filled blind vias and filled plated through holes can be placed within
the SMT or BGA land (referred to as Via-In-Pad , see below). (For more information, see the Via Fill
application note).

The initial non-conductive materials used for Via Fill did not contain enough solids to prevent shrinkage
during the cure process. Some conductive via fill materials, like DuPont CB100, met the needs of some
designs. This material has a limitation of 6:1 aspect ratio to remain void free. Newer board designs are
above 10:1 aspect ratio so the conductive materials will have voids in the hole if it is used in these
applications. There are newer processing methods being investigated that may improve the aspect ratio
capability of the conductive materials.

Newer non-conductive materials have been developed that are 100% solids and have a very high aspect
ratio filling capability near 14:1. These materials work well in high aspect ratio designs and have
essentially no voids. The conductive fill materials are conductive when compared to pure epoxy.
However when compared with copper, the conductive materials are orders of magnitude lower (thermally
and electrically) than copper. The majority of the current and heat is conducted through the copper. So by
adding another 0.1 mil of copper thickness in the barrell, a via filled with non-conductive material will
carry more heat and current than a conductive filled via.

A large benefit of Via Fill is that the primary soldermask can now be flooded over the vias without the
reduced reliability. The soldermask is basically just covering a small depression in the copper. It also
reduces the registration requirements for the primary soldermask. This will reduce the height of the
soldermask under the BGA increasing assembly yields. The solderpaste stencil will sit lower on the board
since the flooded soldermask is thinner than Via Cap.

2003, Merix Corporation

When the BGAs have Via Fill and Via-In-Pad, the need for dogbones between the via pads and the BGA
land is removed (See Figure 1). In addition, 0402 passives can be placed directly over the vias on the
bottom side of the BGA reducing inductance rather than outside the perimeter of the BGA (See Figure 6).
A small increase in density is realized by being able to rout a few signals out on the surface as well.

The preferred method to communicate the requirements for Via Fill is:

1. The primary soldermask (top & bottom) data files should contain:
Features to be uncovered (lands, ICT pads, etc.): Aperture same size as external layer pad or
desired opening.
Via pads to be encroached by primary soldermask: Aperture same size as FHS (smaller than
external layer pad).
Vias to be filled: No aperture in the data if covered or aperture same size as external layer pad if
left open.

2. The Via Fill data file should contain:

Aperture the same size as FHS or external layer pad in the same location as the vias to be filled.
- Only one file is required as viewed from the top side of the board.

3. The fabrication drawing should contain notes similar to:

Soldermask apertures equal to the FHS are to have the primary soldermask encroached onto the
via pad. Soldermask apertures equal to the external layer pads shall be left open (standard
fabrication compensation). Cap vias with secondary soldermask from the top side per (viacap.top)
file and from the bottom side per (viacap.bot) file.
Via Fill is required: Vias identified in the (viafill.top) file must be completely filled with Peters
PP-2795 or equivalent 100% solids fill material, planarized, and plated over with copper and
surface finish. The plated cap must adhere to the fill material after 1x550F solder shock.

Note: The naming of the files is arbitrary, but all files in the data set should be listed in the Readme.txt
file with a description of what each file is to be used for. (See Guidelines for Tooling Interface).

Figure 6: Via-In-Pad. Microvia in pad (left), Filled plated-through via bottom of 1mm pitch BGA (right).

Via-In-Pad generically means that the BGA or SMT pad has a via within the land for the component. It
can refer to microvias, blind vias, or through vias in the lands. It does not imply any filling of the vias with
any material. If the desire is to have the vias filled to prevent solder drain, then the filling method needs to
be defined.

2003, Merix Corporation

Via-In-Pad is used to increase density on the external layers as well as reduce the inductance of the net.
Microvias in SMT lands are very common, but less common in BGA lands. On some designs which
employ Type 2 microvias (single depth microvias with a buried via from layer 2 to n-1), a less costly
approach would be filled through vias. Filled Via-In-Pad is a way to get intermediate density with an
intermediate cost. On 0.5mm pitch BGAs, microvia in the BGA land in the most common approach as the
pads are not typically large enough to allow plated through vias.

It is recommended to use microvias or Via Fill when employing Via-In-Pad technology. Some other
methods for Via-In-Pad cause issues at assembly and reliability concerns. Placing standard through vias
(no soldermask coverage) in a solderable pad leads to solder loss down the via resulting in a starved solder
joint. If the top of the via is in a solderable land and the bottom in a test pad, the lost solder creates a bump
that will cause false opens during ICT. If the through vias are capped or flooded with soldermask, then air
will be trapped inside the via with soldermask on one side and solder paste on the other. During IR reflow,
the air will expand and create a blow hole in the solder joint or blow the soldermask off the other side.
Either option creates challenges in assembly as will using deep blind in solderable lands. Using Via Fill
with Via-In-Pad results in no entrapped air during assembly.

No additional information is required to communicate Via-In-Pad. Just put the vias in the pads and follow
the communication requirements concerning encroachment, via fill, via cap, etc.

Conclusion:
This application note covered several soldermask plugging methods relative to vias and how they are
treated during various soldermask and via filling processes. The advantages of most methods are improved
assembly yields, reduced inductance, higher component density, and improved reliability. Via-In-Pad
works better with microvias and Via Fill than it does for the other methods. When performing Via Fill, the
reliability of the vias is dependent of the quality of the filling material. The new 100% solids materials are
better than the old non-conductive fill materials. Plugging vias with LPI or secondary soldermask prior to
surface finish results in reduced reliability.

The goal should be to design a PCB with the highest quality and lowest system cost while meeting the
reliability, and performance (thermal, mechanical, electrical, etc.) objectives. Soldermask encroachment
of the via is the least expensive method to reduce solder shorts in assembly. The most common method is
Via Cap as it covers the vias and prevents solder from coming to the top side of the board during wave
soldering. It also plugs the holes which assists in vacuum hold down of the board during ICT. Via Cap has
a small cost increase over a board with encroachment only. The highest cost alternative is Via Fill with a
conductive fill material. This method has limited capability with respect to aspect ratio, but works well in
some applications. An intermediate cost alternative is Via Fill with a non-conductive material which
results in higher circuit density (Via-In-Pad), higher assembly yields, and lower inductance.

Select the filling or soldermask plugging alternative that works best in your application. Communicate
your requirements clearly to ensure that the board is fabricated the way you expect. If you have any
additional questions, contact your Merix Field Applications Engineer.

(1) Technical Information: Plugging Processes,..., www.peters.de, TI 15/15, Lackwerke Peters.

(2) DuPont CB100 Datasheet.

2003, Merix Corporation