AGNIBHA DASGUPTA
Student of Dept. of Microelectronics & VLSI Technology
Maulana Abul Kalam Azad University of Technology, WB
(Formerly known as West Bengal University of Technology)
dasgupta.rony7@gmail.com
Abstract: The evolution and adaptation of the might be cheaper than sealing CMOS to obtain the same
microelectronics industry to the BICMOS technology performance improvement. On the other hand ,the high
and its extended families provide a paradigm shift in the cost of BICMOS may be justified by the high
development of high-speed, low-power digital and performance it can offer .In general ,the application itself
analog integrated circuits. It has been proven in most will dictate the technology that is to be used .If CMOS
literatures that the integration of bipolar and CMOS alone can satisfy the requirements ,then it is more cost
technologies are advantageous when used in optimized effective to use CMOS. Yet there are applications where
microelectronic circuitry in different applications such as the requirements can only be satisfied by using
telecommunications, mixed-signal, and radio-frequency CMOS .There are currently commercial BICMOS digital
microelectronics. However, some problems still arise products such as high speed SRAMs, fast
when it comes to the design of such integrated circuits microprocessors, and gate arrays in addition to digital,
due to its complexity. Nevertheless, researchers still analog and mixed signal BICMOS ASICs.
found ways to solve such problems using different The technology for BICMOS fabrication has matched
circuit configuration techniques. A review on the bipolar over the last decade, yet the development of circuits and
and CMOS technologies is riveted concentrating on their systems for such a technology is still lagging .There is a
basic properties, features and advantages when applied great interest among digital or analog circuits and
to microelectronic circuitry. The hybridization of bipolar systems designers to develop techniques to exploit the
and CMOS technologies is also discussed here showing flexibility that BICMOS offers.
its effectiveness that causes its emergence, including
factors that have driven the addition of bipolar
technology to CMOS, resulting into the emergence II. EVOLUTION OF BICMOS
BICMOS technology Most early BICMOS applications were analog;
BICMOS operational amplifiers were introduced in the
mid-70s followed by BICMOS power ICs. Digital LSI
BICMOS devices were introduced in the mid-80s,
I. INTRODUCTION motivated by high power dissipation of bipolar circuits,
BICMOS has faced, as any emerging technology, fierce speed limitations of MOS circuits & a need for high I/O
opposition, but nevertheless has been widely accepted. throughput .Development of VLSI BICMOS resulted in
The need for BICMOS has been and still is a very high performance memories, gate arrays & micro-
controversial issue .The cost of high performance processors BICMOS follows the same scaling curve as
BICMOS process speaks against it. However there are
mainstream CMOS technology resulting in explosive
other arguments supporting the need for such a
growth in BICMOS product growth. BICMOS has been
technology .The comparison between the cost of CMOS
and BICMOS is not trivial especially if we account for established as the technology of choice for high speed
the increasing expenses of sealing CMOS .In other VLSI.
words adding bipolar to an existing CMOS process
III. THE BICMOS PROCESS
BICMOS requires both bipolar junction and CMOS o High gain (BJT)
transistors, in which CMOS requires both nMOS and
pMOS transistors. In the creation of CMOS, one
o Low 1/f noise
complication is that an n- channel MOSFET requires a
p-type background, while a p-channel MOSFET requires
an n-type background. A CMOS process basically o >1 GHz toggle frequency
fabricates the circuit in bulk silicon. A single n-epitaxial
layer is used to implement both the PMOS transistors
and bipolar NPN transistors. Its resistivity is chosen so
that it can support both devices. An n+-buried layer is V. COMPARISON OF BICMOS AND
deposited below the epitaxial layer to reduce the CMOS TECHNOLOGIES
collector resistance of the bipolar device, which
simultaneously increases the immunity to latch up. The
p-buried layer improves the packing density, because the
collector-collector spacing of the bipolar devices can be The BICMOS gates perform in the same manner as
reduced. It comes at the expense of an increased the CMOS inverter in terms of power consumption,
collector-substrate capacitance. This technology opens a because both gates display almost no static power
wealth of new opportunities, because it is now possible consumption. When comparing BICMOS and CMOS in
to combine the high-density integration of MOS logic driving small capacitive loads, their performance are
with the current-driving capabilities of bipolar comparable, however, making BICMOS consume more
transistors. Another method which is much more power than CMOS. On the other hand, driving larger
capacitive loads makes BICMOS in the advantage of
superior to the use of bulk silicon is to use an insulating
consuming less power than CMOS, because the
substrate. However, the latter method is costly than the construction of CMOS inverter chains are needed to
previous one. drive large capacitance loads, which is not needed in
BICMOS. The BICMOS inverter exhibits a substantial
speed advantage over CMOS inverters, especially when
driving large capacitive loads. This is due to the bipolar
transistors capability of effectively multiplying its
current. For very low capacitive loads, the CMOS gate is
faster than its BICMOS counterpart due to small values
of Cint. This makes BICMOS ineffective when it comes to
the implementation of internal gates for logic structures
such as ALUs, where associated load capacitances are
small. BICMOS devices have speed degradation in the
Fig.1.1 Cross-Sectional view of BICMOS low supply voltage region and also BICMOS is having
greater manufacturing complexity than.
XI. Conclusion
XII. Reference
Books
Journals