BASIC THEORY: REGISTER

Storing and Data Transfer

The most common use of flip-flops is the storage and transfer of data or
information. Data may represent numerical values (for example binary numbers) or
some other data which have been coded in binary form. In general, data are stored
in groups of flip-flops called registers.

The most common operation applied to data stored in a FF is data transfer.

This operation implies transferring data from one FF to another one or from one
register to another one. This operation is illustrated in the following animation. The
animation on the left shows how data transfer can be realised between two S-C
clocked flip-flops in a synchronous way. The animation on the right shows the same
operation, but using J-K flip-flops. In any case, the logic value stored in FF A is
transferred to FF B when the rising or falling edge in the clock signal occurs. After
this transfer pulse the output of B will be the same as the output of A.

The operations shown above are examples of synchronous data transfer

because the synchronous and CLK inputs are used to perform the transfer.
The following animation shows how an asynchronous data transfer can be
performed by using the PRESET and CLEAR inputs (asynchronous inputs) of any
type of FF. The asynchronous inputs shown here are active at LOW logic levels.
When the enable transfer line is HIGH, one of the NAND outputs will switch to
LOW, depending on the A and A outputs and will thus set or reset the FF B to the
same state as A. This asynchronous transfer is independent of the synchronous and
CLK inputs of the FF and it is also known as jam transfer because data can get
"jammed" in the FF, even if its synchronous inputs are active.
Parallel Data Transfer

The following animation shows data transfer between two registers using D-
type flip-flops. Flip-Flops X1, X2. and X3 belong to register X, while flip-flops Y1, Y2,
and Y3 belong to register Y. When the transfer clock pulse is applied, the level
stored in X1 is transferred to Y1, X2 to Y2, and X3, to Y3. This transfer takes place in
a synchronous way and it is known as parallel transfer because the content of each
FF is transferred simultaneously to a parallel FF within another register. In serial
transfer the content of a register will be transferred one bit at a time. You will learn
this during the following experiments. It is important though to understand that
parallel transfer will not change the contents of the source register which keep their
values before and after the clock pulse.

Serial Data Transfer: Shift Registers

A shift register is a group of FF configured in such a way that the binary

numbers stored within the FF move from one FF to the next with each clock pulse.
Each FF adopts the value which was previously stored within the FF to the left. In the
following experiment you will see how each FF in a shift register adopts the value
determined by the conditions present at its J and K inputs when the rising or falling
edge at the clock pulse takes place.
 In terms of information processing registers are miniature memory units for
a small number of bits. Normally they serve for short-term storage of information.
The most simple register is the D flip-flop (Latch). More generally, an arrangement of
more than one flip-flop in series, triggered synchronously by one common clock
signal, is what is known as shift-register. Shift registers can also be made of J-K flip-
flops and then be used as counters in some special applications.

Shift registers are used mainly for the following tasks:

1. As buffer storage and memory (small and particularly fast).

2. For converting serial data into parallel data and parallel data into serial data.
3. For synchronisation and time delay of data.

In actual practice only synchronous shift registers are used. The design of
shift registers is based on the procedures used in designing synchronous counters.
The input functions for J and K are determined.

Parallel Vs. Serial Data Transfer

Parallel transfer means that the complete information is simultaneously

transferred at a clock pulse, no matter how many bits are transfererred. Serial
transfer requires N pulses so that the complete information (N bits) is transmitted. So
parallel transfer is much quicker than serial transfer using shift registers. However, in
parallel transfer the output of each FF in the register is connected to the
corresponding input in the next register, while in serial transfer only the last bit of
register X is connected to register Y. In parallel transfer more interconnections are
needed which is important to consider when transmitting a high number of bits
across long distances.

Selection between serial or parallel data transmission depends on each

particular application and on the specifications of a system. Usually a combination of
the two types of data transfer is used in order to take advantage of the speed of
parallel transfer and the simplicity and economy of serial transfer. You will see this in
the following experiments.

IEEE Symbol Example

The following picture shows the symbol used for latch groups and shift
registers. It is important that you keep it in mind because it later will be used in some
circuits. The ANSI symbol is similar to this one. When chip latches or registers are
used, you will find their corresponding symbols.
1. 4-bit Shift Register, Serial-In / Serial-Out
A. Aim

This experiment will allow you to look into the working principle of serial data
transmission using a flip-flop shift register.

B. Equipment

1. UniTrain-I Module

2. UniTrain-I Sequential Circuits Card SO4201-9T

3. Computer

4. Cable

C. Step

1. Look at the following flip-flop group and try to infer the way in which it will
behave. Complete the truth table accordingly. Do not confuse the logic
analyzer's outputs Q0 and Q1 with the FF outputs Q1, Q2, Q3, and Q4.

2. Assemble the shift register according to the previous diagram and the
following animation.
 We did not connect the R and S inputs of the flip-flops in this circuit. Actually
the inputs are internally connected to HIGH voltage. You can see it in the diagram. In
the previous experiments usually all inputs had been explicitly connected to the
UniTrain-I Interface in order to better illustrate their effect on the output. Now we will
just omit their explicit connection.

3. Open the Logic Analyzer and the workspace "4-bit shift register" and click
"OK".
4. Apply the outputs and read the inputs by clicking Settings | Start
Measurement at the menu or by pressing the "Start/Stop measurement"
button.

5. Copy the resulting screen with right click + Copy and paste it into the space
below with right click + Paste. Then answer the following question(s).
QUESTIONS:

1. According to the previous time diagram and truth table, what is the data
(number) at the Data input E which we are trying to transmit through this 4-bit
shift register?

Decimal 10 : 1010
Decimal 9: 1001
Decimal 2: 0010

3. How many clock pulses are necessary in order to read the desired complete
number at Q4 (serially)?
clock pulses

4. Which of the following statement(s) best describe the operation of the

previous shift register?
With every pulse clock the value at the output of the
previous flip-flop is transferred to the next one to the right.
The output value each FF will adopt after a falling edge is
determined by its SET and CLEAR inputs.
The first FF on the left is set or reset directly by the Data
input.
The output value each FF will adopt after a falling edge is
determined by its J and K inputs.
2. 4-bit Circular Shift Register

A. Aim
This experiment will allow you to look into the working principle of serial data
transmission using a circular flip-flop shift register.

B. Equipment

1. UniTrain-I Sequential Logic Circuits

2. UniTrain-I Sequential Circuits Card SO4201-9T

3. Computer

4. Cable

C. Step
1. Modify the connections of the circuit used in the previous experiment as
follows:
2. The data (number) we want to transmit this time through the circular
register is decimal 12 (1100). It will be set first by shortly connecting the S
and R inputs of the flip-flops to LOW (0V) as shown in the animation.

3. After having the flip-flops correctly set remove the cables from their
asynchronous inputs.
4. Open the Logic Analyzer and the workspace "Circular shift register" and
click "OK".
5. Apply the outputs and read the inputs by clicking Settings | Start
Measurement at the menu or by pressing the "Start/Stop measurement"
button.

6. Copy the resulting screen with right click + Copy and paste it into the
space below with right click + Paste.
7. Now set the data to decimal 1 (0001) by shortly connecting the S and R
inputs of the flip-flops to LOW (0V) as you did in the previous part of the
experiment. After having the flip-flops correctly set remove the cables from
their asynchronous inputs.
8. Run the measurement from the logic analyzer once more. Copy the
resulting screen with right click + Copy and paste it into the space below
with right click + Paste. Then answer the questions below.
QUESTIONS:

1. How many clock pulses are necessary in this case in order to read the desired
complete number at Q4 (serially)?
clock pulses

2. What is different from the simple shift register of the previous exercise
concerning the way the output moves through the register?
The circular shift register performs destructive readout, where
each bit is lost once it has been shifted out of the rightmost flip-flop.
The previous arrangement performed destructive readout, where
each bit is lost once it has been shifted out of the rightmost flip-flop.
There seems to be no difference.

3. Which of the following statements describes the operation of this circuit most
best?
The data pattern contained within the shift register will
recirculate as long as clock pulses are applied.
The rightmost bit is destructed or lost after it reaches the
last flip-flop.
The rightmost bit is fed once more to the first flip-flop.
3-bit Shift Register, Serial-In / Parallel-Out

A. Aim

This experiment will allow you to look into the working principle of parallel data
transmission using a flip-flop shift register.

B. Equipment

1. UniTrain-I Sequential Logic Circuits

2. UniTrain-I Sequential Circuits Card SO4201-9T

3. Computer

4. Cable

C. Step

1. Open the Logic Analyzer and the workspace "Shift Register SP 1" and click
"OK".
2. Apply the outputs and read the inputs by clicking Settings | Start
Measurement at the menu or by pressing the "Start/Stop measurement"
 button. Run the measurement at least twice, just to make sure the flip-
flops at the beginning had been correctly reset.

3. Copy the resulting screen with right click + Copy and paste it into the space
below with right click + Paste.

4. Repeat the previous steps for the workspace named "Shift Register SP 2".
Copy the resulting screen with right click + Copy and paste it into the space
below with right click + Paste.
5. Repeat the previous steps for the workspace named "Shift Register SP 3".
Copy the resulting screen with right click + Copy and paste it into the space
below with right click + Paste.
QUESTIONS:

1. Apart from FF 4 not being used do you notice any difference in the
connections as compared to the simple serial-in / serial-out 4-bit shift register?
There is no other difference in the connections as compared to the
simple 4-shift register.
Yes, this circuit is connected as a circular or ring shift register.
Yes, this time, the flip-flops are used in their asynchronous
configuration.

2. Observe the time diagrams obtained. Which workspace does the following
truth table correspond to?

"Shift Register SP 1"

"Shift Register SP 2"
"Shift Register SP 3"

3. Which is the data (number) which is serially going into the input of the shift
register from the previous truth table?

Decimal 3: 011
Decimal 1: 111
Decimal 6: 110

4. After how many clock pulses is the data from the previous answer available to
be read parallelly at bits Q1 to Q3?
The data is available at bits Q1 to Q3 after complete clock pulses.
5. What is(are) the main difference(s) between the first simple shift register for
serial-in / serial-out used two experiments before?

The way in which the data bits are transmitted.

The way in which the data bits are read.
The time after which the data is available is shorter for the serial-in /
parallel-out circuit.
The time after which the data is available is longer for the serial-in /
parallel-out circuit.