CT- 01 syllabus:

1. Weste Harris 2.2, 2.3 (full)

2. Threshold voltage Jacob baker (6.2)
3. Ratio less circuit - Pucknell (2.6 - 2.10)
4. CMOS inverter delay - Pucknell (4.7.1 - 4.8.1)
5. Beta ratio effects, noise margin, pass transistors - Harris (2.5.1 - 2.5.4)
6. Power consumption - Harris (chapter 5)

CT-02 syllabus:
1. Latch up in CMOS circuits: 2.13(page 57) - Pucknell
2. Pseudo NMOS, dynamic CMOS - 6.3.4 (page-159) - Pucknell
3. Driving large capacitive loads - 4.8(page 107) - Pucknell
4. CMOS logic - 1.4 (1.4.1-1.4.7) - Weste
5. Fabrication technology + layout design rules - 3.2, 3.3 Weste shortcut - CMOS
fabrication and layout - 1.5 (1.5.1-1.5.3) - Weste
6. Electro migration - 3.2.3 (page 68) - baker
Problem: - capacitance i.e. delay calculation from layout (tutorial exercise - 4.13(5))

CT-03 syllabus:
1. Examples of structured design: Parity generator (Pucknell - 6.4.1),
2. Bus arbitration logic for n-line bus (Pucknell - 6.4.2),
3. Multiplexers and general logic function block (Pucknell - 6.4.3-6.4.4).
4. Programmable logic array (PLA) design (Pucknell - Appendix - C).
5. Clocked sequential circuit design: two phase clocking (Pucknell - 6.5.1),
6. Charge storage (pucknell-6.5.2),
7. Inverting and non-inverting dynamic register element (pucknell-6.5.3),
8. Dynamic shift register - (Pucknell - 6.5.4)
9. For practice - Tutorial exercises - (Pucknell - 6.8)
10. Subsystem design process. Basic structure of 4-bit arithmetic processor: bus
architectures, shifter- [Pucknell - Chapter7 (full)],
11. Design of a general purpose ALU [Pucknell - 8.3(full)].
12. Interested people - Adder techniques (Pucknell - 8.4) - (not in syllabus but included in
term final).

CT-04 Syllabus:
1. Memory elements design: System time consideration, dynamic shift register, three
transistor and one transistor dynamic memory cell.
Pseudo-static RAM/register cell.
4 transistor dynamic and 6 transistor static CMOS memory cell.
4x4 bit register array and 16 bit static CMOS memory array - Pucknell (Chapter 9 except
9.2.6 and 9.2.7)
2. Finite State Machine design; design of Moore type and Melay type fsm using Verilog.
State minimization,
Algorithmic, digital system design. -Brown (Chapter 8 synchronous sequential circuits)
and Sirs 2 slides.