Colour Television Chassis

QFU1.1E
LA

Contents Page
1. Revision List 2
2. Technical Specs, Diversity, and Connections 2
3. Precautions, Notes, and Abbreviation List 5
4. Mechanical Instructions 9
5. Service Modes, Error Codes, and Fault Finding 20
6. Alignments 39
7. Circuit Descriptions 43
9. Block Diagrams
Wiring diagram 7000 series 40" 55
Wiring diagram 8000 series 40" 56
Wiring diagram 7000 series 46" 58
Wiring diagram 8000 series 46" 59
Wiring diagram 7000 series 55" 62
Wiring diagram 8000 series 55" 63
10. Circuit Diagrams and PWB Layouts Drawing PWB
B 310431365554 70 123-124
B 310431365664 125 177-178
E 272217190673 - 272217190698 Keyboard 179
J 272217190536 Sensor board 183 184
AL 310431365771 16 LED AmbiLight 203
AL 310431365781 15 LED AmbiLight 206
AL 310431365804 12 LED AmbiLight 209
AL 310431365813 10 LED AmbiLight 211
AL 310431365823 9 LED AmbiLight 214
AL 310431365833 7 LED AmbiLight 216
11. Styling Sheets
7000 series 40" 218
8000 series 40" 219
7000 series 46" 221
8000 series 46" 222
7000 series 55" 225
8000 series 55" 226

Published by ER/EL 1269 Quality Printed in the Netherlands Subject to modification EN 3122 785 19212
2012-Sep-14

2012 TP Vision Netherlands B.V.
All rights reserved. Specifications are subject to change without notice. Trademarks are the
property of Koninklijke Philips Electronics N.V. or their respective owners.
TP Vision Netherlands B.V. reserves the right to change products at any time without being obliged to adjust
earlier supplies accordingly.
PHILIPS and the PHILIPS Shield Emblem are used under license from Koninklijke Philips Electronics N.V.
 EN 2 1. QFU1.1E LA Revision List

1. Revision List
Manual xxxx xxx xxxx.0 Chapter 5: added white tone alignment values; see section
First release. 6.3.1.

Manual xxxx xxx xxxx.1 Manual xxxx xxx xxxx.2

Chapter 4: added additional LVDS cable handling info; see Chapter 2: Table 2-1 updated (added CTNs).
section 4.3.2.

2. Technical Specs, Diversity, and Connections

Index of this chapter:
2.1 Technical Specifications
2.2 Directions for Use
2.3 Connections 2.1 Technical Specifications
2.4 Chassis Overview For on-line product support please use the CTN links in Table
2-1. Here is product information available, as well as getting
Notes: started, user manuals, frequently asked questions and
Figures can deviate due to the different set executions. software & drivers.
Specifications are indicative (subject to change).

Table 2-1 Described Model Numbers and Diversity

2 4 7 9 10 11
Mechanics Descr. Block Diagrams Schematics Styling

E (Keyboard/Leading Edge)
Wire Dressing rear cover
Connection Overview

Assembly Removal

J (Sensor Board)
Control & Clock
Wiring Diagram
Wire Dressing

Power Supply
Power Supply

Supply lines
Audio

Sheet
Video

SSB
I2C

CTN
40PFL7007H/12 2.3 4-1 4-2 4.3 7.2 9.1 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.1
40PFL7007K/12 2.3 4-1 4-2 4.3 7.2 9.1 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.1
40PFL7007T/12 2.3 4-1 4-2 4.3 7.2 9.1 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.1
40PFL8007K/12 2.3 4-1 4-3 4.3 7.2 9.2 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.2
40PFL8007T/12 2.3 4-1 4-3 4.3 7.2 9.2 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.2
42PFL6907H/12 2.3 4-4 4-5 4.3 7.2 9.3 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.4 11.3
42PFL6907K/12 2.3 4-4 4-5 4.3 7.2 9.3 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.4 11.3
42PFL6907T/12 2.3 4-4 4-5 4.3 7.2 9.3 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.4 11.3
46PFL7007H/12 2.3 4-6 4-7 4.3 7.2 9.4 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.4
46PFL7007K/12 2.3 4-6 4-7 4.3 7.2 9.4 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.4
46PFL7007T/12 2.3 4-6 4-7 4.3 7.2 9.4 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.4
46PFL8007K/12 2.3 4-6 4-8 4.3 7.2 9.5 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.5
46PFL8007T/12 2.3 4-6 4-8 4.3 7.2 9.5 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.5
46PFL9707S/12 2.3 4-9 4-10 4.3 7.2 9.7 9.11 9.12 9.13 9.14 9.15 - 10.2 10.7 10.4 11.6
46PFL9707T/12 2.3 4-9 4-10 4.3 7.2 9.7 9.11 9.12 9.13 9.14 9.15 - 10.2 10.7 10.4 11.6
47PFL6907H/12 2.3 4-11 4-12 4.3 7.2 9.7 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.4 11.7
47PFL6907K/12 2.3 4-11 4-12 4.3 7.2 9.7 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.4 11.7
47PFL6907T/12 2.3 4-11 4-12 4.3 7.2 9.7 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.4 11.7
55PFL7007H/12 2.3 4-13 4-14 4.3 7.2 9.8 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.8
55PFL7007K/12 2.3 4-13 4-14 4.3 7.2 9.8 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.8
55PFL7007T/12 2.3 4-13 4-14 4.3 7.2 9.8 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.8
55PFL8007K/12 2.3 4-13 4-15 4.3 7.2 9.9 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.9
55PFL8007T/12 2.3 4-13 4-15 4.3 7.2 9.9 9.11 9.12 9.13 9.14 9.15 - 10.1 10.7 10.3 11.9
60PFL9607S/12 2.3 4-16 4-17 4.3 7.2 9.10 9.11 9.12 9.13 9.14 9.15 - 10.2 10.7 10.4 11.10
60PFL9607T/12 2.3 4-16 4-17 4.3 7.2 9.10 9.11 9.12 9.13 9.14 9.15 - 10.2 10.7 10.4 11.10

2.2 Directions for Use

You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com

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 Technical Specs, Diversity, and Connections QFU1.1E LA 2. EN 3

2.3 Connections

REAR CONNECTORS SIDE CONNECTORS

1 2 3 4 5 12
CI

SERV.U

13
NETWORK Y/Pb/Pr L/R AUDIO IN
DVI/VGA

USB 3

10

USB 2

10

BOTTOM REAR CONNECTORS HDMI 5

11
6 7 8 9 10 11 11 11
HDMI 4

11

DIGITAL
AUDIO OUT
(OPTICAL)

VGA SCART 75 SATELLITE USB 1 (1) (2) (3) 14

(RGB/CVBS)
TV ANTENNA HDMI

19210_062_120504.eps
120504

Figure 2-1 Connection overview (SATELLITE and HDMI5 are optional)

Note: The following connector colour abbreviations are used 2,4 - Cinch: Video YPbPr - In, Audio - In (via break-out
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= cable)
Grey, Rd= Red, Wh= White, Ye= Yellow. Gn - Video Y 1 VPP / 75 ohm jq
Bu - Video Pb 0.7 VPP / 75 ohm jq
2.3.1 Connections Rd - Video Pr 0.7 VPP / 75 ohm jq
Rd - Audio - R 0.5 VRMS / 10 kohm jq
Wh - Audio - L 0.5 VRMS / 10 kohm jq
1 - RJ45: Ethernet

3 - Service Connector (UART)

1 - Ground Gnd H
2 - UART_TX Transmit k
3 - UART_RX Receive j
10000_025_090121.eps
120320
5 - Cinch: Audio - In (VGA/DVI)
Figure 2-2 Ethernet connector Rd - Audio R 0.5 VRMS / 10 kohm jq
Wh - Audio L 0.5 VRMS / 10 kohm jq
1 - TD+ Transmit signal k
2 - TD- Transmit signal k 6 - VGA: Video RGB - In
3 - RD+ Receive signal j 1 5

4 - CT Centre Tap: DC level fixation 6

10

11 15
5 - CT Centre Tap: DC level fixation
10000_002_090121.eps
6 - RD- Receive signal j 090127
7 - GND Gnd H
8 - GND Gnd H Figure 2-3 VGA Connector

1 - Video Red 0.7 VPP / 75 ohm j

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 EN 4 2. QFU1.1E LA Technical Specs, Diversity, and Connections

2 - Video Green 0.7 VPP / 75 ohm j 10 - USB2.0

3 - Video Blue 0.7 VPP / 75 ohm j
4 - n.c.
1 2 3 4
5 - Ground Gnd H
10000_022_090121.eps
6 - Ground Red Gnd H 090121
7 - Ground Green Gnd H
8 - Ground Blue Gnd H Figure 2-5 USB (type A)
9 - +5VDC +5 V j
10 - Ground Sync Gnd H 1 - +5V k
11 - n.c. 2 - Data (-) jk
12 - DDC_SDA DDC data j 3 - Data (+) jk
13 - H-sync 0-5V j 4 - Ground Gnd H
14 - V-sync 0-5V j
15 - DDC_SCL DDC clock j
11 - HDMI 1, 2, 3, 4, 5 (optional): Digital Video - In, Digital
Audio with ARC - In/Out
7 - Video RGB - In, CVBS - In/Out, Audio - In/Out (via break-
19 1
out cable)
18 2
20 2
10000_017_090121.eps
090428

21 1
10000_001_090121.eps
Figure 2-6 HDMI (type A) connector
090121

Figure 2-4 SCART connector 1 - D2+ Data channel j

2 - Shield Gnd H
3 - D2- Data channel j
1 - Audio R 0.5 VRMS / 1 kohm k
4 - D1+ Data channel j
2 - Audio R 0.5 VRMS / 10 kohm j
5 - Shield Gnd H
3 - Audio L 0.5 VRMS / 1 kohm k
6 - D1- Data channel j
4 - Ground Audio Gnd H
7 - D0+ Data channel j
5 - Ground Blue Gnd H
8 - Shield Gnd H
6 - Audio L 0.5 VRMS / 10 kohm j
9 - D0- Data channel j
7 - Video Blue 0.7 VPP / 75 ohm jk
10 - CLK+ Data channel j
8 - Function Select 0 - 2 V: INT
11 - Shield Gnd H
4.5 - 7 V: EXT 16:9
12 - CLK- Data channel j
9.5 - 12 V: EXT 4:3 j
13 - Easylink/CEC Control channel jk
9 - Ground Green Gnd H
14 - ARC Audio Return Channel k
10 - n.c.
15 - DDC_SCL DDC clock j
11 - Video Green 0.7 VPP / 75 ohm j
16 - DDC_SDA DDC data jk
12 - n.c.
17 - Ground Gnd H
13 - Ground Red Gnd H
18 - +5V j
14 - Ground P50 Gnd H
19 - HPD Hot Plug Detect j
15 - Video Red 0.7 VPP / 75 ohm j
20 - Ground Gnd H
16 - Status/FBL 0 - 0.4 V: INT
1 - 3 V: EXT / 75 ohm j
17 - Ground Video Gnd H 12 - Head phone (Output)
18 - Ground FBL Gnd H Bk - Head phone 32 - 600 ohm / 10 mW ot
19 - Video CVBS/Y 1 VPP / 75 ohm k
20 - Video CVBS 1 VPP / 75 ohm j 13 - Common Interface
21 - Shield Gnd H 68p - See Figure 10-1-48 B07D, Common interface jk

8 - Aerial - In 14 - Cinch: S/PDIF - Out

- - IEC-type (EU) Coax, 75 ohm D Bk - Coaxial 0.4 - 0.6VPP / 75 ohm kq

9 - SAT - In (optional)
- - F-type Coax, 75 ohm D

2.4 Chassis Overview

Refer to chapter 9. Block Diagrams for PWB/CBA locations.

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 Precautions, Notes, and Abbreviation List
3. Precautions, Notes, and Abbreviation List
Index of this chapter:
3.1 Safety Instructions
3.2 Warnings
3.3 Notes
3.4 Abbreviation List
3.1 Safety Instructions
Safety regulations require the following during a repair:
Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).
Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard.
Safety regulations require that after a repair, the set must be
returned in its original condition. Pay in particular attention to
the following points:
Route the wire trees correctly and fix them with the
mounted cable clamps.
Check the insulation of the Mains/AC Power lead for
external damage.
Check the strain relief of the Mains/AC Power cord for
proper function.
Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the on position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 M and 12 M.
4. Switch off the set, and remove the wire between the
two pins of the Mains/AC Power plug.
Check the cabinet for defects, to prevent touching of any
inner parts by the customer.
3.2 Warnings
All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD w). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential.
Be careful during measurements in the high voltage
section.
Never replace modules or other components while the unit
is switched on.
When you align the set, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.
3.3 Notes
3.3.1 General
Measure the voltages and waveforms with regard to the
chassis (= tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for
NTSC (channel 3).
Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.
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QFU1.1E LA 3. EN 5
3.3.2 Schematic Notes
All resistor values are in ohms, and the value multiplier is
often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 k).
Resistor values with no multiplier may be indicated with
either an E or an R (e.g. 220E or 220R indicates 220 ).
All capacitor values are given in micro-farads ( 10-6),
nano-farads (n 10-9), or pico-farads (p 10-12).
Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
An asterisk (*) indicates component usage varies. Refer
to the diversity tables for the correct values.
The correct component values are listed on the Philips
Spare Parts Web Portal.
3.3.3 Spare Parts
For the latest spare part overview, consult your Philips Spare
Part web portal.
3.3.4 BGA (Ball Grid Array) ICs
Introduction
For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com. Select
Magazine, then go to Repair downloads. Here you will find
Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile.
Where applicable and available, this profile is added to the IC
Data Sheet information section in this manual.
3.3.5 Lead-free Soldering
Due to lead-free technology some rules have to be respected
by the workshop during a repair:
Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.
Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able:
To reach a solder-tip temperature of at least 400C.
To stabilize the adjusted temperature at the solder-tip.
To exchange solder-tips for different applications.
Adjust your solder tool so that a temperature of around
360C - 380C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch off unused equipment or
reduce heat.
Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
avoid mixed regimes. If this cannot be avoided, carefully
clear the solder-joint from old tin and re-solder with new tin.
3.3.6 Alternative BOM identification
It should be noted that on the European Service website,
Alternative BOM is referred to as Design variant.
The third digit in the serial number (example:
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the
specific TV set. In general, it is possible that the same TV
model on the market is produced with e.g. two different types
of displays, coming from two different suppliers. This will then
2012-Sep-14
 EN 6 3. QFU1.1E LA Precautions, Notes, and Abbreviation List

result in sets which have the same CTN (Commercial Type 6 = play 16 : 9 format, 12 = play 4 : 3
Number; e.g. 28PW9515/12) but which have a different B.O.M. format
number. AARA Automatic Aspect Ratio Adaptation:
By looking at the third digit of the serial number, one can algorithm that adapts aspect ratio to
identify which B.O.M. is used for the TV set he is working with. remove horizontal black bars; keeps
If the third digit of the serial number contains the number 1 the original aspect ratio
(example: AG1B033500001), then the TV set has been ACI Automatic Channel Installation:
manufactured according to B.O.M. number 1. If the third digit is algorithm that installs TV channels
a 2 (example: AG2B0335000001), then the set has been directly from a cable network by
produced according to B.O.M. no. 2. This is important for means of a predefined TXT page
ordering the correct spare parts! ADC Analogue to Digital Converter
For the third digit, the numbers 1...9 and the characters A...Z AFC Automatic Frequency Control: control
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be signal used to tune to the correct
indicated by the third digit of the serial number. frequency
AGC Automatic Gain Control: algorithm that
Identification: The bottom line of a type plate gives a 14-digit controls the video input of the feature
serial number. Digits 1 and 2 refer to the production centre (e.g. box
SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M. AM Amplitude Modulation
code, digit 4 refers to the Service version change code, digits 5 AP Asia Pacific
and 6 refer to the production year, and digits 7 and 8 refer to AR Aspect Ratio: 4 by 3 or 16 by 9
production week (in example below it is 2010 week 10 / 2010 ASF Auto Screen Fit: algorithm that adapts
week 17). The 6 last digits contain the serial number. aspect ratio to remove horizontal black
bars without discarding video
information
ATSC Advanced Television Systems
Committee, the digital TV standard in
the USA
ATV See Auto TV
Auto TV A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way
AV External Audio Video
AVC Audio Video Controller
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound
carrier distance is 5.5 MHz
BDS Business Display Solutions (iTV)
BLR Board-Level Repair
BTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
10000_053_110228.eps countries
110228 B-TXT Blue TeleteXT
C Centre channel (audio)
Figure 3-1 Serial number (example) CEC Consumer Electronics Control bus:
remote control bus on HDMI
3.3.7 Board Level Repair (BLR) or Component Level Repair connections
(CLR) CL Constant Level: audio output to
connect with an external amplifier
If a board is defective, consult your repair procedure to decide CLR Component Level Repair
if the board has to be exchanged or if it should be repaired on ComPair Computer aided rePair
component level. CP Connected Planet / Copy Protection
If your repair procedure says the board should be exchanged CSM Customer Service Mode
completely, do not solder on the defective board. Otherwise, it CTI Color Transient Improvement:
cannot be returned to the O.E.M. supplier for back charging! manipulates steepness of chroma
transients
CVBS Composite Video Blanking and
3.3.8 Practical Service Precautions
Synchronization
DAC Digital to Analogue Converter
It makes sense to avoid exposure to electrical shock. DBE Dynamic Bass Enhancement: extra
While some sources are expected to have a possible low frequency amplification
dangerous impact, others of quite high potential are of DCM Data Communication Module. Also
limited current and are sometimes held in less regard. referred to as System Card or
Always respect voltages. While some may not be Smartcard (for iTV).
dangerous in themselves, they can cause unexpected DDC See E-DDC
reactions that are best avoided. Before reaching into a D/K Monochrome TV system. Sound
powered TV set, it is best to test the high voltage insulation. carrier distance is 6.5 MHz
It is easy to do, and is a good service precaution. DFI Dynamic Frame Insertion
DFU Directions For Use: owner's manual
3.4 Abbreviation List DMR Digital Media Reader: card reader
0/6/12 SCART switch control signal on A/V DMSD Digital Multi Standard Decoding
board. 0 = loop through (AUX to TV), DNM Digital Natural Motion

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 Precautions, Notes, and Abbreviation List QFU1.1E LA 3. EN 7

DNR Digital Noise Reduction: noise The SDI signal is self-synchronizing,

reduction feature of the set uses 8 bit or 10 bit data words, and has
DRAM Dynamic RAM a maximum data rate of 270 Mbit/s,
DRM Digital Rights Management with a minimum bandwidth of 135
DSP Digital Signal Processing MHz.
DST Dealer Service Tool: special remote iTV Institutional TeleVision; TV sets for
control designed for service hotels, hospitals etc.
technicians LS Last Status; The settings last chosen
DTCP Digital Transmission Content by the customer and read and stored
Protection; A protocol for protecting in RAM or in the NVM. They are called
digital audio/video content that is at start-up of the set to configure it
traversing a high speed serial bus, according to the customer's
such as IEEE-1394 preferences
DVB-C Digital Video Broadcast - Cable LATAM Latin America
DVB-T Digital Video Broadcast - Terrestrial LCD Liquid Crystal Display
DVD Digital Versatile Disc LED Light Emitting Diode
DVI(-d) Digital Visual Interface (d= digital only) L/L' Monochrome TV system. Sound
E-DDC Enhanced Display Data Channel carrier distance is 6.5 MHz. L' is Band
(VESA standard for communication I, L is all bands except for Band I
channel and display). Using E-DDC, LPL LG.Philips LCD (supplier)
the video source can read the EDID LS Loudspeaker
information form the display. LVDS Low Voltage Differential Signalling
EDID Extended Display Identification Data Mbps Mega bits per second
(VESA standard) M/N Monochrome TV system. Sound
EEPROM Electrically Erasable and carrier distance is 4.5 MHz
Programmable Read Only Memory MHEG Part of a set of international standards
EMI Electro Magnetic Interference related to the presentation of
EPG Electronic Program Guide multimedia information, standardised
EPLD Erasable Programmable Logic Device by the Multimedia and Hypermedia
EU Europe Experts Group. It is commonly used as
EXT EXTernal (source), entering the set by a language to describe interactive
SCART or by cinches (jacks) television services
FDS Full Dual Screen (same as FDW) MIPS Microprocessor without Interlocked
FDW Full Dual Window (same as FDS) Pipeline-Stages; A RISC-based
FLASH FLASH memory microprocessor
FM Field Memory or Frequency MOP Matrix Output Processor
Modulation MOSFET Metal Oxide Silicon Field Effect
FPGA Field-Programmable Gate Array Transistor, switching device
FTV Flat TeleVision MPEG Motion Pictures Experts Group
Gb/s Giga bits per second MPIF Multi Platform InterFace
G-TXT Green TeleteXT MUTE MUTE Line
H H_sync to the module MTV Mainstream TV: TV-mode with
HD High Definition Consumer TV features enabled (iTV)
HDD Hard Disk Drive NC Not Connected
HDCP High-bandwidth Digital Content NICAM Near Instantaneous Compounded
Protection: A key encoded into the Audio Multiplexing. This is a digital
HDMI/DVI signal that prevents video sound system, mainly used in Europe.
data piracy. If a source is HDCP coded NTC Negative Temperature Coefficient,
and connected via HDMI/DVI without non-linear resistor
the proper HDCP decoding, the NTSC National Television Standard
picture is put into a snow vision mode Committee. Color system mainly used
or changed to a low resolution. For in North America and Japan. Color
normal content distribution the source carrier NTSC M/N= 3.579545 MHz,
and the display device must be NTSC 4.43= 4.433619 MHz (this is a
enabled for HDCP software key VCR norm, it is not transmitted off-air)
decoding. NVM Non-Volatile Memory: IC containing
HDMI High Definition Multimedia Interface TV related data such as alignments
HP HeadPhone O/C Open Circuit
I Monochrome TV system. Sound OSD On Screen Display
carrier distance is 6.0 MHz OAD Over the Air Download. Method of
I 2C Inter IC bus software upgrade via RF transmission.
I2D Inter IC Data bus Upgrade software is broadcasted in
I2S Inter IC Sound bus TS with TV channels.
IF Intermediate Frequency OTC On screen display Teletext and
IR Infra Red Control; also called Artistic (SAA5800)
IRQ Interrupt Request P50 Project 50: communication protocol
ITU-656 The ITU Radio communication Sector between TV and peripherals
(ITU-R) is a standards body PAL Phase Alternating Line. Color system
subcommittee of the International mainly used in West Europe (colour
Telecommunication Union relating to carrier = 4.433619 MHz) and South
radio communication. ITU-656 (a.k.a. America (colour carrier
SDI), is a digitized video format used PAL M = 3.575612 MHz and
for broadcast grade video. PAL N = 3.582056 MHz)
Uncompressed digital component or PCB Printed Circuit Board (same as PWB)
digital composite signals can be used. PCM Pulse Code Modulation

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 EN 8 3. QFU1.1E LA Precautions, Notes, and Abbreviation List

PDP Plasma Display Panel SWAN Spatial temporal Weighted Averaging

PFC Power Factor Corrector (or Pre- Noise reduction
conditioner) SXGA 1280 1024
PIP Picture In Picture TFT Thin Film Transistor
PLL Phase Locked Loop. Used for e.g. THD Total Harmonic Distortion
FST tuning systems. The customer TMDS Transmission Minimized Differential
can give directly the desired frequency Signalling
POD Point Of Deployment: a removable TS Transport Stream
CAM module, implementing the CA TXT TeleteXT
system for a host (e.g. a TV-set) TXT-DW Dual Window with TeleteXT
POR Power On Reset, signal to reset the uP UI User Interface
PSDL Power Supply for Direct view LED uP Microprocessor
backlight with 2D-dimming UXGA 1600 1200 (4:3)
PSL Power Supply with integrated LED V V-sync to the module
drivers VESA Video Electronics Standards
PSLS Power Supply with integrated LED Association
drivers with added Scanning VGA 640 480 (4:3)
functionality VL Variable Level out: processed audio
PTC Positive Temperature Coefficient, output toward external amplifier
non-linear resistor VSB Vestigial Side Band; modulation
PWB Printed Wiring Board (same as PCB) method
PWM Pulse Width Modulation WYSIWYR What You See Is What You Record:
QRC Quasi Resonant Converter record selection that follows main
QTNR Quality Temporal Noise Reduction picture and sound
QVCP Quality Video Composition Processor WXGA 1280 768 (15:9)
RAM Random Access Memory XTAL Quartz crystal
RGB Red, Green, and Blue. The primary XGA 1024 768 (4:3)
color signals for TV. By mixing levels Y Luminance signal
of R, G, and B, all colors (Y/C) are Y/C Luminance (Y) and Chrominance (C)
reproduced. signal
RC Remote Control YPbPr Component video. Luminance and
RC5 / RC6 Signal protocol from the remote scaled color difference signals (B-Y
control receiver and R-Y)
RESET RESET signal YUV Component video
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
d'Appareils Radiorcepteurs et
Tlviseurs
SCL Serial Clock I2C
SCL-F CLock Signal on Fast I2C bus
SD Standard Definition
SDA Serial Data I2C
SDA-F DAta Signal on Fast I2C bus
SDI Serial Digital Interface, see ITU-656
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mmoire.
Colour system mainly used in France
and East Europe. Colour
carriers = 4.406250 MHz and
4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link
standard
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
SSC Spread Spectrum Clocking, used to
reduce the effects of EMI
STB Set Top Box
STBY STand-BY
SVGA 800 600 (4:3)
SVHS Super Video Home System
SW Software

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 Mechanical Instructions QFU1.1E LA 4. EN 9

4. Mechanical Instructions
Index of this chapter:
4.1 Cable Dressing
4.2 Service Positions
4.3 Assy/Panel Removal
4.4 Set Re-assembly
Notes:
Figures below can deviate slightly from the actual situation,
due to the different set executions.

4.1 Cable Dressing

19210_069_120504.eps
120504

Figure 4-1 Cable dressing 40" 7000/8000 series

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 EN 10 4. QFU1.1E LA Mechanical Instructions

19210_070_120504.eps
120504

Figure 4-2 Cable dressing 40" rear cover 7000 series

19210_071_120504.eps
120504

Figure 4-3 Cable dressing 40" rear cover 8000 series

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 Mechanical Instructions QFU1.1E LA 4. EN 11

19212_001_120912.eps
120912

Figure 4-4 Cable dressing 42" 6900 series

19212_002_120912.eps
120912

Figure 4-5 Cable dressing 42" rear cover 6900 series

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 EN 12 4. QFU1.1E LA Mechanical Instructions

19210_072_120504.eps
120504

Figure 4-6 Cable dressing 46" 7000/8000 series

19210_073_120504.eps
120504

Figure 4-7 Cable dressing 46" rear cover 7000 series

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 Mechanical Instructions QFU1.1E LA 4. EN 13

19210_074_120504.eps
120504

Figure 4-8 Cable dressing 46" rear cover 8000 series

19212_003_120912.eps
120912

Figure 4-9 Cable dressing 46" 9707 series

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 EN 14 4. QFU1.1E LA Mechanical Instructions

19212_004_120912.eps
120912

Figure 4-10 Cable dressing 46" rear cover 9707 series

19212_005_120912.eps
120912

Figure 4-11 Cable dressing 47" 6900 series

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 Mechanical Instructions QFU1.1E LA 4. EN 15

19212_006_120912.eps
120912

Figure 4-12 Cable dressing 47" rear cover 6900 series

19210_103_120516.eps
120516

Figure 4-13 Cable dressing 55" 7000/8000 series

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 EN 16 4. QFU1.1E LA Mechanical Instructions

bl e
i l a
va
t a
No
19210_104_120516.eps
120516

Figure 4-14 Cable dressing 55" rear cover 7000 series

19210_105_120516.eps
120516

Figure 4-15 Cable dressing 55" rear cover 8000 series

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 Mechanical Instructions QFU1.1E LA 4. EN 17

19212_007_120912.eps
120912

Figure 4-16 Cable dressing 60" 9607 series

19212_008_120912.eps
120912

Figure 4-17 Cable dressing 60" rear cover 9607 series

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 EN 18 4. QFU1.1E LA Mechanical Instructions

4.2 Service Positions

For easy servicing of a TV set, the set should be put face down
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the
display. Caution: Failure to follow these guidelines can 4.3 Assy/Panel Removal
seriously damage the display!
Ensure that ESD safe measures are taken.

4.3.1 Rear Cover

Warning: Disconnect the mains power cord before removing

the rear cover.
Attention: All sets are equipped with a hatch to disconnect the
keyboard control panel. Ambilight sets are in addition equipped
with a hatch to disconnect the Ambilight units.
These hatches are indicated on the rear cover with
SERVICE h.
It is mandatory to open the hatches and disconnect the 4
cables prior to removal of the rear cover! 3
See Figure 4-18 and Figure 4-19 for details.
1. For sets equipped with Ambilight: open the hatch that 4
covers the Ambilight connector and unplug the connector
[1].
2. Remove the hatch that covers the keyboard control panel 4
connector by removing the screws [3].
3. For sets equipped with Ambilight: remove the stand and 3
3
swivel block [4].
4. Unplug the keyboard control panel connector located
underneath the keyboard control hatch.
19300_054_120418.eps
5. Remove remaining fixation screws. 120418
6. Lift the rear cover from the TV. Make sure that wires and
flat foils are not damaged while lifting the rear cover from Figure 4-19 Rear cover removal -all models -2-
the set.
4.3.2 SSB

Refer to Figure 4-20 and Figure 4-21 for details.

Some SSBs have a dedicated LVDS connector, requiring
pressing two catches as indicated in the figure, before
removing the LVDS cable.
1

19054_001_111010.eps
19300_053_120418.eps 111010
120418

Figure 4-20 SSB LVDS connector catches (optional) -1-

Figure 4-18 Rear cover removal -all models -1-

Upon re-connecting the LVDS cable, ensure the catches are

locked after having inserted the LVDS cable.

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 Mechanical Instructions QFU1.1E LA 4. EN 19

4.4 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse
order.

Notes:
Click!
While re-assembling, make sure that all cables are placed
and connected in their original position.
Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.

LVDS flat foil

Click!

19222_001_120626.eps
120626

Figure 4-21 SSB LVDS connector catches (optional) -2-

Underneath the SSB an adhesive heat path is located.

Refer to Figure 4-22 for details.
After board swap, it should be located at the correct position.

19210_089_120509.eps
120509

Figure 4-22 SSB adhesive heath path

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 EN 20 5. QFU1.1E LA Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding

Index of this chapter: Note: It is possible that, together with the SDM, the main
5.1 Test Points menu will appear. To switch it off, push the MENU (or
5.2 Service Modes "HOME") button again.
5.3 Start-up Analogue SDM can also be activated by grounding the
5.4 Service Tools solder path on the SSB, with the indication SDM (see
5.5 Error Codes figures Service mode pad - front) and Service mode pad -
5.6 The Blinking LED Procedure back.
5.7 Protections Digital SDM: use the RC-transmitter and key in the code
5.8 Fault Finding and Repair Tips 062593, directly followed by the MENU (or "HOME")
5.9 Software Upgrading button.
Note: It is possible that, together with the SDM, the main
5.1 Test Points menu will appear. To switch it off, push the MENU (or
As most signals are digital, it will be difficult to measure "HOME") button again.
waveforms with a standard oscilloscope. However, several key
ICs are capable of generating test patterns, which can be
controlled via ComPair. In this way it is possible to determine
which part is defective.

Perform measurements under the following conditions:

Service Default Mode.
Video: Colour bar signal.
Audio: 3 kHz left, 1 kHz right.

SDM
5.2 Service Modes
Service Default mode (SDM) and Service Alignment Mode
(SAM) offers several features for the service technician, while
the Customer Service Mode (CSM) is used for communication
between the call centre and the customer.

This chassis also offers the option of using ComPair, a

19210_082_120507.eps
hardware interface between a computer and the TV chassis. It
120507
offers the abilities of structured troubleshooting, error code
reading, and software version read-out for all chassis. Figure 5-1 Service mode pad - front
(see also section 5.4.1 ComPair).

Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the
activation of the Service modes. For instance the old MENU
button is now called HOME (or is indicated by a house icon).

5.2.1 Service Default Mode (SDM)

Purpose SDM
To create a pre-defined setting, to get the same
measurement results as given in this manual.
To override SW protections detected by the standby
processor and make the TV start up to the step just before
protection. See section 5.3 Start-up.
To start the blinking LED procedure where only LAYER 2
errors are displayed. (see also section 5.5 Error Codes).
19210_083_120507.eps
120507
Specifications
Figure 5-2 Service mode pad - back
Table 5-1 SDM default settings
After activating this mode, SDM will appear in the upper right
Region Freq. (MHz) Default system corner of the screen (when a picture is available).
Europe, AP(PAL/Multi) 475.25 PAL B/G
Europe, AP DVB-T 546.00 PID Video: 0B DVB-T How to Exit SDM
06 PID PCR: 0B 06 PID
Audio: 0B 07
Use one of the following methods:
Switch the set to STANDBY via the RC-transmitter.
Via a standard customer RC-transmitter: key in 00-
All picture settings at 50% (brightness, colour, contrast). sequence.
Sound volume at 25%.
5.2.2 Service Alignment Mode (SAM)
How to Activate SDM
For this chassis there are two kinds of SDM: an analogue SDM Purpose
and a digital SDM. Tuning will happen according Table 5-1. To perform (software) alignments.
Analogue SDM: use the RC-transmitter and key in the To change option settings.
code 062596, directly followed by the MENU (or To easily identify the used software version.
HOME) button. To view operation hours.
To display (or clear) the error code buffer.

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 Service Modes, Error Codes, and Fault Finding
How to Activate SAM
Via a standard RC transmitter: Key in the code 062596
directly followed by the INFO or OK button. After activating
SAM with this method a service warning will appear on the
screen, continue by pressing the OK button on the RC.
Contents of SAM
Hardware Info.
A. SW Version. Displays the software version of the
main software (example: QF1XX-1.2.3.4 =
AAABB_X.Y.W.Z).
AAA= the chassis name.
BB= Product ID.
X.Y.W.Z= the software version, where X is the
main version number (different numbers are not
compatible with one another) and Y.W.Z is the sub
version number (a higher number is always
compatible with a lower number).
B. Standby processor version. Displays the software
version of the standby processor.
C. Production Code. Displays the production code of
the TV, this is the serial number as printed on the back
of the TV set. Note that if an NVM is replaced or is
initialized after corruption, this production code has to
be re-written to NVM. The update can be done via the
NVM editor available in SAM.
Operation hours. Displays the accumulated total of
operation hours (not the standby hours). Every time the TV
is switched on/off, 0.5 hours is added to this number.
Errors (followed by maximum 10 errors). The most recent
error is displayed at the upper left (for an error explanation
see section 5.5 Error Codes).
Reset Error Buffer. When cursor right (or OK button)
pressed here, followed by the OK button, the error buffer
is reset.
Alignments. This will activate the ALIGNMENTS sub-
menu. See Chapter 6. Alignments.
Options numbers. Extra features for Service. For more
info regarding option codes, see chapter 6. Alignments.
Note that if the option code numbers are changed, these
have to be confirmed with pressing the OK button before
the options are stored, otherwise changes will be lost.
Initialise NVM. The moment the processor recognizes a
corrupted NVM, the initialise NVM line will be highlighted.
Now, two things can be done (dependent of the service
instructions at that moment):
Save the content of the NVM via ComPair for
development analysis, before initializing. This will give
the Service department an extra possibility for
diagnosis (e.g. when Development asks for this).
Initialise the NVM.
Note: When the NVM is corrupted, or replaced, there is a high
possibility that no picture appears because the display code is
not correct. So, before initializing the NVM via the SAM, a
picture is necessary and therefore the correct display option
has to be entered. Refer to Chapter 6. Alignments for details.
To adapt this option, its advised to use ComPair (the correct
values for the options can be found in Chapter 6. Alignments)
or a method via a standard RC (described below).
Changing the display option via a standard RC: Key in the
code 062598 directly followed by the MENU (or "HOME")
button and XXX (where XXX is the 3 digit decimal display
code as mentioned on the sticker in the set). Make sure to key
in all three digits, also the leading zeros. If the above action is
successful, the front LED will go out (Standby) as an indication
that the RC sequence was correct. After the display option is
changed in the NVM, the TV will go to the Standby mode. If the
NVM was corrupted or empty before this action, it will be
initialized first (loaded with default values). This initializing can
take up to 20 seconds.
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QFU1.1E LA 5. EN 21
Display Option
Code
39mm
PHILIPS 040
27mm
MODEL:
32PF9968/10
PROD.SERIAL NO:
AG 1A0620 000001
(CTN Sticker)
10000_038_090121.eps
090819
Figure 5-3 Location of Display Option Code sticker
Store - go right. All options and alignments are stored
when pressing cursor right or the OK button.
Software maintenance.
SW Events. In case of specific software problems, the
development department can ask for this info.
HW Events. In case of specific software problems, the
development department can ask for this info :
- Event 26: refers to a power dip, this is logged after
the TV set reboots due to a power dip.
- Event 17: refers to the power OK status, sensed even
before the 3 x retry to generate the error code.
Test settings. For development purposes only.
RF4CE pairing tables. Clear paired remote control. Re-
pairing (coldboot of platform possibly needed) can be done
by pressing the red/blue hot keys simultaneously for a few
seconds.(be sure the distance between the remote control
and TV set RF4CE receiver is less then 30cm). Message
like Pairing successful, confirms the match-make.
Development 1 file versions. Not useful for Service
purposes, this information is mainly used by the
development department.
Development 2 file versions. Not useful for Service
purposes, this information is mainly used by the
development department.
Upload to USB. To upload several settings from the TV to
an USB stick, which is connected to the SSB. The items are
Personal settings, Option codes, Alignments,
Identification data (includes the set type and prod code +
all 12NC like SSB, display, boards), History list. The All
item supports the upload of all several items at once.
A directory repair\ will be created in the root of the
USB stick.
To upload the settings, select each item separately, press
cursor right (or the OK button), confirm with OK and
wait until the message Done appears. In case the
download to the USB stick was not successful, Failure will
be displayed. In this case, check if the USB stick is
connected properly and if the directory repair is present in
the root of the USB stick. Now the settings are stored onto
the USB stick and can be used to download into another TV
or other SSB. Uploading is of course only possible if the
software is running and preferably a picture is available.
This method is created to be able to save the customers
TV settings and to store them into another SSB.
Important remark : to upload the channel list, select
Home => Setup => TV settings => General settings
=> Channel list copy => Copy to USB.The procedure is
also described in the (electronic) user manual.
Download from USB. To download several settings from
the USB stick to the TV, same way of working needs to be
followed as described in Upload to USB. The All item
supports to download all several items at once.
Important remark : to download the channel list, select
Home => Setup => TV settings => General settings
=> Channel list copy => Copy to TV. The procedure is
also described in the (electronic) user manual.
NVM editor. For Smart TV the set Type number must be
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 EN 22 5. QFU1.1E LA Service Modes, Error Codes, and Fault Finding
entered correctly.
Also the Production code (factory location code), 12NC
SSB, 12NC display and 12NC supply can be entered
here via the RC-transmitter.Be sure the cursor is put fully
to the left (use back key) of the dialog box before enter the
new data.
Correct data can be found on the side/rear sticker.
How to Navigate
In SAM, the menu items can be selected with the
CURSOR UP/DOWN key on the RC-transmitter. The
selected item will be highlighted. When not all menu items
fit on the screen, move the CURSOR UP/DOWN key to
display the next/previous menu items.
With the CURSOR LEFT/RIGHT keys, it is possible to:
(De) activate the selected menu item.
(De) activate the selected sub menu.
With the OK key, it is possible to activate the selected
action.
How to Exit SAM
Use one of the following methods:
Switch the TV set to STAND-BY via the RC-transmitter.
Via a standard RC-transmitter, key in 00 sequence, or
select the BACK key.
5.2.3 Customer Service Mode (CSM)
Purpose
When a customer is having problems with his TV-set, he can
call his dealer or the Customer Helpdesk. The service
technician can then ask the customer to activate the CSM, in
order to identify the status of the set. Now, the service
technician can judge the severity of the complaint. In many
cases, he can advise the customer how to solve the problem,
or he can decide if it is necessary to visit the customer.
The CSM is a read only mode; therefore, modifications in this
mode are not possible.
Provided CSM is activated, every menu from CSM can be used
as check for the back end chain video.So for all CSM content
displayed, it could be determined that the back end video chain
is working.
When CSM is activated and there is a USB stick connected to
the TV set, the software will dump the CSM content to the USB
stick. The file (CSM_model number_serial number.txt) will be
saved in the root of the USB stick. This info can be handy if no
information is displayed.
Additional in CSM mode (with USB stick connected), pressing
OK will create an extended CSM dump file on the USB stick.
This file (Extended_CSM_model number_serial number.txt)
contains:
The normal CSM dump information,
All items (from SAM load to USB, but in readable format),
Operating hours,
Error codes,
SW/HW event logs.
To have fast feedback from the field, a flashdump can be
requested by development. When in CSM, push the red
button and key in serial digits 2679 (same keys to form the
word COPY with a cellphone). A file Dump_model
number_serial number.bin will be written on the connected
USB device. This can take 1/2 minute, depending on the
quantity of data that needs to be dumped.
Also when CSM is activated, the LAYER 1 error is displayed via
blinking LED.(see also section 5.5 Error Codes).
How to Activate CSM
Key in the code 123654 via the standard RC transmitter.
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Note: Activation of the CSM is only possible if there is no (user)
menu on the screen!
How to Navigate
By means of the CURSOR-DOWN/UP knob on the RC-
transmitter, can be navigated through the menus.
Contents of CSM
The contents are reduced to 3 pages: General, Software
versions and Quality items. The group names itself are not
shown anywhere in the CSM menu.
General
Set type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it
is not necessary for the customer to look at the rear of the
TV set. Note that if an NVM is replaced or is initialized after
corruption, the set type content has to be re-written to
NVM.The update can be done via the NVM editor available
in SAM.
Production code. Displays the production code (the serial
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, the production code content has
to be re-written to NVM. The update can be done via the
NVM editor available in SAM.
Installed date. Indicates the date of the first installation of
the TV. This date is acquired by time extraction.
Options 1. Displays the option codes numbers of option
group 1 as set in SAM (Service Alignment Mode).
Options 2. Displays the option codes numbers of option
group 2 as set in SAM (Service Alignment Mode).
12NC SSB. Gives an identification of the SSB as stored in
NVM. Note that if an NVM is replaced or is initialized after
corruption, this identification number has to be re-written to
NVM. The update can be done via the NVM editor available
in SAM. This identification number is the 12nc number of
the SSB.
12NC display. Shows the 12NC of the display. Note that if
an NVM is replaced or is initialized after corruption, this
identification number has to be re-written to NVM. The
update can be done via the NVM editor available in SAM.
12NC supply. Shows the 12NC of the power supply. Note
that if an NVM is replaced or is initialized after corruption,
this identification number has to be re-written to NVM. The
update can be done via the NVM editor available in SAM.
12NC RF4CE board. Shows the 12NC of the RF4CE
board.
Software versions
Current main software. Displays the build-in main
software version. In case of field problems related to
software, software can be upgraded. As this software is
consumer upgradeable, it will also be published on the
Internet.
Example: QF1xx-1.2.3.4
Standby software. Displays the build-in standby
processor software version. Upgrading this software will be
possible via USB (see section 5.9 Software Upgrading).
Example: STDBY_61.0.0.7
e-UM version. Displays the electronic user manual SW-
version (12NC version number). Most significant number
here is the last digit.
Strings database version. Reflects the latest embedded
string database version .
FPGA video version.Displays the Scan/backlight FPGA
software version.Device processes the backlight + boost
pwm control, scanning, 3D drive and ambilight buffering.
3D dongle software version.Not applicable.
FRC-V software.Not applicable.
RF4CE software.Embedded software version located on
the RF4CE board.
FPGA lattice backlight software.
FPGA HDR software.
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 Service Modes, Error Codes, and Fault Finding QFU1.1E LA 5. EN 23

Quality items How to Exit CSM

Signal quality. Bad / average /good (not for DVB-S). Press MENU (or "HOME") / Back key on the RC-transmitter.
Ethernet MAC address. Displays the MAC address
present in the SSB. 5.3 Start-up
Wireless MAC address. Displays the wireless MAC As described, the start-up diagrams below, documents which
address to support the Wi-Fi functionality. supplies are present at any certain moment.
BDS key. Indicates if the set is in the BDS status.
CI module. Displays status if the common interface
module is detected.
CI + protected service. Yes/No.
Event counter :
S : 000X 0000(number of software recoveries : SW
EVENT-LOG #(reboots)
S : 0000 000X (number of software events : SW EVENT-
LOG #(events)
H : 000X 0000(number of hardware errors)
H : 0000 000X (number of hardware events : SW EVENT-
LOG #(events).
Coldboot counter. Neglect BDS mode settings
Fastcoldboot counter. Neglect BDS mode settings
Hotboot counter. Neglect BDS mode settings
Application hotboot counter. Neglect BDS mode
settings

Off
Mains Mains
off on

- WakeUp requested WakeUp

- Acquisition needed requested

St by Semi
- stby requested and Active
no data Acquisition St by St by
required requested

GoToProtection
(triggered during startup
by standby P) WakeUp
requested
(SDM)
GoToProtection
GoToProtection

Protection
On

19210_076_120504.eps
120504

Figure 5-4 Transition diagram

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 EN 24 5. QFU1.1E LA Service Modes, Error Codes, and Fault Finding

Off
AC~ Mains is applied Stand by or
Protection
Standby Supply starts running.
All standby supply voltages become available.

st-by P resets, resulting in a high impedant output

stage of the I/O ports.

Initialise I/O pins of the st-by P

- Keep AVC system in reset (internal signal)
- Switch RESET-FUSION-OUTn LOW
- Switch RESET-HDMI-MUXn LOW
- Switch RESET-ETHERNETn LOW
- Switch AUDIO-MUTEn LOW
- Switch SPLASH-ON LOW
- Switch LCD-PWR-ONn High
If the protection state was left by short circuiting the
SDM pins, detection of a protection condition during
startup shall stall the startup. Protection conditions
occuring in a playing set shall be ignored. The
protection mode shall not be entered.

Switch ENABLE-WOLAN high to power Ethernet PHY

and Wifi dongle Switch ENABLE-WOLANn high to power Ethernet
PHY and internal Wifi dongle if Networked Standby
was Off in the Standby mode.
start keyboard scanning, RC detection.
Wake up reasons are off.

Switch ON Platform supply by switching High the

STANDBYn line.

Startup shall continue from the

moment a valid detection is received.
12V platform is turned on, automatically enabling the
low voltage DCDC converter outputs

12V error:
Detect2 high received
No Layer1: 3
within 2 seconds?
Layer2: 16

Yes
Enter protection
Wait 300ms

Enable the supply detection algorithm

All display related I/O lines should be
LOW as long as the Tcon is not
powered to avoid leakage current and
tcon startup problems.
Start AVC system These lines will furtheron be
dynamically controlled by the mainSW.
No

Switch following lines asap:(part of preBOOT)

(GPIO2): LOW
CTRL-DISP2 (GPIO3): LOW
CTRL-DISP3 (GPIO8): LOW
CTRL-DISP4 (BKLGON): LOW
3D-LR (PWM0): LOW
BL-SPI-CS_BL-I-CTRL (PWM1): LOW
BL-DIM (BOOST): LOW Small delay between AVC boot and
other platform ICs is preferred to limit
rush-in current on Platform.

Wait 10ms

Switch RESET-FUSION-OUTn, RESET-

HDMI-MUXn , RESET-ETHERNETn High

19210_080_120504.eps
120504

Figure 5-5 Off to Semi Stand-by flowchart (part 1)

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 Service Modes, Error Codes, and Fault Finding QFU1.1E LA 5. EN 25

Wake up reason
No
coldboot to Active mode?

No yes

AUDIO-MUTEn is switched by MIPS code No Startup screen cfg file

later on in the startup process when audio present?
needs to be released

Standby P monitors MIPS boots yes

boot process and will
init a restart if Boot
process hampers
Reset-lines are switched MIPS sends out startup screen
Boot is failing

TV application starts MIPS starts up the display.

Set was
started with
SDM pin?
Startup screen visible

Wait 4 seconds before restarting

No

Yes

No Switch AVC in reset

Switch RESET-FUSION-OUTn, RESET-

HDMI-MUXn , RESET-ETHERNETn Low
Semi-Standby
3-th try?Switch Standby I/O line LOW

Yes
Ignore boot failure:
Stall the startup process.
Blink error code
Blink Layer2 error 53.
Layer 1 error 2
Enter protection without
turning off the supplies

Enter protection

19210_081_120504.eps
120504

Figure 5-6 Off to Semi Stand-by flowchart (part 2)

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 EN 26 5. QFU1.1E LA Service Modes, Error Codes, and Fault Finding

Semi Standby
The assumption here is that a fast toggle (<2s) can
Wait until previous on-state is left more than 2
only happen during ON->SEMI ->ON. In these states,
seconds ago. (to prevent LCD display problems)
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STB Y->SEMI->ON cannot be
made in less than 2s, because the standby state will
be maintained for at least 4s. Assert RGB video blanking
and audio mute

Display already on?

(cold boot with splash
screen) Yes
Initialize audio and video
No processing IC's and functions
according needed use case.

Startup display
(see separate tab)

Start POWER-OK line

detection algorithm as defined
in the CHS service.
Wait until valid and stable audio and video, corresponding to the
requested output is delivered
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time

return
Release audio mute

unblank the video

Set the Ambilight functionality according the last status

settings

Display cfg file present

and up to date, according
correct display option?

No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
19210_079_120504.eps
120504

Figure 5-7 Semi Stand-by to Active flowchart

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 Service Modes, Error Codes, and Fault Finding QFU1.1E LA 5. EN 27

Active

Mute all sound outputs according

information in the FMS AUDIO

Wait 100ms

Switch off POK line detection

algorithm (see CHS service)

Switch Off LCD backlight

Mute all video outputs switch off Ambilight (see CHS ambilight)

Shut down the display Wait until Ambilight has faded out:
(see separate sheet) Output power Observer should be zero

Semi Standby
19210_077_120504.eps
120504

Figure 5-8 Active to Semi Stand-by flowchart

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 EN 28 5. QFU1.1E LA Service Modes, Error Codes, and Fault Finding

Semi Stand by

If ambientlight functionality was used in semi-standby

(lampadaire mode), switch off ambient light (see CHS
ambilight)

Delay transition until ramping down of ambient light is *) If this is not performed and the set is
finished. *) switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.

transfer Wake up reasons to the Stand by P.

transfer specific Firmware and Wake up reasons to the

Wifi dongle to allow networked standby

Switch AVC system in reset state

Switch reset-USB, Reset-Ethernet and Reset-DVBs
LOW

Switch RESET-FUSION-OUTn, RESET-HDMI-MUXn ,

RESET-ETHERNETn Low

Wait 10ms

Disable all supply related protections and switch off

the DC/DC converters (ENABLE-3V3n)

Switch OFF all supplies by switching HIGH the

Standby I/O line

Important remarks:
Networked Standby No
release reset audio 10 sec after entering required?
standby to save power

Also here, the standby state has to be Switch ENABLE-WOLAN Low to

maintained for at least 4s before starting power off the Ethernet PHY and
another state transition. Internal Wifi dongle.
Yes

Stand by

19210_078_120504.eps
120504

Figure 5-9 Semi Stand-by to Stand-by flowchart

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 Service Modes, Error Codes, and Fault Finding QFU1.1E LA 5. EN 29

5.4 Service Tools 5.5 Error Codes

5.4.1 ComPair 5.5.1 Introduction

Introduction The error code buffer contains all detected errors since the last
ComPair (Computer Aided Repair) is a Service tool for Philips time the buffer was erased. The buffer is written from left to
Consumer Electronics products and offers the following: right, new errors are logged at the left side, and all other errors
1. ComPair helps to quickly get an understanding on how to shift one position to the right.
repair the chassis in a short and effective way. When an error occurs, it is added to the list of errors, provided
2. ComPair allows very detailed diagnostics and is therefore the list is not full. When an error occurs and the error buffer is
capable of accurately indicating problem areas. No full, then the new error is not added, and the error buffer stays
knowledge on I2C or UART commands is necessary, intact (history is maintained).
because ComPair takes care of this. To prevent that an occasional error stays in the list forever, the
3. ComPair speeds up the repair time since it can error is removed from the list after more than 50 hrs. of
automatically communicate with the chassis (when the P operation.
is working) and all repair information is directly available. When multiple errors occur (errors occurred within a short time
4. ComPair features TV software up possibilities. span), there is a high probability that there is some relation
between them.
Specifications
ComPair consists of a Windows based fault finding program If no errors are there, the LED should not blink at all in
and an interface box between PC and the (defective) product. CSM or SDM. No spacer must be displayed as well.
The ComPair II interface box is connected to the PC via an There is a simple blinking LED procedure for board
USB cable. For the TV chassis, the ComPair interface box and level repair (home repair) so called LAYER 1 errors
the TV communicate via a bi-directional cable via the service next to the existing errors which are LAYER 2 errors (see
connector(s). Table 5-2).
The ComPair fault finding program is able to determine the LAYER 1 errors are one digit errors.
problem of the defective television, by a combination of LAYER 2 errors are 2 digit errors.
automatic diagnostics and an interactive question/answer In protection mode.
procedure. From consumer mode: LAYER 1.
From SDM mode: LAYER 2.
Fatal errors, if I2C bus is blocked and the set reboots,
How to Connect
This is described in the chassis fault finding database in CSM and SAM are not selectable.
From consumer mode: LAYER 1.
ComPair.
From SDM mode: LAYER 2.
In CSM mode.
TO TV
When entering CSM: error LAYER 1 will be displayed
TO
UART SERVICE
TO
I2C SERVICE
TO
UART SERVICE by blinking LED.
CONNECTOR CONNECTOR CONNECTOR
In SDM mode.
When SDM is entered via Remote Control code or the
ComPair II
Multi hardware pins, LAYER 2 is displayed via blinking LED.
RC in function
RC out
Error display on screen.
In CSM no error codes are displayed on screen.
Optional Power Link/ Mode
Switch Activity I2C RS232 /UART
In SAM the complete error list is shown.

Basically there are three kinds of errors:

PC
ComPair II Developed by Philips Brugge
Optional power
HDMI
I2C only
Figure 5-10 ComPair II interface connection
Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs can be
blown!
How to Order
ComPair II order codes:
ComPair II interface: 3122 785 91020.
Software is available via the Philips Service web portal.
ComPair UART interface cable for QF1x.x.
(using 3.5 mm Mini Jack connector): 3138 188 75051.
Note: When you encounter problems, contact your local
support desk.
Errors detected by the Standby software which lead to
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section 5.6 The Blinking LED Procedure).
Errors detected by the Standby software which not
lead to protection. In this case the front LED should blink
the involved error. See also section 5.5 Error Codes, 5.5.4
5V DC Error Buffer. Note that it can take up several minutes
before the TV starts blinking the error (e.g. LAYER 1
error = 2, LAYER 2 error = 15 or 53).
10000_036_090121.eps
091118 Errors detected by main software (MIPS). In this case
the error will be logged into the error buffer and can be read
out via ComPair, via blinking LED method LAYER 1-2
error, or in case picture is visible, via SAM.
5.5.2 How to Read the Error Buffer
Use one of the following methods:
On screen via the SAM (only when a picture is visible).
E.g.:
00 00 00 00 00: No errors detected
23 00 00 00 00: Error code 23 is the last and only
detected error.
37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.
Note that no protection errors can be logged in the
error buffer.
Via the blinking LED procedure. See section 5.5.3 How to
Clear the Error Buffer.

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 EN 30 5. QFU1.1E LA Service Modes, Error Codes, and Fault Finding

Via ComPair. If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
5.5.3 How to Clear the Error Buffer code and not the actual cause.(e.g. a fault in the protection
detection circuitry can also lead to a protection)
There are several mechanisms of error detection:
Use one of the following methods:
By activation of the RESET ERROR BUFFER command Via error bits in the status registers of ICs.
Via polling on I/O pins going to the standby processor.
in the SAM menu.
Via sensing of analog values on the standby processor or
If the content of the error buffer has not changed for 50+
hours, it resets automatically. the Mips.
Via a not acknowledge of an I2C communication.

5.5.4 Error Buffer

Take notice that some errors need several minutes before they
start blinking or before they will be logged. So in case of
In case of non-intermittent faults, clear the error buffer before problems wait 2 minutes from start-up onwards, and then
starting to repair (before clearing the buffer, write down the
check if the front LED is blinking or if an error is logged.
content, as this history can give significant information). This to
ensure that old error codes are no longer present.

Table 5-2 Error code overview

Monitored Error/ Error Buffer/

Description Layer 1 Layer 2 by Prot Blinking LED Device Defective Board
I2CM3 (SSB + SRF bus) 2 13 MIPS E BL / EB SSB SSB
I2CM2 (BE bus) 2 14 MIPS E BL / EB SSB SSB
I2CM1(FE bus) 2 18 MIPS E BL / EB SSB SSB
Fusion doesnt boot (HW cause) 2 15 Stby P P BL Fusion SSB
12V 3 16 Stby P P BL / Supply
Display supply (POK) 3 17 MIPS E EB / Supply
HDMI mux 2 23 MIPS E EB SII9387 SSB
I2C switch 2 24 MIPS E EB PCA9540 SSB
Channel dec DVB-T2 2 27 MIPS E EB CXD2834 SSB
Channel dec DVB-S2 2 28 MIPS E EB STV0903 SSB
Lnb controller 2 31 MIPS E EB LNBH25 SSB
Hybrid Tuner 2 34 MIPS E EB SUT-RE214Z SSB
Main NVM 2 35 MIPS E EB STM24C64 SSB
Tuner DVB-S2 2 36 MIPS E EB STV6110 SSB
Class-D 2 37 MIPS E EB TAS 5731 PHP SSB
FPGAScanBacklight 2 38 MIPS E EB XC6SLX4 SSB
T sensor SSB/Display 2 42 MIPS E EB LM 75 T sensor on SSB/Display
Light sensor 6 43 MIPS E EB TSL2571 Set
P touch control 6 44 MIPS E EB / Set
RF4CE 6 46 MIPS E EB / Set
MIPS doesnt boot (SW cause) 2 53 Stby P P BL FUSION SSB
FPGA HDR 5 61 MIPS E BL Xilinx Spartan Display
FPGA Lattice Backlight 5 62 MIPS E BL Lattice Display
TCON P (SHARP) 7 54 MIPS E BL / Display
TCON ASIC (SHARP) 7 55 MIPS E BL / Display
VCON cal (SHARP) 7 56 MIPS E BL / Display

Extra Info
Rebooting. When a TV is constantly rebooting due to
internal problems, most of the time no errors will be logged
or blinked. This rebooting can be recognized via a ComPair
interface and Hyperterminal (for Hyperterminal settings,
see section 5.8 Fault Finding and Repair Tips, 5.8.6
Logging). Its shown that the loggings which are generated
by the main software keep continuing.
Error 13 (I2C bus M3, SSB + SRF bus blocked). Current
situation: when this error occurs, the TV can reboot due to
the blocked bus. The best way for further diagnosis here, is
to check the logging output.
Error 14 (I2C bus M2, BE bus blocked). Current situation:
when this error occurs. The best way for further diagnosis
here, is to check the logging output.
Error 18 (I2C bus M1, FE bus blocked). Current situation:
when this error occurs. The best way for further diagnosis
here, is to check the logging output.
Error 15 (Fusion doesnt boot). Indicates that the main
processor was not able to read his bootscript. This error will
point to a hardware problem around the Fusion (supplies
not OK, Fusion device completely dead, link between Mips
and Stand-by Processor broken, etc...)
Other root causes for this error can be due to hardware
problems regarding the DDRs and the bootscript reading
from the Fusion device.
Error 16 (12V). This voltage is made in the power supply
and results in protection (LAYER 1 error = 3) in case of
absence. When SDM (maintain grounding continuously) is
activated we see blinking LED LAYER 2 error = 16.
Error 17 (Display Supply). Here the status of the Power
OK is checked by software, no protection will occur during
failure of the display supply, only error logging. LED
blinking of LAYER 1 error = 3 in CSM, in SDM this gives
LAYER 2 error = 17.
Error 23 (HDMI mux). When there is no I2C
communication towards the HDMI mux after start-up,
LAYER 2 error = 23 will be logged and displayed via the
blinking LED procedure if SDM is switched on.
Error 24 (I2C switch). When there is no I2C
communication towards the I2C switch, LAYER 2
error = 24 will be logged and displayed via the blinking LED
procedure when SDM is switched on.
Error 27 (Channel dec DVB-T2). When there is no I2C
communication towards the DVB-T channel decoder,
LAYER 2 error = 27 will be logged and displayed via the
blinking LED procedure if SDM is switched on.
Error 28 (Channel dec DVB-S2). When there is no I2C
communication towards the DVB-S channel decoder,
LAYER 2 error = 28 will be logged and displayed via the
blinking LED procedure if SDM is switched on.

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 Service Modes, Error Codes, and Fault Finding
Error 31 (Lnb controller). When there is no I2C
communication towards this device, LAYER 2 error = 31
will be logged and displayed via the blinking LED
procedure if SDM is activated.
Error 34 (Tuner). When there is no I2C communication
towards the tuner during start-up, LAYER 2 error = 34 will
be logged and displayed via the blinking LED procedure
when SDM is switched on.
Error 35 (main NVM). When there is no I2C
communication towards the main NVM during start-up,
LAYER 2 error = 35 will be displayed via the blinking LED
procedure when SDM is switched on. All service modes
(CSM, SAM and SDM) are accessible during this failure,
observed in the Uart logging as follows: "<< ERRO >>>
PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)".
Error 36 (Tuner DVB-S). When there is no I2C
communication towards the DVB-S tuner during start-up,
LAYER 2 error = 36 will be logged and displayed via the
blinking LED procedure when SDM is switched on.
Error 37 (Class-D). When there is no I2C communication
towards the Class-D amplifier during start-up, LAYER 2
error = 37 will be logged and displayed via the blinking LED
procedure when SDM is switched on.
Error 38 (FPGA ScanBacklight). When there is no I2C
communication towards this FPGA device during start-up,
LAYER 2 error = 38 will be logged and displayed via the
blinking LED procedure when SDM is switched on. This
device supports the backlight + boost pwm control,
scanning, 3D drive and ambilight buffering.
Error 42 (Temp sensor). Only applicable for TV sets
equipped/stuffed with temperature devices.
Error 43 (Light sensor). When there is no I2C
communication towards the light sensor device during
start-up, LAYER 2 error = 43 will be logged and displayed
via the blinking LED procedure when SDM is switched on.
Error 44 (Touch control). When there is no I2C
communication towards the touch control micro processor
during start-up, LAYER 2 error = 44 will be logged and
displayed via the blinking LED procedure when SDM is
switched on.
Error 46 (RF4CE). When there is no I2C communication
towards the RF4CE driver during start-up, LAYER 2
error = 46 will be logged and displayed via the blinking LED
procedure when SDM is switched on.
Error 53. This error will indicate that the Fusion device has
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because
of hardware problems (NAND flash, DDR...) or software
initialization problems. Possible cause could be that there
is no valid software loaded (try to upgrade to the latest main
software version). Note that it can take a few minutes
before the TV starts blinking LAYER 1 error = 2 or in SDM
(maintain grounding continuously), LAYER 2 error = 53.
5.6 The Blinking LED Procedure
5.6.1 Introduction
The blinking LED procedure can be split up into two situations:
Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
This will be only one digit error, namely the one that is
referring to the defective board (see table 5-2 Error code
overview) which causes the failure of the TV. This
approach will especially be used for home repair and call
centres. The aim here is to have service diagnosis from a
distance.
Blinking LED procedure LAYER 2 error. Via this
procedure, the contents of the error buffer can be made
visible via the front LED. In this case the error contains
2 digits (see table 5-2 Error code overview) and will be
displayed when SDM (hardware pins) is activated. This is
especially useful for fault finding and gives more details
regarding the root cause of the defective board.
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QFU1.1E LA 5. EN 31
Important remark:
For an empty error buffer, the LED should not blink at all in
CSM or SDM. No spacer will be displayed.
When one of the blinking LED procedures is activated, the front
LED will show (blink) the contents of the error buffer. Error
codes greater then 10 are shown as follows:
1. n long blinks (where n = 1 to 9) indicating decimal digit
2. A pause of 1.5 s
3. n short blinks (where n= 1 to 9)
4. A pause of approximately 3 s,
5. When all the error codes are displayed, the sequence
finishes with a LED blink of 3 s (spacer).
6. The sequence starts again.
Example: Error 12 8 6 0 0.
After activation of the SDM, the front LED will show:
1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s
2. Two short blinks of 250 ms followed by a pause of 3 s
3. Eight short blinks followed by a pause of 3 s
4. Six short blinks followed by a pause of 3 s
5. One long blink of 3 s to finish the sequence (spacer).
6. The sequence starts again.
5.6.2 How to Activate
Use one of the following methods:
Activate the CSM. The blinking front LED will show the
layer 1 error(s), this works in normal operation mode or
automatically when the error/protection is monitored by the
Standby processor.
In case no picture is shown and there is no LED blinking,
read the logging to detect whether error devices are
mentioned. (see section 5.8 Fault Finding and Repair
Tips, 5.8.6 Logging).
Activate the SDM. The blinking front LED will show the
entire content of the LAYER 2 error buffer, this works in
normal operation mode or when SDM (via hardware pins)
is activated when the tv set is in protection.
5.7 Protections
5.7.1 Software Protections
Most of the protections and errors use either the standby
microprocessor or the MIPS controller as detection device.
Since in these cases, checking of observers, polling of ADCs,
and filtering of input values are all heavily software based,
these protections are referred to as software protections.
There are several types of software related protections, solving
a variety of fault conditions:
Related to supplies: presence of the +5V, +3V3 and 1V2
needs to be measured, no protection triggered here.
Protections related to breakdown of the safety check
mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
guaranteed any more.
Remark on the Supply Errors
The detection of a supply dip or supply loss during the normal
playing of the set does not lead to a protection, but to a cold
reboot of the set. If the supply is still missing after the reboot,
the TV will go to protection.
Protections during Start-up
During TV start-up, some voltages and IC observers are
actively monitored to be able to optimize the start-up speed,
and to assure good operation of all components. If these
monitors do not respond in a defined way, this indicates a
malfunction of the system and leads to a protection. As the
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 EN 32 5. QFU1.1E LA Service Modes, Error Codes, and Fault Finding
observers are only used during start-up, they are described in
the start-up flow in detail (see section 5.3 Start-up).
5.8 Fault Finding and Repair Tips
Read also section 5.5 Error Codes, 5.5.4 Error Buffer, Extra
Info.
5.8.1 Ambilight
Due to the aging process on the LEDs fitted on the Ambilight
module, there can be a difference in the colour and/or light
output of the spare ambilight modules in comparison with the
originals ones contained in the TV set. Via SAM => alignments
=> ambilight, the spare module can be fine-tuned.
Other possibility: the original values can also be recovered via
SAM, Upload to USB => alignments. Now the original settings
are on the USB stick and can be reloaded into another SSB
(NVM).
5.8.2 CSM
When CSM is activated and there is a USB stick connected to
the TV, the software will dump the complete CSM content to the
USB stick. The file (Csm.txt) will be saved in the root of the USB
stick. If this mechanism works it can be concluded that a large
part of the operating system is already working (MIPS, USB...)
5.8.3 DC/DC Converter
Description
Input power for the TV platform comes from the main power
supply that delivers +3V3STANDBY (pin 1 of connector 1M95)
and +12V (pins 5,6 of the same connector). +3V3STANDBY
(3.3V nominal) is the permanent voltage, supplying the standby
microprocessor inside the Fusion chip while +12V is started by
the STANDBY signal (connector 1M95, pin 2) when going from
high to low. +12V is split in three branches via fuses 1UA0
(+12Va), 1UA1 (+12Vb) and 1UP1(+12-DVBS):
+12Va serves as input voltage for the switching voltage
regulators that deliver +1V1-FD and +1V5.
+12Vb is used as input voltage for the switching voltage
regulators that deliver +3V3 and +5V.
+12V-DVBS (if DVB-S functionality is present) goes to 12V
to +1V0-DVBS and 12V to +V-LNB switching regulators.
The on board power supply consists of 4 switching voltage
regulators (6 in case of DVB-S version), 6 linear voltage
regulators (7 in case of DVB-S version) one power switch
delivering +3V3AL for Ambilight driver boards and an over-
current protection for 12V (AMBI-POWER) Ambilight boards.
All switching voltage regulators have 12V input voltage and
deliver:
+1V0-DVBS core supply voltage for DVB-S2 demodulator
(1.02V nominal), stabilized close to the point of load by
means of SENSE+1V0-DVBS signal.
+1V1-FD Fusion main core supply voltage (0.95V...1.2V -
depending on DVS1 signal), stabilized close to the point of
load by means of SENSE+1V1-FD signal.
+1V5 supply voltage (1.53V nominal), for the DDR3
memories and DDR3 interface of the Fusion chip.
+3V3 supply voltage (3.37V nominal): overall 3.3V for on
board ICs and for WiFi module, also used as input voltage
for linear voltage regulators delivering +1V1-FA, +1V2-FA
and +2V5.
+5V (5.15V nominal) for USB, WiFi, Conditional Access
Module and via linear voltage regulators, the DVB-T and
DVB-S tuner supplies.
+V-LNB (13V or 18V) supply for outdoor satellite reception
equipment.
The linear voltage regulators are providing:
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+1V1-FA supply voltage (1.10V nominal, from +3V3) for
low power analog (PLL) blocks inside Fusion chip.
+1V2-MIPS supply voltage (1.05...1.3V depending on
DVS2 signal, input voltage: +1V5) for Fusion auxiliary core.
+1V2-FE supply voltage (1.20V nominal, from +1V5) for
HDMI multiplexer and (if present) DVB-T2 demodulator IC
device.
+1V2-FA supply voltage (1.20V nominal, from +3V3) for
higher power analog Fusion internal blocks (mainly video
ADCs).
+2V5 supply voltage (2.5V nominal, from +3V3) for LVDS
(or Vby1) interface and various other internal blocks of
Fusion.
+3V3 supply voltages (3.3V nominal, from +5V) for RF
tuners, separate linear regulator per tuner.
Supply voltages +1V1-FD, +1V5 and +1V2-MIPS are started
immediately when +12V rises above the 5V level. The rest of
the supply voltages (+5V, +3V3, +2V5, +1V2-FA and +1V1-FA
are turned on by signal DETECT12V when becomes high. The
tuners are supplied from their respective linear voltage
regulators when +5V starts.+1V0-DVBS is started almost at the
same time, when +2V5-DVBS (derived from +3V3-DVBS via
the equivalent diode 7RC2) rises.
DETECT12V becomes high when +12V rises above 10V and
stays above 9.5V (0.5V hysteresis).
+3V3AL will become available when enabled via software
(signal ENABLE-3V3-AMBI high).In case of TV sets having
Ambilight consumption from 12V + higher than 1A, the
electronic protection circuit (7UAC and surrounding
components) is used instead of fuse 1UA2. AMBI-POWER
should be available shortly (100 ms) after +12V starts if there
is no load on it. The over-current trigger level is around 4.1A.
Once triggered, it can be reset by removing the shortcircuit
cause and keeping it under no load condition for about 100 ms.
+V-LNB value is determined via software: around 13V for
vertical polarized satellite channels and around 18V for the
horizontal ones. Maximum current is limited in both cases to
400mA
Debugging
The best way to find a failure in the DC/DC converters is to
check their start-up sequence at power on, presuming that
the external supply is operational. Take the STANDBY signal
"high"-to-"low" transition as trigger reference and check the
power start-up sequence as described above.
Tips
Behaviour comparison with a working Fusion platform can
be a fast way to locate failures.
Check first the integrity of fuses 1UA0, 1UA1 and (if
present) 1UA2 and 1UP1.
If a fuse is found interrupted: check the respective +12Va
(or +12Vb or +12V-DVBS) short circuit with all of the
derived supply voltages, for example: a +12Va ->+1V5
short circuit will probably be caused by a defective 7UB5
integrated circuit.
Switching frequency should be around 400KHz for 12V to
+V-LNB switching voltage regulator, 500KHz for +12V to
+1V1-FD and 600KHz...700KHz for the others.
When a short circuit to GND is found on one of the supply
voltage delivered by a switching voltage regulator, then try
first removing the power coil(s) from the output filter of the
converter, this to point the location of the short circuit (at
converter side or at load side).
5.8.4 Power Supply Unit
For fault finding tips, refer to section 7.2.1.
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 Service Modes, Error Codes, and Fault Finding QFU1.1E LA 5. EN 33

5.8.5 Exit Factory Mode
To exit this mode, push the VOLUME minus button on the
TVs local keyboard for 10 seconds (this disables the
continuous mode).
Then push the SOURCE button for 10 seconds until to exit the
Factory mode.
5.8.6 Logging
When something is wrong with the TV set (f.i. the set is
rebooting) you can check for more information via the logging
in Hyperterminal. The Hyperterminal is available in every
Windows application via Programs, Accessories,
Communications, Hyperterminal. Connect a ComPair UART-
cable (3138 188 75051) from the service connector in the TV to
the multi function jack at the front of ComPair II box.
Required settings in ComPair before starting to log:
- Start up the ComPair application.
- Select the correct database (open file QFU1X.X, this will set
the ComPair interface in the appropriate mode).
- Close ComPair
After start-up of the Hyperterminal, fill in a name (f.i. logging)
in the Connection Description box, then apply the following
settings:
1. COMx
2. Bits per second = 115200
3. Data bits = 8
4. Parity = none
5. Stop bits = 1
6. Flow control = none
During the start-up of the TV set, the logging will be displayed.
This is also the case during rebooting of the TV set (the same
logging appears time after time). Also available in the logging
is the Display Option Code (useful when there is no picture),
look for item display number xxx in the beginning of the
logging. Tip: when there is no picture available during rebooting
you are able to check for error devices in the logging (LAYER
2 error) which can be very helpful to determine the failure cause
of the reboot. For protection state, there is no logging.
5.8.7 Guidelines Uart logging
Description possible cases:
In the Uart log startup script we can observe and check the
enabled loaded option codes.
Defective sectors (bad blocks) in the Nand Flash can also be
reported in the logging.
Startup in the SW upgrade application and observe the Uart
logging:
Starting up the TV set in the Manual Software Upgrade mode
will show access to USB, meant to copy software content from
USB to the DRAM. Progress feedback can be found in the
logging.
Startup in Jett Mode:
Check Uart logging in Jet mode mentioned as : JETT UART
READY.
5.8.8 Loudspeakers
Make sure that the volume is set to minimum during
disconnecting the speakers in the ON-state of the TV. The
audio amplifier can be damaged by disconnecting the speakers
during ON-state of the set!
5.8.9 Power Supply
In case of no picture when CSM (test pattern) is activated and
backlight doesnt light up, its recommended first to check the
LED drivers on the PSL(S) + wiring (LAYER 2 error = 17 is
displayed in SDM).
5.8.10 Display option code
Attention: In case the SSB is replaced, always check the
display option code number (group 2, first option number e.g.
44855) in SAM, even when picture is available. Performance
with the incorrect display option code can lead to unwanted
side-effects for certain conditions.
Also supported in this chassis:
While in the download application (start up in TV mode + OK
button pressed), the display option code can be changed via
062598 HOME XXX special SAM command (XXX=display
option in 3 digits).

Uart loggings are displayed:

When Uart loggings are coming out, the first conclusion we
can make is that the TV set is starting up and
communication with the flash RAM seems to be supported.
The Fusion processor is able to read and write in the
DRAMs.
We can not yet conclude: Flash RAM and DRAMs are fully
operational/reliable.There still can be errors in the data
transfers, DRAM errors, read/write speed and timing
control.

No Uart logging at all:

No startup will end up in a blinking LED status: error
LAYER 1 = 2, error LAYER 2 = 53 (startup with SDM
solder paths continuous short).
Error LAYER 2 = 15 (hardware cause) is more related to
a supply issue while error LAYER 2 = 53 (software cause)
refers more to boot issues.

Uart loggings reporting fault conditions, error messages, error

codes, fatal errors:
Some failures are indicated by error codes in the logging,
check with error codes table (see Table 5-2 Error code
overview). e.g. => <<<ERROR>>>PLFPOW_MERR.C :
First Error (id=10,Layer_1=2,Layer_2=23).
I2C bus errors.
Not all failures or error messages should be interpreted as
fault. For instance root cause can be due to wrong option
codes settings => e.g. FpgaDimmingPresent: False/True.

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 EN 34 5. QFU1.1E LA Service Modes, Error Codes, and Fault Finding

5.8.11 SSB Replacement For a more general overview of steps to follow, refer to figure
5-13 SSB replacement flowchart.
Follow the instructions in the flowchart in case a SSB has to be
exchanged. See table 5-3 SSB replacement instructions. Table 5-3 SSB replacement instructions

Step # Action to do Advise / Attention points / Remarks

1 Ensure ESD protection by using a wristband -
2 If SSB is still functional: Go via SAM to upload to USB and copy Personal Upload to USB: A directory repair will be created on the USB, and all data will be copied in this
settings - Option codes - Alignments (Presets) - Set Identification. directory. On sets with software before Q552-xx-140-x-x, there was an issue by copying the
Advice: because of differences in memory allocation, it is advised to upgrade program map table, so it is advised to reinstall the programs from Virgin mode instead of using
main SW before copying data from existing SSB. Copy of Preset list is copy via USB.
possible from normal user interface.
3 Disconnect set from mains and from antenna. Safety and ESD!
4 Open the set and disconnect LVDS flat cable. Disconnect other cables / Always take care for ESD! Be extra careful when removing connectors!
connections.
5 Dismount the (defective) SSB from the set. Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very careful
by moving SSB over SSB supports). See Figure 5-11 and Figure 5-12.
6 Place new SSB in the set, and fixate/mount carefully. Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very careful
by moving SSB over SSB supports). See Figure 5-11 and Figure 5-12.
7 Connect PSU and other connectors. Insert the optional WiFi module. Make sure that the connectors are correctly plugged-in and locked (click). Special attention for the
optional WiFi module: a defective WiFi module can give reboots or no start-up of the SSB. In this
case do a trial without WiFi module.
8 Connect LVDS connector(s). Be very careful: wrong or bad connection can damage the TCON part on the SSB and damage
the LCD display. Check if flat cables are fitted correctly before closing the connector lock.
9 Connect set to mains and switch TV On. Check start-up of the set, backlight switching On.
10 If the set does not start (or reboots) check: Power supply connector must snap into the socket.
- The connectors from the power supply,
- The power supply cable and connection pins,
- LVDS cable connection.
11 Before programming the new SSB, upgrade to latest software. If set is starting Some SSBs will start-up in software upgrade mode, and software needs to be installed before you
up in software upgrade mode, then first install new software via software can program the Display Option codes. Its adviced to use an autorun.upg file for software
Upgrade Menu or via the autorun.upg file. upgrade, this in case you have no OSD on the screen.
12 If set is starting up without picture or menu (OSD), first program the correct Use blind service mode 062598 + Home button, directly followed by the
Display Option codes. Display Option code (3 digits). Set will switch to Standby after Display Option code is entered.
13 Go to SAM and program Set type and Serial number. This is possible via Programming Set type and Serial number is mandatory to have all functionality of the set, like
the NVM editor and virtual keyboard. In case personal settings were DLNA, Net TV For certain sets you may need to use ComPair for this.
recovered from the defective SSB, you can use an Upload from USB.
14 Check if option codes are correct, and keys are present. SSBs with integrated Validity of HDCP, CI+, Marlin, and WDRM keys can be checked via ComPair.
TCON needs TCON alignment in SAM.
15 Update to latest software (Standby and main software). This step is necessary Even when the SSB already has the latest software, it is mandatory to upgrade again the software
to make sure that the (optional) 200 Hz T-CON board has the latest software. to update the 200 Hz T-CON part. At the end of the main software update process, a dedicated
software is loaded, from the main processor via the LVDS connection, to upgrade the
200 Hz T-CON part. For certain LCD displays, a dedicated Display software patch (autoscript) is
available. See General Service info GSC_85590.
16 Once the set is playing, check cable connection between PSU and SSB, by Check the two power connectors 1M95 and 1M99. Bad contact or bad connection here can give
moving the cable if there are no bad connections. reboots.
17 Fill in the Electronic DDF (Defect Description Form): Fault symptom, TV type It is mandatory to fill in the E-DDF form (see the At Your Service web portal).
and TV serial number.
18 Install presets or check if all presets are OK. Check in CSM if Type number, Special attention for Standby software: check if Standby software ID is matching with the D-RAMs
Serial number, Main and Standby software are correct. mounted on the SSB (2 Elpida = 73, 4 Elpida = 64, 2 Hynix = 72, 4 Hynix = 63).
19 Check connectivity to Net TV and DLNA. Check AmbiLight functionality. Only for sets having these functionalities.
20 Inform customer about Memory Card, USB, or Hard drive PVR (Personal Inform customer that previous recordings made on Memory Card (movie download), USB, or Hard
Video Recording) recordings. drive will be lost. USB or Hard drive needs to be re-formatted and matched with new SSB (WDRM
Keys!).

SSB fixation points

Significant risk of damaging the board

by the fixation point

Blue arrows: traces of friction

Red arrows: damaged components

19070_201_110728.eps 19070_202_110728.eps
110804 110804

Figure 5-11 Mounting attention points [1/2] Figure 5-12 Mounting attention points [2/2]

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 Service Modes, Error Codes, and Fault Finding QFU1.1E LA 5. EN 35

In st ru ct io n n o t e SSB rep lacem en t Q55x.x

Before starting: ST AR T
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder upgrades in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in Set is still oper ating?
case there are more than one "autorun.upg" files on the USB stick.
No

Yes

C onnect the U SB stick to the set,

go to SAM and save the current TV settings via Upload to USB

1. D ismount the defective SSB.

2. Replace the SSB by a Service SSB.

Start-up the set

Due to a possible wrong display option code in the received Service
SSB (NVM), its possible that no picture is displayed. Due to this
the download application will not be shown either. This tree enables you
to load the main software step-by-step via the UART logging on the PC
(this for visual feedback). Set behaviour?
No pictur e displayed Pictur e displayed
Set is starting up without software
upgrade menu appearing on screen

1) Start up the TV set, equiped with the Service SSB,

and enable the UART logging on the PC. Pictur e displayed
Set is starting up with software
upgrade menu appearing on screen
2) The TV set will start-up automatically in the
download application if main TV software is not loaded.

1) Plug the USB stick into the TV set and select

3) Plug the prepared USB stick into the TV set. Follow the the autorun .upg file in the displayed browser.
instructions in the UART log file, press Right cursor key to enter
the list. Navigate to the autorun.upg file in the UART logging
printout via the cursor keys on the remote control. When the
correct file is selected, press Ok.
2) Now the main software will be loaded automatically,
supported by a progress bar.
4) Press "Down" cursor and Ok to start flashing the main
TV software. Printouts like: L: 1-100%, V: 1-100% and
P: 1-100% should be visible now in the UART logging.

3) Wait until the message Operation successful ! is displayed

5) Wait until the message Operation successful ! is logged in and remove all inserted media. Restart the TV set.
the UART log and remove all inserted media. Restart the TV set.

Set the correct Display code via 062598 -HOME- xxx where
xxx is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)

After entering the Display Option code, the set is going to

Standby
(= validation of code)

Restart the set

No

Connect PC via the ComPair interface to Service connector.

Saved settings
on USB stick?

Start TV in Jett mode (DVD I + (OSD)) Yes

Open ComPair browser Q54x
In case of settings reloaded from USB, the set type,
Go to SAM and reload settings serial number, display 12 NC, are automatically stored
via Download from USB function. when entering display options.
Program set type number, serial number, and display 12 NC
Program E - DFU if needed.

If not already done:

Check latest software on Service website. - Check if correct display option code is programmed.
Update main and Stand-by software via USB. - Verify option codes according to sticker inside the set.
- Default settings for white drive > see Service Manual.
Attention point for Net TV: If the set type and serial number are not
filled in, the Net TV functionality will not work. It will not be possible
to connect to the internet.
Check and perform alignments in SAM according to the
Service Manual. Option codes, colour temperature, etc.

Final check of all menus in CSM.

Special attention for HDMI Keys and Mac address.
Check if E - D F U is present.

End Q55x.E SSB Board swap ER on behalf of VDS

Updated 28-07-2011

19070_200_110728.eps
111103

Figure 5-13 SSB replacement flowchart

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 EN 36 5. QFU1.1E LA Service Modes, Error Codes, and Fault Finding

Set is st art in g u p in F act o ry m o d e

Set is starting up in F actory m ode?

Noisy picture with bands/lines is visible and the An F is displayed (and the HDMI 1
RED LED is continuous on. input is displayed).

- Press the volume minus button on the TVs local keyboard for 5 ~10
seconds

- Press the SOURCE button for 10 seconds until the F disappears

from the screen or the noise on the screen is replaced by blue mute

The noise on the screen is replaced

with the blue mute or the F is disappeared!

Unplug the mains cord to verify the correct

disabling of the Factory mode.

Program display option code

via 062598 MENU, followed by
the 3 digits code of the display
(this code can be found
on a sticker on - or inside - the set).

After entering display option code, the set is

going in stand-by mode (= validation of code)

R estart the set

H_16771_007b.eps
100322

Figure 5-14 SSB replacement flowchart - Factory mode

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 Service Modes, Error Codes, and Fault Finding
Figure 5-15 SSB start-up
5.9 Software Upgrading
Always check for the latest software version on the service
website in relation to the correct CTN!!!
5.9.1 Introduction
The set software and security keys are stored in a NAND-
Flash, which is connected to the Fusion processor.
It is possible for the user to upgrade the main software via the
USB port. This allows replacement of a software image in a
stand alone set, without the need of an E-JTAG debugger. A
description on how to upgrade the main software can be found
in the electronic User Manual.
Important: When the NAND-Flash must be replaced, a new
SSB must be ordered, due to the presence of the security keys!
(CI +, MAC address, ...).
Perform the following actions after SSB replacement:
1. Set the correct option numbers (see rearcover sticker).
2. Update the TV software => see the eUM (electronic User
Manual) for instructions.
3. Perform the alignments as described in chapter 6 (section
6.5 Reset of Repaired SSB).
4. Check in CSM if Set type, MAC address are valid.
For the correct order number of a new SSB, always refer to the
Spare Parts list!
5.9.2 Main Software Upgrade
The UpgradeAll.upg file is only used in the factory.
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QFU1.1E LA 5. EN 37
18753_211_100811.eps
110810
Automatic Software Upgrade
In normal conditions, so when there is no major problem with
the TV, the main software and the default software upgrade
application can be upgraded with the AUTORUN.UPG
(FUS part of the one-zip file: e.g. QF1EU_0.88.0.0.zip). This
can also be done by the consumers themselves, but they will
have to get their software from the commercial Philips website
or via the Software Update Assistant in the user menu (see
eUM). The autorun.upg file must be placed in the root of the
USB stick.
How to upgrade:
1. Copy AUTORUN.UPG to the root of the USB stick.
2. Insert USB stick in the set while the set is operational. The
set will restart and the upgrading will start automatically. As
soon as the programming is finished, a message is shown
to remove the USB stick and restart the set.
Manual Software Upgrade
In case that the software upgrade application does not start
automatically, it can also be started manually.
How to start the software upgrade application manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the OK button on a Philips TV remote control or a
Philips DVD RC-6 remote control (attention : not supported
by use of RF4CE remote due to the fact this application is
not running yet at the time of the OK request). Keep the
OK button pressed while reconnecting the TV to the
Mains/AC Power.
3. The software upgrade application will start.
Attention!
In case the download application has been started manually,
the autorun.upg will maybe not be recognized.
2012-Sep-14
 EN 38 5. QFU1.1E LA Service Modes, Error Codes, and Fault Finding

What to do in this case:

1. Create a directory UPGRADES on the USB stick.
2. Rename the autorun.upg to something else, e.g. to
software.upg. Do not use long or complicated names,
keep it simple. Make sure that AUTORUN.UPG is no
longer present in the root of the USB stick.
3. Copy the renamed upg file into this directory.
4. Insert USB stick into the TV.
5. The renamed upg file will be visible and selectable in the
upgrade application.

Back-up Software Upgrade Application

If the default software upgrade application does not start (could
be due to a corrupted boot sector) via the above described
method, try activating the back-up software upgrade
application.
How to start the back-up software upgrade application
manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the CURSOR DOWN-button on a Philips TV
remote control while reconnecting the TV to the Mains/AC
Power.(attention : not supported by use of RF4CE remote
due to the fact this application is not running yet at the time
of the CURSOR-DOWN request).
3. The back-up software upgrade application will start.

5.9.3 Standby Software Upgrade via USB

In this chassis it is possible to upgrade the Standby software

via a USB stick. The method is similar as upgrading the main
software via USB.
Use the following steps:
1. Create a directory UPGRADES on the USB stick.
2. Copy the Standby software (one-zip file StandbyUpgrade,
e.g. StandbyFactory_61.0.0.00_13.00.00.upg) into this
directory.
3. Insert the USB stick into the TV.
4. Start the download application manually (see section
Manual Software Upgrade.
5. Select the appropriate file and press the OK button to
upgrade.

5.9.4 Content and Usage of the One-Zip Software File

Below the content of the One-Zip file is explained, and

instructions on how and when to use it.
BLCtrlFPGA_QF1EU_x.x.x.x.zip. Contains the
BLCtrlFPGA software in upg format.SW version available
in CSM 2.5 FPGA video version.Attention : no power
interruption allowed during the upgrade process (upgrade
not full proof).
FUS_QF1EU_x.x.x.x.zip. Contains the autorun.upg
which is needed to upgrade the TV main software and the
software download application.
StandbyUpgrade_QF1EU_x.x.x.x.zip. Contains the
StandbyFactory software in upg format.
ProcessNVM_QF1EU_x.x.x.x.zip. Default NVM content.
Must be programmed via ComPair or can be loaded via
USB, be aware that all alignments stored in NVM are
overwritten here.

5.9.5 UART logging 2K12 (see section 5.8 Fault Finding and
Repair Tips, 5.8.6 Logging)

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 Alignments QFU1.1E LA 6. EN 39

6. Alignments
Index of this chapter: LATAM models: an NTSC M TV-signal with a signal
6.1 General Alignment Conditions strength of at least 1 mV and a frequency of 61.25 MHz
6.2 Hardware Alignments (channel 3).
6.3 Software Alignments
6.4 Option Settings 6.3.1 White Point
6.5 Reset of Repaired SSB
6.6 Total Overview SAM modes
Choose Home, Setup, TV Settings and then Picture
and set picture settings as follows:
6.1 General Alignment Conditions Picture Setting
Perform all electrical adjustments under the following
Contrast 100
conditions:
Brightness 50
Power supply voltage (depends on region):
Colour 0
AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%).
Light Sensor Off
AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%).
Picture format Unscaled
EU: 230 VAC / 50 Hz ( 10%).
LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%).
In menu Picture, choose Pixel Precise HD and set
US: 120 VAC / 60 Hz ( 10%).
picture settings as follows:
Connect the set to the mains via an isolation transformer
with low internal resistance. Picture Setting

Allow the set to warm up for approximately 15 minutes. Dynamic Contrast Off

Measure voltages and waveforms in relation to correct Dynamic Backlight Off

ground (e.g. measure audio signals in relation to Colour Enhancement Off

AUDIO_GND). Caution: It is not allowed to use heat sinks Gamma (advanced) 0

as ground.
Test probe: Ri > 10 M, Ci < 20 pF. Go to the SAM and select Alignments-> White point.
Use an isolated trimmer/screwdriver to perform
alignments. White point alignment LCD screens:
Use a 100% white screen (format: 720p50) to the HDMI
6.1.1 Alignment Sequence input and set the following values:
Colour temperature: Cool.
All White point values to: 127.
First, set the correct options:
In SAM, select Option numbers.
In case you have a colour analyser:
Fill in the option settings for Group 1 and Group 2
Measure, in a dark environment, with a calibrated
according to the set sticker (see also paragraph 6.4
contactless colour analyser (Minolta CA-210 or Minolta
Option Settings).
CS-200) in the centre of the screen and note the x, y value.
Press OK on the remote control before the cursor is
Change the pattern to 90% white screen. If a Quantum
moved to the left.
Data generator is used, select the GreyAll test pattern at
In submenu Option numbers select Store and press
level = 230.
OK on the RC.
Adjust the correct x, y coordinates (while holding one of the
OR:
White point registers R, G or B on 127) by means of
In main menu, select Store again and press OK on
decreasing the value of one or two other white points to the
the RC.
correct x, y coordinates (see Table 6-1 White D alignment
Switch the set to Stand-by.
values - LED - Minolta CA-210, or 6-2 White D alignment
Warming up (>15 minutes).
values - LED - Minolta CS-200). Tolerance: dx: 0.002, dy:
0.002.
6.2 Hardware Alignments Repeat this step for the other colour temperatures that
Not applicable. need to be aligned.
When finished press OK on the RC and then press STORE
6.3 Software Alignments (in the SAM root menu) to store the aligned values to the
Put the set in SAM mode (see Chapter 5. Service Modes, Error NVM.
Codes, and Fault Finding). The SAM menu will now appear on Restore the initial picture settings after the alignments.
the screen. Select ALIGNMENTS and go to one of the sub
menus. The alignments are explained below. Table 6-1 White D alignment values - LED - Minolta CA-210
The following items can be aligned:
White point Value Cool (9800K) Normal (8250K) Warm (6190K)
Ambilight. x tbd tbd tbd
TCON alignment : not applicable y tbd tbd tbd
Reset TCON alignment : not applicable

To store the data: Table 6-2 White D alignment values - LED - Minolta CS-200
Press OK on the RC before the cursor is moved to the
left Value Cool (11000K) Normal (9000K) Warm (6500K)
In main menu select Store and press OK on the RC x tbd tbd tbd
Switch the set to stand-by mode. y tbd tbd tbd

For the next alignments, supply the following test signals via a
If you do not have a colour analyser, you can use the default
video generator to the RF input:
values. This is the next best solution. The default values are
EU/AP-PAL models: a PAL B/G TV-signal with a signal average values coming from production.
strength of at least 1 mV and a frequency of 475.25 MHz
Select a COLOUR TEMPERATURE (e.g. COOL,
US/AP-NTSC models: an NTSC M/N TV-signal with a
NORMAL, or WARM).
signal strength of at least 1 mV and a frequency of 61.25 Set the RED, GREEN and BLUE default values according
MHz (channel 3).
to the values in Table 6-3.
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 EN 40 6. QFU1.1E LA Alignments

When finished press OK on the RC, then press STORE (in 4. Select the number of the module that have to be aligned.
the SAM root menu) to store the aligned values to the NVM. Module 1 is the first one which will come across according
Restore the initial picture settings after the alignments. the wiring path, starting at the small signal panel,
proceeding towards the ambient light modules one by one
Table 6-3 White tone default settings 40" after the other. The first module will be attached to the next
module 2. Module number 2 to number 3 etc. Herewith the
White Tone e.g. 40PFLx007/x
way to define the ambilight module numbering.
Colour Temp R G B
5. Align the brightness, use as reference the neighbouring
Normal 127 99 95
modules output. Adjust now by eye side, the brightness is
Cool 127 107 115
automatically stored.
Warm 127 90 58
6. Select one of 10 matrixes which color matches most with
the neighbouring modules. (see table 6-10 Overview
matrix correction table).
Table 6-4 White tone default settings 42" 7. The alignment is stored automatically (tip: dont switch off
the set immediately after the alignment is done, automatic
White Tone 42PFL6907 storage can require a time frame of 10 seconds).
Colour Temp R G B
Normal 123 125 101 Table 6-10 Overview matrix correction table
Cool 115 124 118
Warm 127 116 58
Matrix # fR fG fB
Matrix 0 1 1 1
Table 6-5 White tone default settings 46" Matrix 1 1 0.9 0.9
Matrix 2 0.9 1 0.9

White Tone e.g. 46PFLx007/x Matrix 3 0.9 0.9 1

Colour Temp R G B Matrix 4 0.9 1 1

Normal 127 92 95 Matrix 5 1 0.9 1

Cool 127 100 113 Matrix 6 1 1 0.9

Warm 127 83 59 Matrix 7 0.95 1 1

Matrix 8 1 0.95 1
Matrix 9 1 1 0.95
Table 6-6 White tone default settings 46"

White Tone e.g. 46PFL9707/x

6.3.3 TCON alignment (not applicable)
Colour Temp R G B
Normal 127 111 87 6.4 Option Settings
Cool 125 121 106
Warm 127 98 55 6.4.1 Introduction

Table 6-7 White tone default settings 47" The microprocessor communicates with a large number of I2C
ICs in the set. To ensure good communication and to make
White Tone 47PFL6907
digital diagnosis possible, the microprocessor has to know
Colour Temp R G B
which ICs to address.
Normal 127 89 92
Cool 127 94 116
Notes:
Warm 127 77 50
After changing the option number(s), save them by
pressing the OK button on the RC before the cursor is
moved to the left, select STORE in the SAM root menu
Table 6-8 White tone default settings 55" and press OK on the RC.
The new option setting is only active after the TV is
White Tone e.g. 55PFLx007/x switched off / stand-by and on again with the mains
Colour Temp R G B switch (the NVM is then read again).
Normal 127 90 88
Cool 127 97 110 6.4.2 (Service) Options
Warm 127 78 50

From 2011 onwards, it is not longer possible to change

Table 6-9 White tone default settings 60" individual option settings in SAM. Options can only be changed
all at once by using the option codes as described in section
White Tone e.g. 60PFL9607/x 6.4.3.
Colour Temp R G B
Normal 126 119 99 6.4.3 Opt. No. (Option numbers)
Cool 119 122 122
Warm 127 102 63 Select this sub menu to set all options at once (expressed in
two long strings of numbers).
6.3.2 Ambilight An option number (or option byte) represents a number of
different options. When you change these numbers directly,
you can set all options very quickly. All options are controlled
Each ambient light module is aligned by a matrix and by the
brightness. After replacement of a spare module, the via eight option numbers.
When the NVM is replaced, all options will require resetting. To
brightness/color can be adjust/fine-tuned according the
be certain that the factory settings are reproduced exactly, you
neighbouring modules.
1. Go to SAM. must set both option number lines. You can find the correct
option numbers on the rearcover sticker from the TV set.
2. Select Alignments.
Example: The options sticker gives the following option
3. Select Ambilight. A white test pattern shall be displayed
by the ambilight modules. numbers:
Group 1 : 08192 00133 01387 45160

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 Alignments QFU1.1E LA 6. EN 41

Group 2 : 12232 04256 00164 00000
The first line (group 1) indicates hardware options 1 to 4, the
second line (group 2) indicate software options 5 to 8.
Every 5-digit number represents 16 bits (so the maximum value
will be 65536 if all options are set).
When all the correct options are set, the sum of the decimal
values of each Option Byte (OB) will give the option number.
Diversity
Not all sets with the same Commercial Type Number (CTN)
necessarily have the same option code!
Use of Alternative BOM => an alternative BOM number usually
indicates the use of an alternative display or power supply. This
results in another display code thus in another Option code.
Refer to Chapter 2. Technical Specs, Diversity, and
Connections.
6.4.4 Option Code Overview
Refer to the rearcover sticker in the set for the correct option
codes.
Important: after having edited the option numbers as
described above, you must press OK on the remote control
before the cursor is moved to the left!
access to the Smart TV portals. The loading of the CTN and
production code can also be done via ComPair (Model number
programming).
After a SSB repair, the original channel map can be restored,
provided that the original channel map was stored on a USB
stick before repair was commenced and that basic functionality
of the TV, needed for this procedure, was not hampered as a
result of the defect. The procedure of channel map cloning is
clearly described in the (electronic) user manual.
6.5.1 SSB identification
Whenever ordering a new SSB, it should be noted that the
correct ordering number (12nc) of a SSB is located on a sticker
on the SSB. The format is <12nc SSB><serial number>. The
ordering number of the correct Service SSB is the one
preceded by the letter S in case 2 or more ordering numbers
are present on the bar code sticker.

6.5 Reset of Repaired SSB

A very important issue towards a repaired SSB from a Service
repair shop (SSB repair on component level) implies the reset
of the NVM on the SSB.
A repaired SSB in Service should get the service Set type
00PF0000000000 and Production code 00000000000000.
Also the virgin bit needs to be set. To set all this, you can use
the ComPair tool or use the NVM editor and Setup => TV
settings => General settings => Reinstall TV (virgin mode).

After a repaired SSB has been mounted in the set (set repair
on board level), the type number (CTN) and production code +
12NCs (SSB, display and supply) of the TV has to be set 18310_221_090318.eps
according the type plate of the set (no info on 12NCs here). For 090319
this, you can use the NVM editor in SAM. This action also
ensures the correct functioning of the Smart TV feature and Figure 6-1 SSB identification

6.6 Total Overview SAM modes

Table 6-11 SAM mode overview

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description

Hardware Info A. SW version e.g. QF1EU_0.9.1.0 Display TV & Stand-by SW version and CTN serial
B. Stand-by processor version e.g. STDBY_83.84.0.0 number

C. Production code e.g. see type plate

Operation hours Displays the accumulated total of operation hours.TV
switched on/off & every 0.5 hours is increase one
Errors Displayed the most recent errors
Reset error buffer Clears all content in the error buffer
Alignment White point Colour temperature Normal 3 different modes of colour temperature can be
Warm selected

Cool
White point red LCD White Point Alignment. For values,
White point green see Table 6-3 White tone default settings 40" to 6-5
White tone default settings 46"
White point blue
Ambilight Select module
Brightness
Select matrix
Option numbers Group 1 e.g. 00008.00001.15421.02239 The first line (group 1) indicates hardware options 1
to 4
Group 2 e.g. 44816.34311.33024.00000 The second line (group 2) indicates software options
5 to 8
Store Store after changing
Initialise NVM N.A.
Store Select Store in the SAM root menu after making any
changes

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 EN 42 6. QFU1.1E LA Alignments

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description

Software maintenance Software events Display Display information is for development purposes
Clear
Test reboot
Test kernel crash
Test application crash
Hardware events Display Display information is for development purposes
Clear
Test setting Digital info Current frequency: 538
QAM modulation: 64-qam Display information is for development purposes
Symbol rate:
Original network ID: 12871
Network ID: 12871
Transport stream ID: 2
Service ID: 3
Hierarchical modulation: 0
Selected video PID: 35
Selected main audio PID: 99
Selected 2nd audio PID: 8191
Install start frequency 000 Install start frequency from 0 MHz
Install end frequency 999 Install end frequency as 999 MHz
Default install frequency
Installation Digital only Select Digital only or Digital + Analogue before
Digital + Analogue installation

RF4CE pairing tables Clear paired remote control

Development file Development 1 file version Display parameters DISPT6.0.23.18 Display information is for development purposes
versions Acoustics parameters SNDPR0.0.3.6
PQ - FUSIO 6.1.4.13
Ambilight parameters PRFAM 6.1.0.2
Temp comp parameters 2.0
Development 2 file version 12NC one zip software Display information is for development purposes
Initial main software QF1EU_0.4.5.0
NVM version QF1EU_0.4.5.0
e-Sticker software
Upload to USB Channel list Item Channel list removed from the user interface
Personal settings
Option codes
Alignments
Identification data
History list
All (options included)
Download from USB Channel list Item Channel list removed from the user interface
Personal settings
Option codes
Alignments
Identification data
All (options included!)
NVM editor Type number NVM editor; key-in and update Type number,
Production code Production code and 12NCs after SSB replacement

12NC SSB
12NC display
12NC supply

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 Circuit Descriptions QFU1.1E LA 7. EN 43

7. Circuit Descriptions
Index of this chapter:
7.1 Introduction
7.2 Power Supply
7.3 General Power Architecture
7.4 Back-End Processing 7.1 Introduction
The QFU1.1E LA chassis is part of the FUSION platform and
Notes: covers sets in the 69xx, 7xxx, 8xxx and 9xxx range.
Only new circuits (circuits that are not published recently)
are described. 7.1.1 FUSION 2011 Architecture Overview
Figures can deviate slightly from the actual situation, due
to different set executions.
For details about the chassis block diagrams refer to
For a good understanding of the following circuit chapter 9. Block Diagrams. An overview of the FUSION 2012
descriptions, please use the wiring-, block- (see chapter
architecture can be found in Figure 7-1 and Figure 7-2.
9. Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts). Where
necessary, you will find a separate drawing for clarification.

DDR 1GB FLASH

4 2Gb 1GB

64/48

NR 8 V-by-1 RGB Cell

DVB-T/C
ISDB-T DEI FHD@240
Hybrid Analogue PQ Enhancement CIN@240
Tuner FRC
DVBC/T2
3D: Active
2D-3D conversion
Analogue BL-PWM
Inputs BL BL-I-CTRL Backlight 8
DVB-S2 PWM
DVB-S2 3D_LR
Tuner
3D goggle drive
NVM 3D-LED 3D-IR
USB

USB

CI+ FPGA
Spartan 6
USB LX4
HDMI HUB
9385

ETH
Skype
PHY

19210_064_120504.eps
120504

Figure 7-1 Architecture of FUSION platform 2012 (69xx, 7xxx, 8xxx range)

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 EN 44 7. QFU1.1E LA Circuit Descriptions

DDR 1GB FLASH

4 2Gb 1GB

64/48

NR 8 V-by-1 RGB Cell

DVB-T/C
ISDB-T DEI FHD@240
Hybrid Analogue PQ Enhancement CIN@240
Tuner FRC
DVBC/T2
3D: Active
2D-3D conversion
Analogue BL-SPI
Inputs BL BL VS BL - HDR
DVB-S2
DVB-S2
Tuner 3D_LR 3D goggle 3D-LED
drive 3D-IR
NVM FPGA
USB

USB

Spartan 6
CI+ LX4

USB
HDMI HUB
9385

ETH
Skype
PHY

19210_063_120504.eps
120504

Figure 7-2 Architecture of FUSION platform 2012 (9xxx range)

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 Circuit Descriptions QFU1.1E LA 7. EN 45

7.1.2 SSB Cell Layout

L,R Subw
SiS CTRL Vx1 SC BL Temperature
sensor

VGA out
DC-DC 1M95 (PSU)
Class D
Scart dongle
+12V AL
Hybrid tuner (PSU)
Fusion SOC
DVBS tuner
BL dim
(PSU)
USB TS LAN
HDMI ARC UART
To AL
(power + SPI)

HDMI HDMI
DC-DC usb WIFI
MUX
HDMI usb SKYPE

analogue inputs
dongles
SPDIF

Phones
USB

USB

CA+
HDMI

HDMI

19280_099_120503.eps
120503

Figure 7-3 SSB layout cells (top view)

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 EN 46 7. QFU1.1E LA Circuit Descriptions

SDM
FPGA
CA+
Set NVM

19280_100_120503.eps
120503

Figure 7-4 SSB layout cells (bottom view)

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 Circuit Descriptions QFU1.1E LA 7. EN 47

7.2 Power Supply

7.2.1 Power Supply Unit

Display
All power supplies are a black box for Service. When any of
1316 1M54 1M09 Ambi-light
these power supplies is defective, a new board must be 1319
ordered and the defective one must be returned, unless the
main fuse of the board is broken. Always replace a defective
fuse with one with the correct specifications! This part is
available in the regular market. SSB
1M99/1M11
Consult the Philips Service web portal for the order codes of the 1M95
boards.
1308
7.3 General Power Architecture
For the power architecture refer to figure 7-5 and 7-6.
For start-up steps (for trouble-shooting), refer to figure 7-7. The
start-up sequence is marked with numbers in red.
AC-in
19280_103_120504.eps
120504

Figure 7-5 General power architecture

AL

PSU switch +3V3AL

AC in
ENABLE-3V3-AMBI Tcon
+3V3

DC-DC

+12V
DC-DC
PLF
converters

12V
Undervoltage
detect

STANDBY DETECT12V
LCD-PWR-ONn
STANDBYn
Fusion
SPLASH-ON ENABLE-WOLAN
SoC
internal
Wifi dongle
LED driver POWER-OK

Ethernet
3V3stby +3V3-STANDBY switch +3V3-LAN PHY

19210_075_120504.eps
120504

Figure 7-6 Functional supply overview

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 EN 48 7. QFU1.1E LA Circuit Descriptions

10000_000full_090126.eps
091118

Figure 7-7 Functional power overview - power sequence

7.4 Back-End Processing

For the configuration, refer to Figure 7-8 to Figure 7-11.

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 Circuit Descriptions QFU1.1E LA 7. EN 49

19210_065_120504.eps
120507

Figure 7-8 Back-end configuration xxPFL6xxx/xx series

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 EN 50 7. QFU1.1E LA Circuit Descriptions

19210_066_120504.eps
120504

Figure 7-9 Back-end configuration xxPFL7xxx/xx & xxPFL8xxx/xx series

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 Circuit Descriptions QFU1.1E LA 7. EN 51

19210_067_120504.eps
120504

Figure 7-10 Back-end configuration xxPFL9xxx/xx series

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 EN 52 7. QFU1.1E LA Circuit Descriptions

19210_068_120504.eps
120504

Figure 7-11 Back-end configuration Platinum (Cinema) series

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 IC Data Sheets QFU1.1E LA 8. EN 53

8. IC Data Sheets
This chapter shows the internal block diagrams and pin
configurations of ICs that are drawn as black boxes in the
electrical diagrams (with the exception of memory and logic
ICs).

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 EN 54 8. QFU1.1E LA IC Data Sheets

8.1 Diagram 10-2-7 B02A, Tuner-channel decoder B02A, CXD2834 (IC7KC0)

Block diagram
MPEG
TUNER Decoder
TAINP (IF)
IF+ 12-bit
TAINM (IF) ADC
IF-

DVB-T2 LDPC/BCH Stream

RFAIN 10-bit TSCLK
(RFAGC-MON) Demodulator Decoder Processor TSCLK
ADC
TSVALID
TSVALID
TSIF
GPIO1 (PWM) TSSYNC
(RFAGC) GPIO TSSYNC
DVB-T
TSDATA7-0
Demodulator TSDATA7-0
TS
RS Decoder
TIFAGC Smoothing
IFAGC AGC DVB-C
Demodulator

TTUSCL SCL
SCL SCL
TTUSDA I2C IF SDA
SDA SDA

41MHz or OSC
20.5 MHz PLL

XTALI
XTALO

Pinning information

19220_025_120227.eps
120227

Figure 8-1 Internal block diagram and pin configuration

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 Block Diagrams QFU1.1E LA 9. EN 55

9. Block Diagrams
9.1 Wiring diagram 7000 series 40"

7000 series, 2 sided AmbiLight 40"

8A02

8802
8M54
8801
8M99 8A01

1A04
1A01

8C31
8316 1M99 1M54 1A04 1A05
1T71 1M95 1C31 1C30
To Wifi USB
5p 1.25mm
14 p 18p 18p
8P 9p Phono
1316 1M54 1M99 1M95 1M09
4p Fan control or temp
9p 8P sensor
20p 14 p 6p
/1M11 (4p)

8M95 SPI

1F53
FFC 15p

1G50/1G55

Conditionnal access

1A05
41p
Wifi
SSB
B (1111)

MAIN POWER SUPPLY

A (1050) 8G51

1G51
51p

USB
inlet 5p 1.25mm

1C21
1C20/1C21 Local control FFC 18 p

USB
8308

1D35
3p

1D02
3p Sub woofer

1D01
4p Speakers

HDMI
HDMI
Keyboard Control Panel
AmbiLight

AmbiLight
1F00
1D11
(1164)

(1163)
13

2p3 1R00
08

Opto
1G51 SP
VGA HDMI HDMI HDMI
1E01 DIF
51p

AL AL
Panel
1M21
(1012)

(1004) 8D01

1A01
1A04

8M20

8M21

Sensor
J (1010)
1M21 1M20

Board Level Repair

Component Level Repair
Only for authorized workshops
19210_097_120514.eps
120514

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 Block Diagrams QFU1.1E LA 9. EN 56

9.2 Wiring diagram 8000 series 40"

8000 series, 3 sided AmbiLight 40"

AmbiLight AmbiLight
1A01
AL (1172) 1A03 1A01
AL (1170) 1A03

8A04 8A02
1A01

1A04
8802
8801 8M54

8A03 8M99 8A01

8C31
8316 1M99 1M54 1A04 1A05
1T71 1M95 1C31 1C30
To Wifi USB
5p 1.25mm
14 p 18p 18p
8P 9p Phono
1316 1M54 1M99 1M95 1M09
4p Fan control or temp
9p 8P sensor
20p 14 p 6p

1A05
/1M11 (4p)

8M95 SPI

1F53
FFC 15p

1G50/1G55

Conditionnal access
41p
Wifi
SSB
B (1111)

MAIN POWER SUPPLY

A (1050) 8G51

1G51
51p

USB
inlet 5p 1.25mm

1C21
1C20/1C21 Local control FFC 18 p

USB
8308

1D35
3p

1D02
3p Sub woofer

1D01
4p Speakers

HDMI
AmbiLight

AmbiLight
HDMI
Keyboard Control Panel
(1164)

(1163)
1F00
1D11
13

2p3 1R00
08

AL 1G51
VGA 1E01
Opto
SP
DIF
HDMI HDMI HDMI AL
51p
1A04

Panel

1A01
1M21
(1012)

(1004) 8D01

8M20

8M21

Sensor
J (1010)
1M21 1M20

Board Level Repair

Component Level Repair
Only for authorized workshops
19210_098_120515.eps
120515

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 Block Diagrams QFU1.1E LA 9. EN 57

9.3 Wiring diagram 6000 series 42"

6000 series, 2 sided AmbiLight 42"

to Panel
8A02

8802

8316 8A01
8319

1A04
1A01

1316 1319
8801 13p
13p 1T71 1M95 1M99 1M54 1A04 1A05 1C31 1C30
To Wifi USB
5p 1.25mm
14 p 18p 18p
8P 9p Phono
4p Fan control or temp
sensor

1M99
8M99 4p

SPI

1F53
FFC 15p

MAIN POWER SUPPLY

A

1G50/1G55
1M95

Conditionnal access
(1050) 8M95 14 p
41p
8G50

1A05
SSB
B (1111)

1M09
6p

245 245

1G51
8G51 51p

USB
5p 1.25mm
Woofer

1C21
1C20/1C21 Local control FFC 18 p

USB
1D35
3p

1D02
3p Sub woofer

2p3

1D01
4p Speakers

HDMI
1308

HDMI
1F00
1D11
Keyboard Control Panel

8308
1R00
Opto
SP
VGA HDMI HDMI HDMI
AmbiLight

AmbiLight
1E01 DIF
(1164)

(1163)
8C31 8M20
1M21

AL 1G50 1G51 AL
(1012)

41p 51p

inlet

E Panel

Wifi
(1004)

1A01
1A04

Tweeter Tweeter

8M21

3p HL 1M21
1M20
Sensor
J 11p FH52
(1010)

Board Level Repair

Component Level Repair
Only for authorized workshops
19212_026_120913.eps
120913

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 Block Diagrams QFU1.1E LA 9. EN 58

9.4 Wiring diagram 7000 series 46"

7000 series, 2 sided AmbiLight 46"

8A02

40A1
1A01

8
8802
8A01
8801 8M54
8M99

1T71 1M95 1M99 1M54 1A04 1A05 1C31 1C30

To Wifi USB
1M54 5p

50A1
1316 1M99 1M95 1M09 14 p 5p
8P 9p Phono
20p 9p 8P 6p
8M95 Fan control or temp
14 p 4p
sensor
/1M11 (4p)

SPI

1F53
FFC 15p

8C31

1G50/1G55

Conditionnal access
Wifi 41p
5p 1.25mm

SSB
B (1111)

MAIN POWER SUPPLY

A (1050)
8G51

1G51
51p

USB
5p 1.25mm

8308

1C21
1C20/1C21 Local control FFC 18 p

USB
inlet

1D35
3p

1D02
3p Sub woofer

1D01
4p Speakers

HDMI
HDMI
For possible

1F00
1D11
extra Audio
amplifier
13

2p3
08
AmbiLight

AmbiLight
1R00
Opto
SP
VGA HDMI HDMI HDMI
1E01 DIF
Keyboard Control Panel
(1164)

(1163)
AL 8M20 AL
1G51
51p

Panel
(1012)
1M21

E
(1004) 8D01

10A1
1A03

8M21

Sensor
J (1010)
1M21 1M20

Board Level Repair

Component Level Repair
Only for authorized workshops
19210_099_120515.eps
120515

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 Block Diagrams QFU1.1E LA 9. EN 59

9.5 Wiring diagram 8000 series 46"

8000 series, 3 sided AmbiLight 46"

AmbiLight AmbiLight
1A03
AL (1170) 1A01 1A03
AL (1172) 1A01

8A04 8A02

1A04
1A01

8A03

8A01 8
8802
8801 8M54
8M99

1T71 1M95 1M99 1M54 1A04 1A05 1C31 1C30

To Wifi USB

1A05
1316 1M54 1M99 1M95 5p
1M09 14 p 5p
8P 9p Phono
20p 9p 8P 6p
8M95 Fan control or temp
14 p 4p
sensor
/1M11 (4p)

SPI

1F53
FFC 15p

8C31

1G50/1G55

Conditionnal access
Wifi 41p
5p 1.25mm

SSB
B (1111)

MAIN POWER SUPPLY

A (1050)
8G51

1G51
51p

USB
5p 1.25mm

8308

1C21
1C20/1C21 Local control FFC 18 p

USB
inlet

1D35
3p

1D02
3p Sub woofer

1D01
4p Speakers

HDMI
HDMI
For possible

1F00
1D11
extra Audio
amplifier
13

2p3
08
AmbiLight

AmbiLight
1R00
Opto
SP
VGA HDMI HDMI HDMI
1E01 DIF
Keyboard Control Panel
(1164)

(1163)
AL 8M20 AL
1G51
51p

Panel
(1012)
1M21

E
(1004) 8D01

1A01
1A03

8M21

Sensor
J (1010)
1M21 1M20

Board Level Repair

Component Level Repair
Only for authorized workshops
19210_100_120515.eps
120515

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 Block Diagrams QFU1.1E LA 9. EN 60

9.6 Wiring diagram 9000 series 46"

9000 series, 3 sided AmbiLight 46"

AmbiLight AmbiLight
1A01
AL (1172) 1A03 1A01
AL (1170) 1A03

8A02
8A04

1A04
1A01

8A03

8802

1A05
B
1319 1316 14p 15p FFC 0.5 mm Hirose I 2S

Wifi
8801 5p 1.25mm

8A01
8319

1T71 1M95 1M99 1M54 1A04 1A05 1C31 1C30

To Wifi USB
5p 1.25mm
18p 18p
8316 14 p 8P 9p Phono
4p Fan control or temp
8F53 sensor

1319 1316 SPI

1F53
FFC 15p

12p 14p

1G50/1G55

Conditionnal access
8M95 41p

SSB
8M99
B (1111)

1G51
8151 51p
1M99

8p

USB
5p 1.25mm

MAIN POWER SUPPLY

A
1M95

(1050) 14 p

1C21
8C31 1C20/1C21 Local control FFC 18 p

USB

AmbiLight
AmbiLight

1D35
3p

1D02
3p Sub woofer

(1163)
(1164)

1D01
1M09

4p Speakers

HDMI
6p

HDMI
AL AL
Keyboard Control Panel

1F00
1D11
inlet

1R00
1A04

1A01
Opto
SP
VGA HDMI HDMI HDMI
1E01 DIF
8408

2p3
(1012)

51p 1G51

E
1308
1M21

8121

8M20

Sensor
1M21 1M20
J (1010)

Board Level Repair

Component Level Repair
Only for authorized workshops
19212_027_120913.eps
120913

2012-Sep-14 back to
div. table
 Block Diagrams QFU1.1E LA 9. EN 61

9.7 Wiring diagram 6000 series 47"

6000 series, 2 sided AmbiLight 47"

8A02

8802

8801 8A01

1A04
1A01

8316
8M99
8319
8M95

1316 1319 8C31

13p 13p

1T71 1M95 1M99 1M54 1A04 1A05 1C31 1C30

To Wifi USB
5p 1.25mm
14 p 18p 18p
8P 9p Phono

1M99
4p Fan control or temp
sensor
4p
MAIN POWER SUPPLY
A (1050) SPI

1F53
FFC 15p

1A05
1M95
14 p

1G50/1G55

Conditionnal access
41p
8G50
SSB
B (1111)

1M09
6p
Woofer

1G51
51p
8G51

USB
5p 1.25mm

1C21
1C20/1C21 Local control FFC 18 p

USB
1D35
3p

1D02
2p3 3p Sub woofer

1308

1D01
4p Speakers

HDMI
HDMI
Keyboard Control Panel

1F00
1D11
8308
1R00
Opto
AmbiLight

AmbiLight
SP
VGA HDMI HDMI HDMI
1E01 DIF
(1164)

(1163)
8T71
1M21

AL 8M20 AL
(1012)

1G50 1G51
41p41p 51p

E inlet
Panel

1A01
1A04

(1004)

Wifi
Tweeter Tweeter

8M21 1T02

Temp se
sensor
nso
or

3p HL 1M20
Sensor
J 1M21 11p FH52
(1010)

Board Level Repair

Component Level Repair
Only for authorized workshops
19212_028_120914.eps
120914

2012-Sep-14 back to
div. table
 Block Diagrams QFU1.1E LA 9. EN 62

9.8 Wiring diagram 7000 series 55"

7000 series, 2 sided AmbiLight 55"

8M54
1A01

1A04
8A02 8802

8316
8801

8M99 8A01

1316 1M54

20p 9p 1T71 1M95 1M99 1M54 1A04 1A05 1C31 1C30

1A05
1M99
To Wifi USB
6p
8P 14 p 8P 9p 5p
Phono
4p Fan control or temp .
sensor

1M95
14 p 8M95 SPI

1F53
FFC 15p

MAIN POWER SUPPLY

1G50/1G55

Conditionnal access
A

1M09
6p 41p
(1050)
SSB
B (1111)

1G51
8G51 51p

USB
1C21

USB
1D35
3p

1D02
3p Sub woofer

2p3

1D01
4p Speakers

HDMI
1308

HDMI
For possible

1F00
8308

1D11
extra Audio
amplifier

1R00
Opto
SP
VGA HDMI HDMI HDMI
1E01 DIF
AmbiLight

AmbiLight
inlet
(1164)

(1163)
Keyboard Control Panel

AL AL
1A05

Wifi 8C31
5p 1.25mm

1G51
51p

Panel
1M21

1A01
(1012)
1A04

(1004) 8D01

8M20

8M21

Sensor
J (1010)
1M21 1M20

Board Level Repair

Component Level Repair
Only for authorized workshops
19210_101_120515.eps
120515

2012-Sep-14 back to
div. table
 Block Diagrams QFU1.1E LA 9. EN 63

9.9 Wiring diagram 8000 series 55"

8000 series, 3 sided AmbiLight 55"

AmbiLight AmbiLight AmbiLight

1A01 1A05
AL (1172) 1A03 1A01 1A05
AL (1171) 1A03 1A01 1A05
AL (1170) 1A03

8A06
6
8A03

1A01
8A05 8A04
1A01

8M54

8802

8316
AmbiLight

AmbiLight
8801
(1175)

(1173)
8M99 8A01

1316 1M54

AL 20p 9p 1T71 1M95 1M99 1M54 1A04 1A05 1C31 1C30

AL

1M99
To Wifi USB
6p
8P 14 p 8P 9p 5p
Phono
4p Fan control or temp .
sensor

1M95
14 p 8M95 SPI

1A03
1F53
FFC 15p
1A03

MAIN POWER SUPPLY

1G50/1G55

Conditionnal access
A

1M09
6p 41p
8A07 (1050)
SSB
B (1111)

1G51
8G51 51p

USB

1A01
8A02
1A01

1C21

USB
1D35
3p

1D02
3p Sub woofer

2p3

1D01
4p Speakers

HDMI
1308

1A05
HDMI
1A05

For possible

1F00
8308

1D11
extra Audio
amplifier

1R00
Opto
SP
VGA HDMI HDMI HDMI
1E01 DIF
AmbiLight

inlet
(1176)

Keyboard Control Panel

AL Wifi
5p 1.25mm
8C31
AL

1G51
51p

Panel
1M21
(1012)

1A03
1A03

(1004) 8D01

8M20

8M21

Sensor
J (1010)
1M21 1M20

Board Level Repair

Component Level Repair
Only for authorized workshops
19210_102_120515.eps
120515

2012-Sep-14 back to
div. table
 Block Diagrams QFU1.1E LA 9. EN 64

9.10 Wiring diagram 9000 series 60"

9000 series, 3 sided AmbiLight 60"

AmbiLight AmbiLight AmbiLight

1A04 1A05
AL (1172) 1A02 1A04 1A05
AL (1171) 1A03 1A04 1A05
AL (1170) 1A02

8A06
8A04

8A05
Wifi

1A04
8A03
1A02

5p 1.25mm

8316
8319

1A05
AmbiLight

1316/CN102 1319/CN101

AmbiLight
12p 1.5mm 14p 1.25mm
(1175)

I 2S

(1173)
15 FFC 0.5 mm Hirose

AL 8C31
1319

12p
1316

14p
AL
LED drivers

1M99
8p 8M99
1A03

1M95
14 p 8M95

1M09
6p

1A02
1T71 1M95 1M99 1M54 1A04 1A05 1C31 1C30
1C3
30
1A04

To Wifi USB
6p
p
14 p 8P 9p 5p
Phono
Pho
ono
4p Fan control or temp .
MAIN POWER SUPPLY sensor

A (1050)
SPI

1F53
8F53 FFC 15p

1G50/1G55

Conditionnal access
8A07 8A02
41p

SSB
B (1111)
1A02

1A04
1G51
51p

USB
8A01

1C21

USB
1D35

1A05
3p

8151

AmbiLight
1D02
AmbiLight

3p Sub woofer
2p3

1D01
4p Speakers

HDMI
1308

(1174)
(1176)

HDMI
8408 For possible

1F00
1D11
extra Audio
amplifier

AL VGA
1R00
Opto
SP
HDMI HDMI HDMI
AL
1E01 DIF

inlet
Keyboard Control Panel

8D01
1A05

1G51
51p

Panel
1M21

8120
8121
(1012)
1A04

1A02
(1004)
E

Sensor
J (1010)
1M21
M21 1M20

Board Level Repair

Component Level Repair
Only for authorized workshops
19212_029_120914.eps
120914

2012-Sep-14 back to
div. table
 Block Diagrams QFU1.1E LA 9. EN 65

9.11 Block Diagram Video

VIDEO
B02B DVBS-FE B02A TUNER-CHANNEL DECODER B03x FUSION B04B V-BY-ONE OUT
7RA0 7RA1 7J00
STV6110A STV0903BAC FUSION240
1R01 1G55
B03A TS_TSB_MCU B03E PANEL_USB
4 DVB-S 21 IP 7 DVB-S 78 TS-INT-VALID 9RC2-1 TS-CHDEC-VALID T26 TSSDEN 41
LAN_IO
TUNER CHANNEL TS-INT-SOP 9RC2-2 TS-CHDEC-SOP
SAT IN 20 IM 8
DECODER
75 U30 TSSSYNC TX0,1 VbyOne
74 TS-INT-CLOCK 9RC2-4 TS-CHDEC-CLK U29 TSSCLK
32 XTAL 122 TO DISPLAY
30 18 QP 12 73 TS-INT-DATA 9RC2-3 TS-CHDEC-DATA U28 TSSDI
19 QM 11
1RA0

16M
TX2,3
2 AGC 16 7KC0
31 CXD2834R

ONLY **PFL***7/K**
4 TS-CHDEC-VALID
DVBT2
B02A TUNER-CHANNEL DECODER
CHANNEL 3 TS-CHDEC-SOP TX4,5
1F00
SUT-RE214Z DECODER 5 TS-CHDEC-CLK
8 TS-CHDEC-DATA
PIN NUMBERING
4 IF_AGC 48
AGC1 PANEL DEPENDANT
2 5KC8 3KA0 IF-N-DVBT2 5KC1 2KCF 3KCB 37
TX6,7 8
IF1-_P
3 5KC9 3KA1 IF-P-DVBT2 5KC0 2KCE 3KCA 38
IF1-_N
ONLY **PFL***7/T**
RF IN
MAIN HYBRID B06M FE
TUNER
8 5FA5 3FA4 2FS1 5FS1 IF-IN-P
IF2-_N F30 IN_P

7 5FA4 3FA3 2FS2 5FS2 IF-IN-N F29 IN_N

IF2-_P
7FA1,2
9 EF SOC-IF-AGC F27 TAGCO_IF
AGC2

B06A HDMI
7HA0
SII9387ACT B03E PANEL_USB
1H05 LAN_IO
1 ERX2+ 33 TXC_P 86 HDMIF-RXC+ B30 RXC_P
3 ERX2- 32 TXC_N 87 HDMIF-RXC- C30 RXC_N
1

4
2

ERX1+ 31 TX0_P 84 HDMIF-RX0+ A29 RX0_P

6 ERX1- 30 TX0_N 85 HDMIF-RX0- B29 RX0_N
R4X
7 ERX0+ 29 TX1_P `82 HDMIF-RX1+ A28 RX1_P
9 ERX0- 28 TX1_N 83 HDMIF-RX1- B28 RX1_N
18
19

10 ERXC+ 27 TX2_P 80 HDMIF-RX2+ A27 RX2_P

HDMI 5 12 ERXC- 26 TX2_N 81 HDMIF-RX2- B27 RX2_N
CONNECTOR
B05B ANALOGUE EXTERNALS B04F AUDIO-VIDEO
1VA1
1H04 B03E AV_IN_OUT
1 10 SC1-R 2VWB PR-R3 C18 PR-R3
DRX2+ 24
14 SC1-G 2VW9 Y-G3 C20 Y-G3
3 DRX2- 23
1
2

4 22 18 SC1-B 2VWA PB-B3 C19 PB-B3

DRX1+
SCART 5 SC1-CVBS 2VW2 CVBS3 B16 CVBS3
6 DRX1- 21
R3X 17 3VA9 9VW4
7 DRX0+ 20 SC1-STATUS FS1 C17 FS1
9 19 9 3VAD SC1-BLK 3VWW FB1 B17 FB1
18

DRX0-
19

10 DRXC+ 18
HDMI 4 12 DRXC- 17 1VA5
CONNECTOR
1 R1-VGA 2VW5 PR-R1 A18 PR_R1
10

15
5

2 G1-VGA 2VW3 Y-G1 A20 Y_G1

1H03
HDMI 3 B1-VGA 2VW4 PB-B1 A19 PB_B1 B03C UMAC 1 DDR3 B03D UMAC 0 DDR3
1

SWITCH
11

1 CRX2+ 15 B03B DDR3

B03A TS_TSB_MCU
3 CRX2- 14 13 9VW1
VGA 3VAH H-SYNC-VGA PCHS J28 PCHS M1-MA M1-MA(0-15)
1
2

4 CRX1+ 13 CONNECTOR 14 9VW2

3VAJ V-SYNC-VGA PCVS J27 PCVS
6 CRX1- 12
R2X M1-MD M1-MD(0-15)
7 CRX0+ 11
B06G

D(8-15)
10 ANALOGUE EXTERNALS 7J01 7J02 7J03 7J04

D(0-7)
9 CRX0-
18
19

10 H5TQ2G83BFR H5TQ2G83BFR H5TQ2G63BFR H5TQ2G63BFR

CRXC+ 9 B03E AV_IN_OUT
HDMI 3 12 8 FUSION
CRXC- cVC4 C2S2
CONNECTOR DRX0- Y1-IN 2VW6 Y-G2 B20 Y_G2 UMAC SDRAM SDRAM SDRAM SDRAM
1VA8 CONTROLLER
256Mx8 256Mx8 128Mx16 128Mx16

D(16-31)
D(0-15)
cVC5 DRXC- C2S8 PB1-IN 2VW7 PB-B2
YPBPR B19 PB_B2
1H02
1 BRX2+ 6
PR1-IN PR1-IN 2VW8 PR-R2 B18 PR_R2
3 BRX2- 5
1VA4
1

4 BRX1+ 4
2

6 BRX1- 3 M0-MA M0-MA(0-31)

R1X CVBS
7 BRX0+ 2
9 BRX0- 1 M0-MD M0-MD(0-15)
CVBS1 CVBS1 2VW1 CVBS C15 CVBS1
18
19

10 BRXC+ 100
HDMI 2 12 BRXC- 99
CONNECTOR B07D CI B06C USB +5V-HDD B07C USB INTERN
1E01
B03E PANEL_USB 1
1H01 LAN_IO cEC0 2
1P00 AC29 USB2-DM USB-MAIN-DM
1 D2_N
ARX2+ 97 17 USB2-DP USB-MAIN-DP 3
+5VCA D2_P AC30 7EH1
3 ARX2- 96 4
18 cEC1 CY7C65634
1

4 ARX1+ 95
2

51 B03A FLASH +5V

6 ARX1- 94 1C30
R0X 52 CI_GPIO
7 ARX0+ 93 1
7EA0 +5V-PORTA
9 ARX0- 92 PCMCIA FRDx_PODDx CY7C65632 3 USB-CAM-DM 2
68P

CA-D(0-7) 1E03
18
19

10 ARXC+ 91 1 4 USB-CAM-DP 3
12 ARXC- 90 CA-A(0-13) FRDx_PODAx 2 4
HDMI 1 6 USB-PORTA-DM
CONNECTOR CONDITIONAL cEC2 7 USB-PORTA-DP 3
ACCESS 7PA1,2 AB29 USB1-DM USB-MAIN-DM 1
D1_N 4 11 USB
74LVC245APW
20 USB1-DP
cEC4 HUB

1EH1
AB30 USB-MAIN-DP 2

12M
+3V3 D1_P
+5V-PORTB
B03A TS_TSB_MCU 1E02 10 +3V3-LAN
11 USB 1 1C31
MDO(0-7) BUFFER CA-MDO(0-7) TS1Dx 2 1
1EA0 HUB 3 USB-PORTB-DM

12M
3 1 6 USB-WIFI-DM 2
4 USB-PORTB-DP
4 2 7 USB-WIFI-DP 3
10
B06L CONDITIONAL ACCESS 4

3PW2,3
CA-MDI(0-7) TS2ODx 12 USB-SET-DM 9EHA
MDI(0-7)
13 USB-SET-DP
9EHB
WITH SKYPE 19210_002_120313.eps
NO SKYPE
120419

2012-Sep-14 back to
div. table
 Block Diagrams QFU1.1E LA 9. EN 66

9.12 Block Diagram Audio

AUDIO
B02B DVBS-FE B02A TUNER-CHANNEL DECODER B03x FUSION B05A CLASS-D AMPLIFIER
7RA0 7RA1 7J00 7D60
STV6110A STV0903BAC FUSION240 TAS5731
1R01 B03A TS_TSB_MCU B03E AV_IN_OUT
4 DVB-S 21 IP 7 DVB-S 78 TS-INT-VALID 9RC2-1 TS-CHDEC-VALID T26 TSSDEN
TUNER CHANNEL 75 TS-INT-SOP 9RC2-2 TS-CHDEC-SOP U30 TSSSYNC
SAT IN 20 IM 8 5D78
DECODER TS-INT-CLOCK 9RC2-4 TS-CHDEC-CLK
32 122 74 U29 TSSCLK
XTAL WSI2SOUT Y27 WSI2SOUT 20
1D01
30 18 QP 12 73 TS-INT-DATA 9RC2-3 TS-CHDEC-DATA U28 TSSDI
SDI2SOUT1 AA30 SDI2SOUT1 22 L+ 1
19 QM 11
1RA0

16M SCKI2SOUT 9D54 1D02

SCKI2SOUT Y26 21
2 AGC 16 7KC0 9D52 15 5D75 2 1
31 L-
CXD2834R
SPEAKER L 2
ONLY **PFL***7/K** B03A TS_TSB_MCU R+ 3 3
4 TS-CHDEC-VALID 3D63 19
DVBT2 MUTE H26 AUDIO-MUTEn
B02A TUNER-CHANNEL DECODER CHANNEL 3 TS-CHDEC-SOP R- 5D80 4
1F00 SPEAKER
5 TS-CHDEC-CLK 1 L+
SUT-RE214Z DECODER SPEAKER R WOOFER
4 IF_AGC 48 8 TS-CHDEC-DATA
AGC1 B01A DETECT12V 5D72
46 L- PASSIVE 2.1
3KA0 IF-N-DVBT2 5KC1 2KCF 3KCB 7D50-1 7D50-2 CLASS D
2 5KC8 37
IF1-_P 7D70 POWER 5D71
25 39 R+
3 5KC9 3KA1 IF-P-DVBT2 5KC0 2KCE 3KCA 38 AMPLIFIER
IF1-_N 1D01
ONLY **PFL***7/T**
36 R- L+ 1
RF IN
MAIN HYBRID B06M FE 1D02
TUNER 5D81 2 1
L-
8 5FA5 3FA4 2FS1 5FS1 IF-IN-P
IF2-_N F30 IN_P SPEAKER L 2
B06Q RESET-FUSION-OUTn R+ 3 3
7 5FA4 3FA3 2FS2 5FS2 IF-IN-N F29 IN_N
IF2-_P
7FA1,2 R- 5D83 4 SPEAKER
9 EF SOC-IF-AGC F27 TAGCO_IF SPEAKER R
AGC2 WOOFER
5D77
ACTIVE 2.1 1D35
1
B06A HDMI B03A FLASH_CI_ 2
7HA0 GPIO
3D81 3 SOUND
SII9387ACT B03E PANEL_USB HPD R30 SPEAKER-DETECTn
IN
1H05 LAN_IO
STAND
1 ERX2+ 33 TXC_P 86 HDMIF-RXC+ B30 RXC_P
3 ERX2- 32 TXC_N 87 HDMIF-RXC- C30 RXC_N B07B HEADPHONE 7DH1
1

4
2

ERX1+ 31 TX0_P 84 HDMIF-RX0+ A29 RX0_P

7DH0-1,2 TPA6111
6 ERX1- 30 TX0_N 85 HDMIF-RX0- B29 RX0_N B03E AV_IN_OUT
R4X
7 ERX0+ 29 TX1_P `82 HDMIF-RX1+ A28 RX1_P B06Q RESET-FUSION-OUTn 5
9 ERX0- 28 TX1_N 83 HDMIF-RX1- B28 RX1_N
18

1DH4
19

10 ERXC+ 27 TX2_P 80 HDMIF-RX2+ A27 RX2_P HPHOL B21 HPHOL 2 AMPLI- 1

12 ERXC- 26 TX2_N 81 HDMIF-RX2- B27 RX2_N HPHOR 6 FIER 7
HDMI 5 HPHOR A21
CONNECTOR 14 HARC3 HEADPHONE
B06B
B05B ANALOGUE EXTERNALS B04F AUDIO-VIDEO OUT 3.5 mm

1VA1
1H04 B03E AV_IN_OUT
1 23 3VA7 SC-RIN 3VW7 2VWE AR-4 E23 AR_4
24
DRX2+ SCART 19 3VA8 SC-LIN 3VW9 2VWF AL-4 D23 AL_4 B03A TS_TSB_MCU B06Q CONTROL 7CW1
3 DRX2- 23 PCA9554
1
2

4 DRX1+ 22
STB_RSTO J29 STB_RST0 3CUC RESET-FUSION-OUTn
B05A B07B
6 DRX1- 21 7 ARC-SEL0 B06B
R3X
7 DRX0+ 20 I/O
9 19
B06G ANALOGUE EXTERNALS 8 ARC-SEL1 B06B
18

DRX0- EXPANDER
19

10 DRXC+ 18 1VA6
3VC6 VGA-LIN 3VWH 2VWJ AL-3 B23 AL_3 9 ARC-SEL2 B06B
HDMI 4 12 DRXC- 17
CONNECTOR AUDIO 3VC7 VGA-RIN 3VWK 2VWK AR-3 A23 AR_3
14 HARC2
B06B VGA/DVI

1H03
HDMI B03C UMAC 1 DDR3 B03D UMAC 0 DDR3
1 CRX2+ 15 SWITCH B03B DDR3
3 CRX2- 14 B06B HDMI-ARC 7HD0 B06P HDMI M1-MA M1-MA(0-15)
1
2

4 CRX1+ 13 74HC4052
6 CRX1- 12 HARC0 5XXX 9xxx
R2X 13 11 ARC-SEL0 B06Q M1-MD M1-MD(0-15)
7 11 B06B
CRX0+
5XXX 9xxx

D(8-15)
10 HARC1 14 10 ARC-SEL1 B06Q 7J01 7J02 7J03 7J04

D(0-7)
9 CRX0-
18

B06B
19

10 H5TQ2G83BFR H5TQ2G83BFR H5TQ2G63BFR H5TQ2G63BFR

CRXC+ 9 5XXX 9xxx
HARC2 15 9 ARC-SEL2 B06Q FUSION
HDMI 3 12 CRXC- 8 B06B MUX
CONNECTOR 14 5XXX 9xxx UMAC SDRAM SDRAM SDRAM SDRAM
HARC1 HARC3 12 B03E PANEL_USB CONTROLLER
B06B B06B 128Mx16 128Mx16
LAN_IO 256Mx8 256Mx8

D(16-31)
D(0-15)
HARC4 5XXX 9xxx 3 HDMI-ARC 3HW1 HEAC T27 HEAC
1H02 B06B 1
1 BRX2+ 6
3 BRX2- 5
B06K AUDIO
1

4 BRX1+ 4 B03E AV_IN_OUT

2

6 BRX1- 3 1J50 2 M0-MA M0-MA(0-31)

R1X +3V3
7 BRX0+ 2 SPDIF 1 SPDIFO E26 SPDIFO
9 1 OUT 3 M0-MD M0-MD(0-15)
BRX0-
18
19

10 BRXC+ 100
HDMI 2 12 BRXC- 99
CONNECTOR 14 HARC0 B07D CI B06C USB +5V-HDD B07C USB INTERN
B06B 1E01
B03E PANEL_USB 1
1H01 LAN_IO cEC0 2
1P00 AC29 USB2-DM USB-MAIN-DM
1 D2_N
ARX2+ 97 17 USB2-DP USB-MAIN-DP 3
+5VCA D2_P AC30 7EH1
3 ARX2- 96 4
18 cEC1 CY7C65634
1

4 ARX1+ 95
2

51 B03A FLASH +5V

6 ARX1- 94 1C30
R0X 52 CI_GPIO
7 ARX0+ 93 1
7EA0 +5V-PORTA
9 ARX0- 92 PCMCIA FRDx_PODDx CY7C65632 3 USB-CAM-DM 2
68P

CA-D(0-7) 1E03
18
19

10 ARXC+ 91 1 4 USB-CAM-DP 3
12 ARXC- 90 CA-A(0-13) FRDx_PODAx 2 4
HDMI 1 6 USB-PORTA-DM
CONNECTOR 14 HARC4 CONDITIONAL cEC2 7 USB-PORTA-DP 3
B06B 7PA1,2 AB29 USB1-DM USB-MAIN-DM 1
ACCESS D1_N 4 USB
74LVC245APW 11
20 USB1-DP
cEC4 HUB

1EH1
AB30 USB-MAIN-DP 2

12M
+3V3 D1_P
+5V-PORTB
B03A TS_TSB_MCU 1E02 10 +3V3-LAN
11 USB 1 1C31
MDO(0-7) BUFFER CA-MDO(0-7) TS1Dx 2 1
1EA0 HUB 3 USB-PORTB-DM

12M
3 1 6 USB-WIFI-DM 2
4 USB-PORTB-DP
4 2 7 USB-WIFI-DP 3
10
B06L CONDITIONAL ACCESS 4

3PW2,3
CA-MDI(0-7) TS2ODx 12 USB-SET-DM 9EHA
MDI(0-7)
13 USB-SET-DP
9EHB
WITH SKYPE 19210_004_120412.eps
NO SKYPE
120412

2012-Sep-14 back to
div. table
 Block Diagrams QFU1.1E LA 9. EN 67

9.13 Block Diagram Control & Clock Signals

CONTROL + CLOCK SIGNALS
B01A CONNECTORS AND PROTECTIONS B06A HDMI 7HA0 B03x FUSION B03C UMAC 1 DDR3 B03D UMAC 0 DDR3
SII9387ACT 7J00
TO PIN: FUSION240
7UA3 ARX-HOTPLUG 46
1M95 1H01-19 B03E PANEL_USB B03B DDR3
2 3UA0 STANDBYn BRX-HOTPLUG 50 M1-CONTROL
1H02-19 LAN_IO M1-CONTROL
B06Q HDMI
CRX-HOTPLUG 55
3UA1 1H03-19 SWITCH HDMIF-RX

1
2
TO 11 BL-ON DRX-HOTPLUG 74
B04B 1H04-19 M1-MA M1-MA(0-15)
POWER 3UA2 ERX-HOTPLUG 59
12 BL-DIM 1H05-19
SUPPLY B04A M1-MD M1-MD(0-15)
3UAA

18
19
BL-DIM1 68
B07F B04A RESET-HDMI-MUXn

D(8-15)
7J01 7J02 7J03 7J04

D(0-7)
13 3UA3 9HA1 H5TQ2G83BFR H5TQ2G83BFR H5TQ2G63BFR H5TQ2G63BFR
BL-I-CTRL 5x HDMI 1H01-13
B07E B03A TS_TSB_MCU
CONNECTOR 1H02-13 FUSION
14 3UA4 POWER-OK PCEC-HDMI HDMI-CEC M28
B04A 1H03-13 CEC UMAC SDRAM SDRAM SDRAM SDRAM
1H04-13 CONTROLLER 128Mx16 128Mx16
256Mx8 256Mx8

D(16-31)
D(0-15)
1H05-13

B01F MISCELLANEOUS B06E ETHERNET 7EF0 B03E PANEL_USB

1E00 AR8030 LAN_I/O
1M54
ETH-RXD GBE_RXD
2 5EF7-1,2
ETH-TXD GBE_TXD
TO M0-MA M0-MA(0-31)
POWER BL-DIM(1-8) B07F
40 EN-MDC W25
SUPPLY 9 GBE_MDC
EN-MDIO Y30 M0-MD M0-MD(0-15)
39
ONLY 7000/8000 SERIES ETHERNET GBE_MDIO
ETHERNET 5 3EF5 9EF1 EN-RXC V25
33
1C20 CONNECTOR GBE_RXC M0-CONTROL M0-CONTROL
1C21

1EF0
30 EN-RXEN W30

25M
1 3CYA RJ45 GBE_RXEN
1 LIGHT-SENSOR B06Q 32 EN-TXEN V30
2 2 3CYB 3D-LED_3D-RF B07F
4 GBE_TXEN B06D SERVICE +3V3 B04B V-BY-ONE OUT 1G55
3 3 3CYC 9CY2 LED2 7EF1 3GVB
B03A CTRL-DISP1 4
SEE I2C DIAGRAM
4 4 1 20 IRQ-WOLANn
TO B06Q
MAINSTREAM TV 3GWH

3CS0
3CS1
LIGHT 5 5 3CYD KEYBOARD_IRQ2-SRFn B06Q ONLY B07F 3D-LR-DISP 6 VbyOne
SENSOR/ 6 6 B03E UART_JTAG
TOUCH +3V3-STANDBY RESET-ETHERNETn I2C
1E06
CTRL-DISP2
3GWG
3
TO DISPLAY
7 7 B06Q 3CS3 3CS4-3 3CS4-1 B03A
3CYE RC_IRQ-RF4CEn B06Q TXD Y28 TXD-SERVICE 3
CONTROL UART
8 8 3CYF +5V 3CS2 3CS4-2 3CS4-4 3GWF
RXD-SERVICE 2 SERVICE CTRL-DISP3 7
9 9 B06F NAND-FLASH + EEPROM RXD Y29 B04A
7JA0 CONNECTOR ONLY 7000/8000 SERIES
10 10 B03A FLASH_CI 1
MT29F8G08 3GV9
GPIO 7CS1 SPLASH-ON
11 11 B06Q
12 ST232C
FRA_AD 9GV1
FLASH FRA(0-12)
B01A
BL-ON
13 3CYK TXD-RF4CE B04A 11 14
RES 14
512kx16 7 F-READY AG23
FREADY
8 F-OEn AK29 LEVEL B04D CONNECTOR - BACKLIGHT
15 3CYM RXD-RF4CE FOE 1G53
B04A 9 F-CEn AJ24 SHIFTER
16 3CYN 9CY1 LED1 BOOTCS 12 13 3GD8 3GD3-3
SEE I2C DIAGRAM B03E BL-SPI-CLK-FUS BL-SPI-CLK 5
17 17 NAND-ALE AK22
3CYP SPEAKER-DETECTn FRA14_ALE
B03A MAIN 16 NAND-CLE AE23 BL-SPI-SDO-FUS
3GD9
BL-SPI-SDO
3GD3-2
7
TO
18 3CYT RESET-RF4CE FRA13_CLE B03E
B06Q SW
18 F-WEn AK24 HOTEL TV ONLY POWER
FWE 3GD5 3GD3-1
B03E BL-SPI-CS_BL-I-CTRL-FUS BL-SPI-CS_BL-I-CTRL 11 SUPPLY
3GD6
BL-DIM 13
B02B DVBS 7RA0 7RA1 B02A TUNER-CHANNEL DECODER B04A
FE STV6110A STV0903BAC B03A TS_TSB_MCU
ONLY 9000 SERIES
21 IP 7 78 TS-INT-VALID 9RC2-1 TS-CHDEC-VALID T26 TSSDEN
TS-INT-SOP 9RC2-2 TS-CHDEC-SOP
B03E PANEL_USB B04A CONTROL B07E FPGA - POWER & CONTROL
20 IM 8 75 U30 TSSSYNC LAN_IO 7GG2
DVB-S 3CV3
32 122 74 TS-INT-CLOCK 9RC2-4 TS-CHDEC-CLK U29 TSSCLK BOOST E3 BL-DIM-FUS BL-DIM M25P40
DVB-S XTAL CHANNEL B01A B04D
18 QP 12 73 TS-INT-DATA 9RC2-3 TS-CHDEC-DATA U28 TSSDI 3CV2 FLASH
TUNER DECODER PWM0 E4 3D-LR-FUS 3D-LR 3D-LR 3D-LR MISO 2
19 QM 11 7KC0 MOSI 5 16Mbit
AGC CXD2834R CCLK 6
2 16
34 4 TS-CHDEC-VALID B03A FLASH_CI CSO-B 1
3CV5 FPGA
AMBI-SPI-MOSI 9GG1-4
1KC0

41M

30 31 DVBT2 3 TS-CHDEC-SOP GPIO GPIO16 D12 AMBI-SPI-MOSI-FUS AMBI-SPI-MOSI AMBI-SPI-OUT-MOSI

1RA0 SW
CHANNEL 5 TS-CHDEC-CLK
AMBI-SPI-CCLK-FUS
3CV4 AMBI-SPI-CCLK AMBI-SPI-CCLK 9GG1-2
35 GPIO15 C12 AMBI-SPI-OUT-CCLK
DECODER 8 TS-CHDEC-DATA
16M RESET-FUSION-OUTn 29 3CV7 POWER-OK 7GG4
B06Q GPIO20 E11 GPIO20
B01A
ONLY **PFL***7/T** 3CVM FPGA-SYS-CLK
GPIO0 B7 GPIO0 TXD-RF4CE
B01F
B06N SERIAL FLASH 7CT3
3CVP
M25P05-AVMN6 GPIO1 B10 GPIO1 RXD-RF4CE 1GGA
B01A
6 3CTU SF-CLK L30 SFCLK 3CV1
GPIO8 A11 GPIO8 CTRL-DISP3
FLASH 3 3CT2 SF-WP K30 SFWPn B04B
3CTZ 3CVA RESET-HDMI-MUXn 12M
128kx8 1 SF-CS L29 SFCES GPIO22 A12 GPIO22
B06A
5 3CT0 SF-SDI L28 SFSI
STANDBY 7 3CT9 SF-HOLDn L27 SFHOLDn B03A TS_TSB_MCU B06Q CONTROL B07F FPGA - I/O BANKS
SW 3CTH SF-SDO 3CWG SPLASH-ON
2 L26 SFSO STB_GP6 N27 STB-P6
B04B 7GF1
3CUB XC6SLX4
PWRON R29 PWRON STANDBYn
B01A 27 AMBI-SPI-OUT-MOSI
B03A FUSION B03A FLASH 3CW4 B01F BL-DIM(1-8)
B01F
SPEAKER-DETECTn R30 HPD CI_GPIO LGSEN M30 LGSEN LIGHT-SENSOR
B01F 26 AMBI-SPI-OUT-CCLK
CTRL-DISP1 C10 GPIO2 3CW3 3D-LED_3D-RF 45
B04B KYBRD J30 KYBRD KEYBOARD_IRQ2-SRFn B01F 43 3D-LR
B01F
CTRL-DISP2 C9 GPIO3 3CWM 50
B04B IR RC_IRQ-RF4CEn FPGA-SYS-CLK
IR M29 B01F 3D-LR-DISP 46
H29 XTLO24M B04B FPGA 65
3CW5 MISO
RESET-RF4CE
1J00

STB-P8
24M

STB_GP8 N25 B01F 64 MOSI

H30 XTLI24M 3CUC
STB_RSTO J29 STB-RSTO RESET-FUSION-OUTn 70 CCLK
B02A B06C B07C
B03E PANEL_USB 3CUA 38 CSO-B
LAN_IO STB_P7 N26 STB-P7 RESET-ETHERNETn
B03E FUSION B04D
BL-SPI-CLK-FUS A8 H_BK_LITE
B06E
3CWK IRQ-WOLANn
HP_DETECT K27 HP-DETECT
BL-SPI-SDO-FUS C8 TCON_ON B06E
B04D

B04D
BL-SPI-CS_BL-I-CTRL-FUS D2 PWM1 B06C USB +5V-HDD
1E01
B07C USB INTERN
B03E PANEL_USB
1
B07D CI 1P00 LAN_IO
cEC0 2
AC29 USB2-DM USB-MAIN-DM 7EH1 +5V
17 D2_N
+5VCA USB2-DP USB-MAIN-DP 3 1C30
18 D2_P AC30 CY7C65634
1
4
cEC1
51 B03A FLASH 7EA0 USB-CAM-DM 2
3
52 CI_GPIO CY7C65632
+5V-PORTA 4 USB-CAM-DP 3

1E03 4
CA-D(0-7) FRDx_PODDx
68P

1 17 RESET-FUSION-OUTn
B06Q
FRDx_PODAx cEC2 6 USB-PORTA-DM 2 USB
CA-A(0-13) AB29 USB1-DM USB-MAIN-DM 1 11
D1_N 3
7 USB-PORTA-DP HUB

1EH1

12M
7PA1,2 cEC4 4
PCMCIA AB30 USB1-DP USB-MAIN-DP 2
74LVC245APW D1_P
20 10 +3V3-LAN
+3V3 B03A TS_TSB_MCU +5V-PORTB 1C31
CONDITIONAL
11 USB 1E02 1
MDO(0-7) CA-MDO(0-7) TS1Dx 1
HUB 1 2
1EA0

ACCESS 6 USB-WIFI-DM
12M

3 USB-PORTB-DM 2 2 USB-WIFI-DP 3
BUFFER 7
10 4 USB-PORTB-DP 3 4
4

B06L CONDITIONAL 12 USB-SET-DM 9EHA

RESET-FUSION-OUTn 17
ACCESS B06Q 13 USB-SET-DP
3PW2,3 9EHB
CA-MDI(0-7) MDI(0-7) TS2ODx WITH SKYPE NO SKYPE 19210_021_120424.eps
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 Block Diagrams QFU1.1E LA 9. EN 68

9.14 Block Diagram I2C

IC
B03C UMAC 1 DDR3 B03x FUSION B06Q CONTROL B06F NAND-FLASH B05A CLASS-D B06A HDMI B06R TEMPERATURE B07F FPGA - B07A LPC DEBUG B06Q CONTROL
+ EEPROM AMPLIFIER SENSOR I/O BANKS
7J00 +3V3 +3V3
7J01 7J02
H5TQ2G83BFR H5TQ2G83BFR FUSION240

3CWW
3CWU

3CWV

3CWY
1CW6

3CUG

3CUF
SDRAM SDRAM 5 SCL-SSB 1
7CW0
256Mx8 256Mx8 B03E DEBUG
PCA9540B

D(8-15)
D(0-7)
4 SDA-SSB 3 ONLY
AA26 SCL-M3 1 2 CHANNEL

3HAW
3CUW

3HAV
3CUY

3TW1

3TW0

3GF8

3GF9
AIN-5V

3JA2

3JA3

3D56

3D55
MULTIPLEX.

9NAA

9NA9
AA25 SDA-M3 2 8 SCL-SRF
B03B 12 13 6 5 24 23 71 70 2 1 2 1

3HAB-4

3HAB-3
ERR
24 7 SDA-SRF 1H01
M1-MA(0-15) M1-MA 7CW1
ERR 7JA2 7D60 7HA0 16 7TW0 7GF1
44 ARX-DDC-SDA

3NAH
3NAJ
1
13

2
PCA9554 M24C64 TAS5711 SII9387 LM75 XC6SSLX4
M1-MD(0-15) M1-MD 15
45 ARX-DDC-SCL 24 25
I/O EEPROM AUDIO HDMI TEMPERATURE FPGA

18
19
EXPANDER (NVM) AMPLIFIER MUX BIN-5V SENSOR BL
HDMI
B03D UMAC 0 DDR3
CONNECTOR 1 7NA2

3HAB-2

3HAB-1
1CW7 ERR ERR ERR ERR ERR
41 35 37 ERR 1H02 42 38 LPC1768
1 23
7J03 7J04 DEBUG 48 BRX-DDC-SDA 16

1
2
H5TQ2G63BFR H5TQ2G63BFR FUSION ONLY 3 MAIN NVM
UMAC SW 49 BRX-DDC-SCL 15

18
CONTROLLER

19
SDRAM SDRAM CIN-5V
128Mx16 128Mx16 RES HDMI
D(16-31)
D(0-15)

CONNECTOR 2 RES RES RES

3HAA-4

3HAA-3
1H03
B06Q CONTROL B01F MISCELLANEOUS
53 CRX-DDC-SDA 16

1
2
+3V3
1T71 54 CRX-DDC-SCL 15
3TA1

18
1

19
M0-MA(0-31) M0-MA SET DIN-5V
3TA2 TEMPERATURE HDMI

3CUG

3CUF
3 SENSOR
M0-MD CONNECTOR 3

3HAC-1

3HAC-2
M0-MD(0-15)
1H04
1CV8 72 16
CRX-DDC-SDA

1
2
U26 SCL-S 3CUH 1
B06F NAND-FLASH + EEPROM
DEBUG 1C21 73 CRX-DDC-SCL 15
3CUJ 3 ONLY 3CYG
U27 SDA-S

18
1

19
TO
CIN-5V
7JA0 3CYH LIGHT SENSOR HDMI
MT29F8G08 B03A RES 3 TOUCH CONTROL
CONNECTOR 4

3HAA-2

3HAA-1
RES 1H05
FLASH FLASH
57 CRX-DDC-SDA 16
B06D SERVICE +3V3

1
2
CI
512kx16 GPIO
58 CRX-DDC-SCL 15

18
19
FRA(0-12) FRA_AD
MAINSTREAM TV

3CS0
3CS1
ONLY HDMI
CONNECTOR 5
MAIN
SW 1E06
JTAG 3CS3 3CS4-3 3CS4-1 +5V-EDID B05B ANALOGUE +5V-VGA
Y28 TXD-SERVICE 3
I2C UART EXTERNALS
UART 3CS2 3CS4-2 3CS4-4 SERVICE
Y29 RXD-SERVICE 2

3HAL-1

3HAL-2

3HAL-1

3HAL-2
CONNECTOR 1VA5

10

15
1

5
61 VGA-SDA-EDID-HDMI 12
B06N SERIAL FLASH 7CT3
B03A 62 15

6
M25P05-AVMN6 VGA-SCL-EDID-HDMI

11
HOTEL TV ONLY
RES
VGA
FLASH 6 SFB-CLK
7CS1 CONNECTOR
TS 11 14
3 SFB-WPn TSB ST232C
128kx8 1 SFBI-CS MCU
5 SFB-SI LEVEL B06Q CONTROL +3V3 B01C DVBS B02A TUNER B02B DVBS-FE B06M FE B02A TUNER
SHIFTER SUPPLY CHANNEL DECODER CHANNEL DECODER
2 SFB-SDO
12 13
STANDBY
SW

3CR6
3CR7
1FA0
AA28 SCL-M1 3CWJ cFS1 1
SCL-FE SCL-TUNER
DEBUG
AA27 SDA-M1 3CWF SDA-FE cFS2 SDA-TUNER 3 ONLY
RES

3UPD
3UPB

3KC2

3KC3

3RA7

3RA8
ERR B04A CONTROL B04B V-BY-ONE OUT
18 +3V3
1CV1 7 8 20 21 97 98

5FA6

5FA7
1
DEBUG 7UP2 7KC0 7RA1 19 SCLT
3GM6
3GM5

3 ONLY LNBH25 CXD2834 STV0903

1G55 18 SDAT
3CVF 9GM2 3GVD 2 DVB-S DVB-T2 DVB-S
E2 SCL-M2 SCL-BE SCL-DISP

3FA2

3FA1
TO DISPLAY CHANNEL CHANNEL CHANNEL
3CVG SDA-BE 9GM1 SDA-DISP 3GVE 1 PANEL DECODER DECODER DECODER
D1 SDA-M2
12 13 10 11
+3V3
1CWA
ERR ERR ERR
ERR
1 31 27 28 7RA0 1F00
14 1 2 STV6110 SUT-RE214Z
3GM2

3GM1

3GM4

3GM3

DEBUG
3 ONLY
7GM1 5 SATELLITE TUNER
PCA9540B TUNER
4 RES
2 CHAN. ERR
MULTIPLEX. 34
ERR
8 1CWB B04D CONNECTOR - BACKLIGHT 36
1
7 DEBUG
3 ONLY
RES
RES 1G53 B06Q CONTROL B01F MISCELLANEOUS B06Q CONTROL 1CWD
+3V3-STANDBY 1
9GM4 3GD2 3
SCL-BL DEBUG
TO DISPLAY 3 ONLY
9GM3 SDA-BL 3GD1 2 PANEL

3CR6
3CR7

3CYU

3CYV
7CY1 1C21
EF 3CYN 16
1 LED1
3CU8 3CYS
P26 STB-SCL SCLMC 6 7CY6 TO
PCA9633 LIGHT SENSOR
P27 STB-SDA 3CU9 3CYR
SDA-MC 7 PWM 7CY2 TOUCH CONTROL
EF 3CYC 3
2 LED2

RES

19210_001_120313.eps
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 Block Diagrams QFU1.1E LA 9. EN 69

9.15 Supply Lines Overview

SUPPLY LINES OVERVIEW
B04B V-BY-ONE OUT
B01A CONNECTORS AND PROTECTIONS B01D POWER SEQUENCING
B06D SERVICE B06R TEMP-SENSOR
6UAF +3V3-WIFI +3V3 +3V3
B07c +12V +12V B06h
1M95 B01a +3V3 +3V3
1M95 B06h +3V3 +3V3
+3V3-STANDBY B01d,B01f, +3V3-STANDBY +3V3-STANDBY B06h
1 1 B01a +VDISP +VDISP
B03f,B04a, B04c
2 2 STANDBYn B05a,B06a, +2V5 +2V5
B06Q B06h
3 3 B06n,B06q, +3V3 +3V3 B06E ETHERNET
4 4 B06s,B07b B06h
B04C OUTPUT - VDISP +3V3-LAN 5EF4 VDD33-PHY
B06S STRAP-OPTIONS
5 5 +12V ENABLE-3V3 B07c
B01c,B01d,
+3V3-STANDBY +3V3-STANDBY
6 6 B01f,B04c +3V3 +3V3 7EF0 B01a
CONTROL ENABLE-2V5 B06h
1UA0 +12Va AR8030 3
B01b +2V5 +2V5

PSU B06h 8,27 VDDH-2V5

T 3.0A ENABLE-1V5-1V1

7 7 +12V 1GS1 +VDISP

ETHERNET
AVDDL-1V1
B07A LPC-DEBUG
1UA1 +12Vb B01a 7GS2 B04b 6,11,17
B04h,B06h, 1NA2 7NA0
8 8
T 3.0A B07a B01F MISCELLANEOUS T 3.0A 1 +5V-LPC VOLT. +3V3-LPC
9 9
+12V-AUDIO +3V3-STANDBY +3V3-STANDBY REG.
10 10 B05a B01a 5J20 +3V3-LPC-ANA
+5V +5V 7GS3
11 11 BL-DIM
B04A B06h
LCD-PWR-ONn B06F NANDFLASH + EEPROM
+12Vb +12Vb
12 12 BL-DIM1 +3V3 +3V3 B01a
B07F B06h
13 13 BL-I-CTRL +3V3 +3V3
B07E B06h
RES

5TA1
14 14 POWER-OK
B04A
+12V 5TA2 1TA1
1T71
4
TEMP B04D MISCELLANEOUS
B01a SENSOR
T 1.0A
(OPTIONAL)
+3V3 1GD1
1G53
9 BACK
B07B HEADPHONE

RES
B06h
LIGHT
B06H DC-DC
+3V3-STANDBY +3V3-STANDBY
1M99 1M99 T 1.0A B01a
1 1 +12Vb +12Vb
B01a
1UA2 AMBI-POWER 7UW0 +3V3 +3V3
2 2 +12V-AL B07h B06h
3 3 T 2.0A
B02A TUNER-CHANNEL DECODER
B05A CLASS-D AMPLIFIER
TPS54426
B01c,B01f,
4 4 GND-AL 7FA0 5UW0 13 SYNCHRONOUS 10 5UB2 +5V B02a,B02b,
2-SIDED +5V 5FA0 +VCC-TUNER
5 B06h STEP DOWN 11 B06a,B06b,
5 AMBILIGHT IN OUT +3V3-STANDBY +3V3-STANDBY 14
COM B01a CONVERTER B06c,B06p,
6 6 +12V B07c,B07d
7UAC 7
7 7 +3V3 5KC6 +3V3-DVBT2-D +3V3 5D85 +3V3D
B06h B06h
8 8 DETECT12V
B01a,B01d,B01f,
+1V2-FE 5KC7 +1V2-DVBT2-C +12V-AUDIO +12V-AUDIO 7UW1 B02a,B02b,B03f,
B06a B01a TPS54426
3-SIDED B04a,B04b,B04c,
AMBILIGHT B04d,B05a,B06a,
3KCE 5UW3 13 SYNCHRONOUS 10 5UB4 +3V3
+1V2-DVBT2-P B06b,B06c,B06d,
STEP DOWN 11
14
B05B ANALOGUE EXTERNALS CONVERTER B06f,B06i,B06k,
B06m,B06p,B06q,
1VA5 7
+3V3 +3V3 +5V-VGA B06r,B07b,B07c,
B06h VGA 9 B06a ENABLE+3V3
7UAE
B02B DVBS-FE CONNECTOR
B07d,B07e,B07g
7RC1
RT9715
B06h
+5V 5RC0 +3V3-DVBS 7UW2 B07C USB INTERN
IN OUT RT9025 7EH4
5 HIGH SIDE 1 +3V3-AL B07h COM TPS61200
POWER LOW +2V5 B01d,B03f,
SWITCH
5RA0 +3V3-DEMOD B06A HDMI 3
DROP OUT
6
B04c 5 LOW 2 +3V3-LAN B06e
4 +3V3 +3V3 CONVERTER DROP OUT
5RA1 +3V3RF B06h CONVERTER
ENABLE-3V3-AMBI 2
7RC0 5HA5 VDD33 +2V5-F 6
+3V3 +2V5-DVBS B03f
B06h IN OUT
B01c ENABLE+2V5
5HA6 EPWR33 ENABLE-WOLAN
COM
+3V3-WIFI +3V3-WIFI
B01B FUSION SUPPLY
+1V0-DVBS +1V0-DVBS +1V5 +1V5 B04H SECOND SOURCE B01a
B01c B01b DC-DC CONVERTERS +3V3 +3V3
+12Va +12Va +12Vb +12Vb B06h
B01a 7HA1 B01a
7UB5 +V-LNB +V-LNB RT9025 7URA +5V +5V
B01a B06h
TPS54429 LOW +1V2-FE RT8288
3 6 B02a
DROP OUT
5UB5 13 SYNCHRONOUS 10 5UB7 +1V5 5UR1 1 SYNCHRONOUS 2,3 +5V
B03f,B06a CONVERTER
STEP DOWN 11 5HA2 VDD12 BUCK
14
CONVERTER B03B FUSION UMAC CONTROLLER CONVERTER B07D CI
7 5HA3 TVDD12 5
+1V5-M0 +1V5-M0 +3V3 +3V3
B03f 5HA4 B06h
ENABLE+1V5+1V1 AVDD12 DETECT12V
+1V5-M1 +1V5-M1 +5V +5V
5U02 B03f 7UR6 B06h
+3V3-STANDBY +3V3-STANDBY
B01a RT8293 3PA1 +5VCA
7UC0
7UC2 +5V-VGA +5V-VGA 5UR5 2 SYNCHRONOUS 1,2 +3V3 +T
RT8228 5
B05b BUCK
3 5UC0 B03C UMAC 1 DDR3
CONVERTER
Synchronous
7UC3
+1V1-FD
B03f B03f
+1V5-M1 +1V5-M1
+5V-EDID 7 B07E FPGA - POWER & CONTROL
Buck PWM 5UC2

6HA0
Controller 3J11 ENABLE+3V3 +3V3 +3V3
DDR-MVREF11 +5V +5V B06h
1 B06h RES
3J14 DDR-MVREF12 5GG1 VAUX
3HAS SBVCC5 B07f
8 7GG6
B06I DC-DC
7UV1 VCCINT
ENABLE+1V5+1V1 1P04 IN OUT B07f
HDMI 5 EIN-5V RT9025 COM
3UD2 18
+Vb
B03D UMAC 0 DDR3 CONNECTOR
B06h
+3V3 1 LOW 5 +1V1-FA
B03f 5GG2 VCCO3
B07f
1P03 DROP OUT
7UC7 +1V5-M0 +1V5-M0 HDMI 4 DIN-5V CONVERTER
7UC4 7UC8 B03f 18 5GG3 VCCO2
CONNECTOR B07f
3J2V DDR-MVREF01 7UV0
+1V2-MIPS 1P02 VOLT. +1V2-FA 5GG4 VCCO1
B03f 3J30 HDMI 3 CIN-5V B03f B07f
DDR-MVREF02 18 REG.
CONNECTOR
5GG5 VCCO0
B07f
ENABLE+1V5+1V1 1P05
HDMI 2 BIN-5V
18
CONNECTOR
B06K AUDIO

B01C DVBS-SUPPLY 1P05 B07F FPGA - I/O BANKS

HDMI 1 AIN-5V +3V3 +3V3
18 B06h
+5V +5V B03F FUSION POWER SUPPLY CONNECTOR
B07e
VAUX VAUX
B06h
+2V5-DVBS +2V5-DVBS +3V3 +3V3 VCCINT VCCINT
B02b B06h B07e

B01a
+3V3-STANDBY +3V3-STANDBY B06M FE
B07e
VCCO3 VCC03
+12V 1UP1 +12V-DVBS +2V5 +2V5
B06B HDMI-ARC
B01a B06h +3V3 +3V3 VCCO2 VCCO2
B06h B07e
T 3.0A +5V 5HD5 +5V-ARC
+2V5-F +2V5-F B06h
B06h VCCO1 VCCO1
B07e
+1V5 +1V5 +3V3 5HD6 +3V3-ARC
7UP1 B01b B06h VCCO0 VCCO0
B07e
TPS54227 5J0P +1V5-M0
B03b,B03d B06N PNX85500: STANDBY CONTROLLER
5UP1 8 SYNCHRONOUS 6 5UP2 +1V0-DVBS 5J0R
B02b +1V5-M1 +3V3-STANDBY +3V3-STANDBY
STEP DOWN B03b,B03c
B01a
CONVERTER
B01b
+1V2-MIPS +1V2-MIPS B06C USB B07G CPLD
7UP2 +3V3 +3V3
+1V2-FA +1V2-FA B06h +3V3 +3V3
LNBH25PQ B06i B06h
+5V +5V B06P HDMI
5GC1 VINT
+1V1-FA +1V1-FA B06h
5UP6 17 LNB 20 +V-LNB B06i 1E03
B02b 3EA7 +5V-PORTA +3V3 +3V3
CONTROLLER 9 B06h
+1V1-FD +1V1-FD 5GC2 VID
B01b +T
+5V +5V RES
B06h
1E02
3EAC +5V-PORTB 9
+T B07H AMBILIGHT
B04A CONTROL
3ECH
1E01 B06Q CONTROL
+3V3AL +3V3AL
+3V3 +3V3 +5V-HDD 9 B01a
B06h +3V3-STANDBY +3V3-STANDBY
+T B01a
+3V3-STANDBY +3V3-STANDBY AMBI-POWER AMBI-POWER
B01a B01a
+3V3 +3V3
B06h

19210_061_120426.eps
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 70

10. Circuit Diagrams and PWB Layouts

10.1 B 310431365554
10-1-1 B01A, Connectors and protections

Connectors and protections

B01A B01A
+12V

6UAF
+3V3-WIFI +3V3-STANDBY 9UA1-1 RES +3V3-WIFI
9UA1-2 RES

4K7
B230LA-M3 3UAJ
2UA9 RES 9UA1-3 RES
9UA1-4 RES +12V
FUAS DETECT12Vn
6.3V 330u
2UA0 RES 2UAV
3
1UA2
1u0 330u 6.3V +12VAL AMBI-POWER 3UAH-1
1M95 1 8 5 7UA1-2
T 2.0A 63V
BC847BS(COL)

2
FUA0 +3V3-STANDBY 7UA0-2 22K

3UAF-2
1 3UA0 FOR DUAL SIDE AL ONLY
FUA1 4

10K
STANDBY BC847BPN(COL)
2

6
FUA2 4

3UAH-3
3 100R

2UA1 RES
IUAA

22K
FUA3

7
4
FUA4 5

10n
5 +12V

3
FUA5 3

3
3UAF-3
2UA3 RES
6

PDZ6.2B(COL)

10K
7 FUA6 +12V-AUDIO IUAF

2UA2

100n
FUA7

1u0
8

6UAA

8
16V

FUAL

3UAF-1
9
2UAT

2UA4

100p

10K
10 IUAC
FUA8
100u

11 6

7
FUA9 7UA0-1

1
3UAH-2
12 IUAB FUAN
FUAA

22K
BC847BPN(COL) DETECT12V
13 2
FUAB
14
1

2
3UA1

3UAE

1u0 RES
1-2041145-4

1K0
BL-ON IUAD

5
2UAJ
3UAA 100R

3UAH-4
3UAG

4K7

22K
BL-DIM1
IUAE
3UA2 100R
BL-DIM

4
3UA3 100R
BL-I-CTRL
3UAD 3UAF-4
6
IUAG +12V DETECTION
3UA4 100R +3V3-STANDBY
5 4
POWER-OK 3K3 10K
100R 7UA1-1 2
BC847BS(COL)
2UA8

1
10n
2UA5

2UA6

2UA7
100p
10n

1n0

OPTIONAL
*
INSTEAD 1M99 1UA0 IUA0
+12Va
1M11
1
* T 3.0A 32V

2 +12V
3 +12VAL
4 +12VAL 1UA1 IUA1
+12Vb +22V
+12VAL +12VAL

RES 3 3UAN-3 6

RES 1 3UAP-1 8

RES 2 3UAP-2 7

RES 3 3UAP-3 6

5
2041145-4

RES 3UAN-1

RES 3UAN-2

RES 3UAN-4

RES 3UAP-4
GND-AL T 3.0A 32V

4K7

4K7

4K7

4K7

4K7

4K7

4K7

4K7
1
+12VAL

4
K
TS2431

3UAV-2
2UAB RES

7UAF

10K
R
AMBI-POWER
2UAA

100n

1M99 2
1u0

A
1

3UAR

2UAK
IUAL

390R

100p
FUAH

RES
2
FUAJ

3
3 +12VAL
4 GND-AL
5 RES 1 4 FUAP
6 3UA5 IUAK 2UAN
BC857BS(COL) BC857BS(COL)
7 7UAA-1 7UAA-2
FUAK +12V 2 5
8 1K5 100p

3UAT-3

3UAT-4
2UAU RES

2UAM
3UA6
2041145-8 IUAJ 3

2K2

2K2

2K2
1u0
6
IUAV
100n

3UAV-1

3UAW
RES

0R1
10K
3UAV-4

3UAT-1
10K

2K2
+3V3-STANDBY +3V3 3UAY IUAN
RES GND-AL
100R

5
6
7
8
IUAP
7UAC
4 SI4778DY-GE3

3UAV-3
3UA7

10K

10K

PDZ15B(COL) PDZ15B(COL)

1
2
3
IUAM 7UA2 3

3UAT-2
3UA8

6UAC
RES 9UA0 PMV31XN

2K2
IUAR 6UAB
1 7UAB FUAT AMBI-POWER
100K
BC847BW
S1D
2 IUAS
3UA9
STANDBYn 7UA3
3UAM DBG
2UAD

3UAC
3UAB

3UAS

2UAL
220K
100n

100p
BC847BW

RES
1R0

10K
10K

LTST-C190KGKT

6UAD
3UAK

DBG
330R
10K
RES

7UAE

6UAE
5UAA
RT9715EGB
IUAT 3u0
STANDBY +3V3 5 3
VIN FLG

2UAP

1u0
FUAR
ENABLE-3V3-AMBI 4 1 +3V3AL
EN VOUT
EN
AMBILIGHT 3-SIDED PROTECTION
2UAR

2UAS
GND
10u

10u GND-AL
2

1X03 1X05 1X00

EMC HOLE REF EMC HOLE EMC HOLE

6 2011-12-16

Connectors and protections

8204 000 9215

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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 71

10-1-2 B01B, Fusion supply

Fusion supply
B01B +Vb
B01B

8
5 7UC8-2 +1V5
LM8337
6
+12Va

4
GND-1V2

2UCS

10u
GND-1V2

8
3 7UC8-1 7UC7
LM8331 3UD0

1 3UCT-1 8
PHD38N02LT
IUCG

2 3UCH-2 7

4 3UCH-4 5
100K
2

3UCH-1

3UCH-3
IUCH 10R IUCK

3UCW

3UCY

3UCZ

3UC6

2UC2
220K

680K

100n
4K7

4K7

4K7

4K7

22K

22K

4
7UC6-1
BC847BS(COL)

3
GND-1V2
7UC6-2 6
BC847BS(COL)
IUCF GND-1V2 GND-1V2
3 2
GND-1V2 GND-1V2
IUCD
ENABLE+1V5+1V1 4 3UCT-4 5 5 1
2UC3
100K IUCL

2UCT RES
4
330p

1n0
3UD1 2UC4

1
GND-1V2
4K7 IUCJ 1n0

K
TS2431
7UC4

R
+12Va +5V 2

3A
3UD2

9UC1
RES
22R
3UCJ FUC3
+1V2-MIPS
12K 1%
FUC2 GND-1V2 3UCM IUCE 2UCV

2UCG

1u0
2K2 1n0
2UCU
RES RES

1u0
GND-1V2
cUP9

+Vb GND-1V2

7UC5
RT9194GE CORE VOLTAGE SUPPLY MIPS FUSION
6

RES VCC
5
DRI
1 3
EN FB

100K 1%

33K 1%
4 IUCC
PGOOD

RES 3UCK
3UC4

3UC5

RES 3UCL
270K
1M0
GND
2

DVS2
IUCM 47K 1%
3UCS

3UCV

1M0
5UC1 IUC0
+12Va
30R

2UCC
2UCA

2UCB
22u

22u

22u

5
6
7
8
IUC1 IUC2 7UC2
3UC0 4 SI4778DY-GE3

1
2
3
10R

3UC1
+5V

3R3
3UC2 RES

2K2
2UCD

9UC0
7UC1 IUC3
BC847BW
220p
RES

PDZ5.6B(COL)
IUC4
5UB5 IUBA IUBB 5UB7 FUB5

RES 6UC1
+12Va +1V5

1 3UC3-1 8

2 3UC3-2 7

3 3UC3-3 6

4 3UC3-4 5
B340A-M3
6UC2
30R 2u0

2UCP
2UBN RES
2UBK

5
6
7
8
100n

10R

10R

10R

10R
10u
2UBM

2UBP

2UBT
2UBL

7UC3
10u

10u

22u

22u

22u

IUC5
4 SI4172DY-GE3

270K 5%
7UB5

1
2
3
2UCE

3UC7
TPS54429PWP

10u
7UC0 2UCF
RT8228BGQW 5 2UC1
13 10
VIN1 SW1
11 VCC IUCB
SW2 IUC6 2UCH IUC7 3UC8 1n0 1n0
14 IUBE 4 5UC2
VIN2 2UBV BOOT
12 IUCP
VBST 100n 3R3
1 IUBF 11 3
+1V5 VO 100n TON UGATE 2u0
IUBC 6 3UC9 DBG 6UC0 DBG IUCN
3UB6 PG IUC8 5UC0 FUC0
2 +5V 9 2
VFB IUBG 3UB7 RES PGOOD PHASE +1V1-FD
22K 1% IUBD 3 2K2
VREG5 IUCA 2u0

2UCJ RES

2UCK RES

220u 2.5V
4 100K LTST-C190CKT 10 1
2UBW RES SS CS LGATE
470K RES

2UCW

2UCY
2UCL
16

22u

22u

22u

22u
22K 1%

2UC0

7 17 8 6
1u0

22p EN ENABLE+1V5+1V1 EN FB
2UBY
3UB8

3UB9

18
3n3

RES
2UBS

1%
RES

19 7
1n0

MODE
2UCR RES

20 3UCA

150K
21 GND GND_HS
VIA

12

13
22
1n0

23
24 GND-1V1F
GND-1V5 GND-1V5
25
GND-1V5 GND-1V5 26
DDR3 SUPPLY FUSION CORE VOLTAGE SUPPLY FUSION
GND PGND GND_HS GND-1V1F GND-1V1F
5

8
9

15

GND-1V1F RES 2UCM

22p
GND-1V5 3UCG IUC9 3UCB 3UCC
DVS1 SENSE+1V1-FD
ENABLE+1V5+1V1 180K 1% 22K 1% 10R

120K 1%
3UCR RES
12K 1%

22K 1%
3UCD RES
3UCN +1V1-FD
3UCP

3UCE

3UCF
1M0
10R
220K 1% 2UCN

6 2011-12-16
1u0
Fusion supply
GND-1V1F GND-1V1F GND-1V1F 8204 000 9215

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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 72

10-1-3 B01C, DVBS supply

DVBS supply
B01C 5UP1 IUP1
B01C
+12V-DVBS
30R
7UP1

2UP0

2UP1

2UP2

100n
TPS54227DDA

10u

10u

8
VIN

STEP DOWN IUP6 2UP4
2 7
VFB VBST 5UP2 IUP9
100n +1V0-DVBS
4 6 IUP3
SS SW 3u0

2UP6 RES
2UP5
1

22u

22u
+2V5-DVBS EN
3 IUP7
VREG5
IUPG 3UP1 RES
VIA

2UP7
GND_HS GND

1u0
68K

10
11
3UP2 RES

1n0
8K2 1%

RES 2UP8

2UP9

10n
IUP8 2UPA RES

22p

1%
2UPB RES FUP1

470K

3UP4
RES 3UP5

22K
GND-1V0 GND-1V0 22p
3UP6
SENSE+1V0-DVBS
8K2 1%
GND-1V0 GND-1V0 3UP7

68K
CORE VOLTAGE SUPPLY FOR DVBS DEMODULATOR

cUP1
+12V +12V-DVBS
1UP1 GND-1V0

T 3.0A 32V

+12V-DVBS

2UPL RES

5UP6
100n

30R
IUPJ

10u 25V
RES 2UPM
2UPC

2UPD

2UPE
100n

10u

10u

5UP5

10u
7UP2
17

LNBH25PQ
VCC
IUP4 +V-LNB
LX
3
IUPF 2UPJ
16
VBYP
470n

B230LA-M3
21
VUP

RS1D
6UP6

6UP5
6
ADDR FUPA
20 +V-LNB
3UPB VOUT
SCL-FE 7
SCL

B230LA-M3
47R 1 IUPE
3UPD
2UPK

6UP4
220n
SDA-FE 8 DSQ 5
SDA
47R 10
19 11

47u 25V

47u 25V
DETIN

2UPG
2UPH
2UPF
NC 12

1u0
F22-DISECQ-TX 22 13
IN
DEBUG DEBUG 23 14
OUT
6UP1 24
3UP3
+5V 2 26
FLT
27
1K0 LTST-C190KGKT 18 28
BPSW
IUP2 29
3UPE 9 VIA 30
ISEL
22K
31 LNB SUPPLY
32
GND_HS

33
PGND
GND
15

25

6 2011-12-16

DVBS supply
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 73

10-1-4 B01D, Power sequencing

Power sequencing
B01D B01D
3UF1 IUF8 3UFF
+12V
100K +5V 12K
IUF2 +12V
3UG2-4
+3V3 ENABLE+2V5
22K

1 3UF7-1 8
IUF7 4 7UF3-2

RES 3UF2
7 3UF7-2 2

2UF5

100K

100K
100n
BC847BPN(COL)
5
100K
3UFA 3

2UF2

1u0
IUFG ENABLE+1V5+1V1
100K RES

4 3UF7-4 5

6 3UF7-3 3
3

RES 3UFG
2UF4
100K

100K

47K
7UF8-2

10n
RES IUFS
6 5
BC847BS(COL)
2 7UF3-1 4
+2V5 BC847BPN(COL)
IUFA
1

+2V5
100R RES

100R RES

100R RES

100R RES
1 3UFV-1 8

2 3UFV-2 7

3 3UFV-3 6

4 3UFV-4 5

+12V

DETECT12Vn

3UG0-3

3UG0-1
22K

22K
ENABLE+1V5+1V1
IUF0
IUF1
ENABLE+3V3
4
+12V +3V3-STANDBY BC847BPN(COL)
5 7UF7-2
+12V
3 IUF5

3UG2-2

3UG2-3
IUF6

22K

22K
6
IUFR
3UG1-4

3UGB
IUFC

100K
7UF8-1 2

3UG0-2
BC847BS(COL)

22K
22K
1
4 4
IUFD IUFE 3UG0-4
BC847BPN(COL) BC847BPN(COL)
7UF5-2 5 7UF6-2 5
IUFP 22K
6
ENABLE+3V3 3 3
IUF3 3UG1-3

3UGC

120K
7UF7-1 2 DETECT12V
3UGF IUFJ BC847BPN(COL)
ENABLE+2V5

3UG1-1

3UG1-2
22K
1

22K

22K
100R
6
IUFN
2 3UG2-1 IUFK
7UF5-1
BC847BPN(COL)
22K
1
IUFL 6

2 IUFM
7UF6-1
BC847BPN(COL)
1

2UF9

100n
3UGE

3K3

6 2011-12-16

Power sequencing
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 74

10-1-5 B01E, -

-
B01E B01E

intentionally blank

6 2011-12-16

-
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 75

10-1-6 B01E, Miscellaneous

Miscellaneous
B01F B01F
1M54
FGY2 RES
1
FGY3 3GY3 BL-DIM1 1T71
2 FTA1 3TA1 FTA2
FGY4 100R 3GY7 BL-DIM2 SCL-SRF
3 1
FGY5 3GY8 100R BL-DIM3 RES 10R
4 FTA3 3TA2 FTA4 2
FGY6 100R 3GY9 BL-DIM4 SDA-SRF FTA6
5 3
FGY7 3GYA 100R BL-DIM5 RES 10R
6 4
FGY8 100R 3GYB BL-DIM6
7

RES 2TA1

RES 2TA2
FGY9 3GYC 100R

10p

10p
8 BL-DIM7
FGYA 100R 3GYD BL-DIM8 502386-0470
9
100R
2041145-9 TEMPERATURE
1n0

1n0

1n0

1n0

1n0

1n0

1n0

1n0
SENSOR

2GYG
2GYC

2GYD

2GYH
RES 5TA1
2GYB

2GYE

2GYF

2GYJ
+3V3 FTA5
30R

RES 2TA3

1u0
T 1.0A 63V
RES
1TA1
+3V3-STANDBY

RES 5TA2
+12V ITA1
30R

RES 2CYK

100n
7CY6
PCA9633TKRES

8
VDD
LED1 1
LED0 SCL
6 3CYS RES SCL-MC
47R
LED2 2 7 3CYR RES SDA-MC
LED1 SDA
47R
3 10
LED2
11
+3V3-STANDBY +5V 4 VIA 12

GND_HS
LED3
13

VSS
3CY1 RES

5
3CY2
10K

10K

ICY1
9CY1 RES LED1-OUT
LED1 3CYU SCL-MC
ICY2 47R
3CY3 3CY4 3CYV
LED1 LED1 LED2 SDA-MC
47R
10K 10K
7CY1
BC847BW

+3V3-STANDBY +3V3
+3V3-STANDBY
+3V3
3CY5 RES

3CY6 RES

2CY1

1u0
3CY7 RES
10K

10K

100K

ICY3
9CY2 LED2-OUT

3CY8 RES 3CY9 ICY4

LED2 LED2 1C21 1C20
3CYA FCY1
10K 10K LIGHT-SENSOR 1 1
3D-LED_3D-RF FTA7 3CYB 100R FCY2 2
7CY2 2
BC847BW LED2-OUT 100R 3CYC FCY3 3 3
RES ICY6 100R 4 FCY4
KEYBOARD_IRQ-SRFn 3CYD 4
KEYBOARD_IRQ-SRFn FCY5 5 5
10R +3V3-STANDBY 6
6
RC_IRQ-RF4CEn 3CYE FCY6 7 7
9CY3
RES

100R +5V 3CYF 8 8

+T 0R4 9 9
3CYG
SCL-SRF RES FCY7 10
ICY7 10
SDA-SRF 3CYH RES 10R FCY8 11 11
IRQ-SRFn IRQ-SRFn 10R RES 3CYJ FCY9 12 12 13
TXD-RF4CE 3CYK 100R FCYA 13
10R +5V 3CYL RES 14 FH52-11S-0.5SH
RXD-RF4CE 3CYM FCYB 1R0 15
LED1-OUT 3CYN 10R FCYC 16
SPEAKER-DETECTn 100R 3CYP RES FCYD 17
RESET-RF4CEn 3CYT 100R FCYE 18
100R 19 20
RES

RES

2CY7 RES
RES

FH52-18S-0.5SH

2CYC

2CYD
2CYA

2CYB

2CYE

2CYF
RES 2CY2

2CYL

2CY3

2CY4

2CY5

2CY6

2CY8

2CY9
100n

100p

100p

100p

100p

100p

100p

100p
47n

10p

10p

10p

10p

10p

1u0
6 2011-12-16

Miscellaneous
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 76

10-1-7 B02A, Tuner channel decoder

Tuner channel decoder

B02A VCC-TUNER B02A
3FA0 IFA1

0R1

5FA1

2FA5

2FA6
30R

22u

22u
2 3 2 3

2FA7

2FA8

100n
10p
1FA1 1 1 1FA2
U.FL-R-SMT-1(10) U.FL-R-SMT-1(10) 1F00
SUT-RE214Z

15

14
FFA9 1
3KA0 5KC8 A3.3V
IF-N-DVBT2 AFA5 2
IF1_P
IF-P-DVBT2 47R 3KA1 330n 5KC9 AFA4 3
IF1_N
330n FFA8 4
47R 2FAJ AGC1

TUNER
9FA1 9FA0 5
10p 2FAK NC1
7FA0 6
5FA4 NC2
LD1117DT33 SOC-IF-N 3FA3 AFA2 AFA0 10p 7
IF2_P
5FA0 IFA0 SOC-IF-P 47R 3FA4 AFA3 330n 5FA5 AFA1 8
FFA0 IF2_N
+5V 3 2 VCC-TUNER 47R 5FA6 330n FFA4 9
IN OUT FFA7 FFA3 AGC2
SCL-TUNER 3FA2 2FA9 10p 10
30R 330u 6.3V I2C_SCL
COM SDA-TUNER FFA6 5FA7 30R 3FA1 100R 11
I2C_SDA
2FA0

2FA1

2FA2

2FA4
100n
2FAA 10p

10u

1n0
RES 30R 100R FFA2

12

13

16
1

2FAG
2FAC

2FAH
2FAB

10p

10p

10p

10p
FFA1 1FA0 DBG FFAA
1
2
3
5 4

BM03B-SRSS-TBT 3KA3
IF-AGC
100R

3KCC
2FAF

22K
10p
RES 3KA4 FFA5 3FA7
IF-AGC FFAB
100R 100R
SOC-IF-AGC

2FAD

3FAD

2FAE
RES 3KA2

RES 3FA8
6K8

6K8

22K
22n

10p
IFA6

T2-AGC FFAC

3FA9

2K7
+1V2-DVBT2-C +1V2-DVBT2-P 7KA0
PDTA114EU
RES
+3V3-DVBT2-D
VCC-TUNER
2KC4
2KC7

2KC6

2KC5

2KC0

100n

6 IFA3 3
100n
100n
100n

100n
100n

7FA1-1 2 5 7FA1-2
2KC3

2KC2

2KC1
100n

100n

BC857BS(COL) BC857BS(COL)
1 4
4 9RC2-4 5 TS-INT-CLK
1 9RC2-1 8 TS-INT-VALID IFA5 IFA4
2 9RC2-2 7 TS-INT-SOP
3 9RC2-3 6 TS-INT-DATA

3FAC
3FAA

3FAB
470R

470R
10K
2KCC

2KCB
12p

12p

7KC0 RES 2KCK

10
22
28
44

19
42

32

CXD2834ER
7

41M PVDD
2
4

IKC0 CVDD DVDD 3KC1 6p8 VCC-TUNER

3 1 35 5 TS-CHDEC-CLK
XTALI TSCLK
5KC0 4 47R 8 1 3KC0-1 TS-CHDEC-VALID
1KC0 3KC4 IKC1 TSVALID
34 3 7 2 3KC0-2 47R TS-CHDEC-SOP
XTALO TSSYNC
1K0 47R
4u7 2KCD
8 6 3 3KC0-3 TS-CHDEC-DATA
2KCE IKC2 3KCA 0
IF-P-DVBT2 9KC0 10p 38 9 47R
100n TAINP 1
IF-N-DVBT2 9KC1 2KCF 47R 3KCB 37 12
TAINM 2
100n 2KCG IKC3 13
10p 47R 3
5KC1 TSDATA 14
4

T2-AGC 4u7
3KC6
41
RFAIN I2C 5
15
16
5KC5 IKC7 5KC7 IKC8
6 VCC-TUNER +3V3-DVBT2-D +1V2-FE +1V2-DVBT2-C
1K0 ADDRESS 7
17
30R 30R
2KCH

1
10n

DKC0 GPIO0 = 3KC2 5KC6

2KCR
47 20

1u0
GPIO1 SCL SCL-FE +3V3
2 21 47R 3KC3 SDA-FE
IKC4 GPIO2 0XD8 SDA
47R
30R

2KCP
50

1u0
3KC7 48 51
IF-AGC TIFAGC
2KCJ 52
10K
100n 53
3KC8 IKC5 46 54
+3V3-DVBT2-D TTUSCL 3KCE IKC9
3K3 3KC9 IKC6 45 55 +1V2-DVBT2-C +1V2-DVBT2-P
TTUSDA
3K3 56 22R
57

2KCS
24 58

10u
TESTMODE
59
60
25 61
SLVADR0
VIA 62
63 Position Nr FUSION TV550-R4
26 64
DKC1 OSCEN_X
65 3FA7 - 100R
66
RESET-FUSION-OUTn 29 67 3FA9 2K7 -
RST_X
68
69
3FAA 470R -
30 70
SLVADR3
71
3FAB 10K -
72
33
NC1
73
3FAC 470R -
40 74
NC2
VSS 3FAD 2K7 22K
GND_HS
6
11
18
23
27
31
36
39
43

49

2FAD 100nF 22nF

FKC1 _
7FA1 BC857BS 5 2011-12-06

Tuner channel decoder

8204 000 9218

19210_011_120424.eps
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2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 77

10-1-8 B02B, DVBS Front-end

DVBS Front-end
B02B B02B
7RA1-1
STV0903BAC
7RA1-2
STV0903BAC

+3V3-DVBS
5RA0 IRA8
+3V3-DEMOD
+1V0-DVBS
15 1
XTAL 122
XTALI MAIN VS
52 SENSE+1V0-DVBS

17 POWER_VIA 4 124 16
3RA2 FRA7
AGC
30R NC XTALO AGCRF1

RES 2RCA
22 6

2p2
1K0
I2C-ADDRESS : D0 2RC9 RES

2RCD

2RCC
2RCE
2RAY

2RA0

2RA1

2RA2

2RA3

2RA4
2RB0

100n

100n

100n
25 10 59 63

22u

22u

22u

22u

10n

10n
RES DIRCLK 0 NC
47n
28 14 104 64 47p TS-INT-DATA
GNDA CLKI 1 NC
RES 31 113 103 65 TS-INT-CLK
NC CLKI2 2 NC
33 117 100 67 TS-INT-SOP
NC CLKOUT27 3 NC
36 121 D 68 TS-INT-VALID
4 NC
39 125 QM 11 70
N 5 NC
42 QP 12 I1 71
P 6 NC
45 129 73 3RA0-3 3 6 TS-DVBS-DATA
GND_HS 7
+1V0-DVBS 48 74 3RA1 47R TS-DVBS-CLK
CLKOUT
5RA1 IRA7 51 130 75 3RA0-2 2 7 47R TS-DVBS-SOP
STROUT
+3V3-DVBS +3V3RF 53 131 IM 8 78 3RA0-1 1 8 47R TS-DVBS-VALID
N DPN

2RAA
2RA5

2RA6

2RA7

2RA8

2RA9
100n

100n

100n
57 132 7 Q1 79 47R

10n

10n

10n
30R VDD1V0 IP P ERROR NC
2RBK 61 133
2RBL

66 134 82
22u

10n
NC

RES 2RB1
69 135 83

6p8
NC
72 136 60 84
0 NC
77 137 56 CS 86
1 NC
+1V0-DVBS 81 138 87 NC
85 139 128 89
DISEQCIN1 NC
88 140 F22-DISECQ-TX 20 90 NC
DISEQCOUT1

2RAG
2RAC

2RAD
2RAB

2RAE

2RAF
100n

100n

100n
93 141 126 91

10n

10n

22u
NC FSKRX_IN NC
99 142 NC
107 94
FSKRX_OUT NC
102 143 NC 95
3RA7 IRA0 NC
Diversity Matrix (Satellite Tuner dependant) 105
110
144
145
SCL-FE
SDA-FE 47R 47R
97
98
SCL
108
109
NC
SDA NC
112 146 111 NC
3RA8 IRA1
147 SCLT 19 115
SCLT NC
Position Nr Affected Pin Default Value STV6110 STV6111 +3V3-DEMOD 21 VIA 148 SDAT 18
SDAT
1 116 NC
38 149 119 NC

2RBY 4,5 100P - X

54 150 120 NC

2RAM
2RAH

2RAN
2RAK

2RAP
2RAL
2RAJ
100n

100n

100n

100n
76 151

10n

10n

10n
FRA0
9RB8 4,5 JUMP X - 80
92
VDD3V3 152
153
RESET-DVBS
IRA2
62
58
RESETB
COMP
0
40
41 IRA3 3RA3

2RBM 4,5 27P X - 96 154

STDBY 1
120K

3RA6
106 155 26 101

10K
FRA1 TCK 1 NC

2RCB 4,5 27P - X 2

156
157
FRA2
23
24
TDI 2
50
49
NC

-
+1V0-DVBS FRA3 TDO 3 NC
3 VDDA1V0 158 29 47
2RBW 7 33N X 159
+3V3-DVBS FRA4
27
TMS 4
46
NC
FRA5 TRST 5 NC

9RB6 25 JUMP X - 2RAR

100n
5
9
160
161
6
GPIO 7
44
43
NC
NC

3RA4
13 162 37

1K0
9RB7 25 JUMP X 114 163
8
35
NC
NC

-
VDDA2V5 9
118 164 34 NC
2RB7 27 10U X 123 165
10
32 NC

-
FRA6 11
+2V5-DVBS 127 30
2RBU 27 4N7 X 12
55
NC
NC

-
13
2RBV 68P X

2RAW
27
2RAU
2RAS

2RAV
2RAT
100n

100n

100n

100n

100n
9RB9 27 JUMP X -
3RB3 27 4R7 X 2K2

+3V3RF

IRA4 3RB3 IRA9

* 9RB9
* 4R7

2RBU

2RBV
2RB2

2RB3

2RB4

2RB5

2RB6

2RB7
100n

100n
1n0

1n0

1n0

4n7

10u

68p
* * *
7RC1
2RBE LD1117DT33
7RA0 5RC0 IRC3 FRC1
STV6110AT 6 8 11 14 22 27 28 3 2
10p 3 +5V IN OUT +3V3-DVBS
2 NC 4

LNA LT MIX DIG BB VCO SYN

NX3225GA

16V
2RB8 3RB0 30R
1RA0

30 VSS 32 COM
16M

XTAL_OUT XTAL

2RC5

2RC6
100n
XTAL_IN 100p 1K0

22u
2RBF 1 31 18 4 5 QP 1
IP
19 3 6 3RB1-4 100R
IN QM
1 3RB1-3 100R
10p XTAL_CMD
2RC7 RES SATELLITE 21 1 8 IP
QP
SCLT 10p 12 TUNER 20 2 7 3RB1-1 100R IM
SCL QN
SDAT 13 3RB1-2 100R
SDA
2RC8 RES I2C-ADDRESS : C6 RF_OUT
7
10p

10p

10p

10p

10p

10p

10p

10p
AGC 10p 2
AGC
34
2RBW
2RBD

9RB0 16 35
10p

33n

2RBC

2RBN

2RBR
2RBA

2RBB

2RBP

2RBS
2RB9

AS IRC0
RES 36 +3V3
23 37
+3V3RF
24 NC VIA 38 *

2RC0
39

1u0
1R01 7RC0
40

6 2
1 * 2RBM
4
RF_IN
41
42
RT9193-25GB

27p FRC0
7 3 1 5 +2V5-DVBS
IN OUT
2RBY

GND
100p

8 4 3RC1 IRC1
IRC2
9 5 RF LNA LT MIX DIG BB VCO SYN HS 3 4
+3V3-DVBS EN BP
5RA2

2RC1

2RC2
5 3 9 10 15 17 25 26 29 33
27n

1u0

1u0
10
* 10K
COM

2RC3

3RC2

2RC4
100n

10K

10n
2
FRA8
* 2RCB
RES 2RBG

9RB6

9RB7
0p56

+V-LNB
27p
* *
SM15T

2RBH
RES 2RBT

6RA0

9RB8
2RBJ

100p
47p

1n0

+3V3RF
*
+3V3-DVBS 7RC2
BC847BW

5 2011-12-06

DVBS Front-end
8204 000 9218

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2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 78

10-1-9 B03A, LVDS fanout

LVDS fanout
B03A B03A

7J00-6
FUSION240 7J00-7
FUSION240
AK23
FLASH_CI_GPIO AJ22
CA-D00
AF26
FRD0_PODD0 PODA4
AH22
CA-A04 TS_TSB_MCU AH18
CA-D01 FRD1_PODD1 PODA5 CA-A05 0 MDI0
CA-D02 AE24 AF22 CA-A07 AJ18 MDI1
FRD2_PODD2 POD_A7 1
CA-D03 AK25 AJ23 CA-A08 AK18 MDI2
FRD3_PODD3 POD_A8 2
CA-D04 AH25 AH23 CA-A09 AE19 MDI3
FRD4_PODD4 POD_A9 3
CA-D05 AH27 CA-MDO0 AG20 TS2OD AF19 MDI4
FRD5_PODD5 0 4
CA-D06 AK27 AE27 CA-RDY CA-MDO1 AH20 AG19 MDI5
FRD6_PODD6 PODIREQ 1 5
CA-D07 AJ25 AG30 CA-RST CA-MDO2 AJ20 AH19 MDI6
FRD7_PODD7 PODRST 2 6
CA-A00 AF25 AF30 CA-VS1n CA-MDO3 AK20 AJ19 MDI7
FRD8_PODA0 PODVS1 3 7
CA-A01 AG26 AE28 CA-WAITn CA-MDO4 AE21 TS1D
FRD9_PODA1 PODWAIT 4
CA-A02 AK26 AE30 FJ16 CA-MDO5 AF21 AK19 MICLK
FRD10_PODA2 POD_DIR 5 TS2OCLK
CA-A03 AG25 CA-MDO6 AG21 AE20 MISTRT
FRD11_PODA3 6 TS2OSYNC
CA-A10 AE25 AD28 CA-CE1n CA-MDO7 AH21 AF20 MIVAL
FRD12_PODA10 PODCE1 7 TS2ODEN
CA-A11 AH26 AD27 CA-CE2n
FRD13_PODA11 PODCE2 2FZ5
CA-A12 AH28 AF29 CA-CD1n CA-MOCLK AJ21
FRD14_PODA12 PODCD1 TS1CLK 3FZ0
CA-A13 AF24 AD30 CA-CD2n CA-MOSTRT AK21 F27 4n7 SOC-IF-AGC
FRD15_PODA13 POD_CD2 TS1SYNC TAGCO_IF
CA-MOVAL AE22 G26 100R
TS1DEN TAGCO_RF FJ10
AE29
POD_VCC_EN
FRA0 AG29 AD29 T28
FRA0_AD0 POD_VPP_EN DGPIO1
CA-WEn AD26 TS-CHDEC-DATA U28 T29
FRA1_PODWE TSSDI DGPIO2
CA-IORDn AH29 TS-CHDEC-CLK U29
FRA2_PODIORD TSSCLK
CA-IOWRn AJ29 R30 SPEAKER-DETECTn TS-CHDEC-SOP U30
FRA3_PODIOWR HPD TSSSYNC
CA-REGn AF28 TS-CHDEC-VALID T26 M27 STB-GP0
FRA4_PODREG TSSDEN 0
FRA5 AH30 B7 GPIO0 IF-IN-P M26 STB-GP1
FRA5_AD1 GPIO0 10p 1
FRA6 AG28 B10 GPIO1 2FZ6 M25 STB-GP2
FRA6_AD2 GPIO1 47p 2FZ1 2
FRA7 AJ30 C10 CTRL-DISP1 IF-IN-N F30 N30 STB-GP3
FRA7_AD3 GPIO2 10p P 3
FRA8 AJ28 C9 CTRL-DISP2 F29 IN N29 STB-GP4
FRA8_AD4 GPIO3 2FZ2 N 4
CA-OEn AJ27 B9 SDIO1-D1 N28 STB-GP5
FRA9_PODOE GPIO4 STB_GP 5
FRA10 AF27 B8 SDIO1-WP 100n E28 N27 STB-GP6
FRA10_AD5 GPIO5 2J10 P 6
FRA11 AG27 A7 SDIO1-D2 100n 2FZ3 E27 PD N26 STB-GP7
FRA11_AD6 GPIO6 N 7
FRA12 AG24 B11 SDIO1-D3 2FZ4 N25 STB-GP8
FRA12_AD7 GPIO7 18p 8
NAND-CLE AE23 A11 GPIO8 P25 STB-GP9
FRA13_CLE GPIO8 9

3
AK22 A10 H30 P26

24M
NAND-ALE FRA14_ALE GPIO9 SDIO1-D0 XTLI24M 10 STB-GP10

1J00
CA-A14 AJ26 C11 SDIO1-CMD
FRA15_PODA14 GPIO10
A9 3FZ1 SDIO1-CLK 2 H29 R28 STB-RXD
GPIO11 2J11 XTLO24M STB_RXD
4 R27 STB-TXD

1
33R STB_TXD
F-OEn AK29 P27 STB-SDA
FOE 18p STB_SDA
F-WEn AK24 A13 RESET-STANDBYn J26 P28 STB-SCL
FWE GPIO14 FJ14 RSTN STB_SCL
C12 AMBI-SPI-CCLK-FUS
GPIO15
F-CEn AJ24 D12 AMBI-SPI-MOSI-FUS J25 LED
BOOTCS GPIO16 LED
TS-DVBS-DATA AE26 C13 FJ15 TEST-CON P30 M29 IR
FCE2N GPIO17 TESTCON IR
TS-DVBS-VALID AF23 E10 GPIO18 TEST-MOD P29 J30 KYBRD
FINT1 GPIO18 TESTMOD KYBRD
TS-DVBS-SOP AK28 D11 GPIO19 M30 LGSEN
FINT2 GPIO19 LGSEN
TS-DVBS-CLK AH24 E11 GPIO20 ENABLE-STANDBY H25 M28 HDMI-CEC
FCLK GPIO20 STB_EN CEC
CA-A06 AG22 B12 ENABLE-3V3-AMBI-FUS R29 PWRON
FAVD_PODA6 GPIO21 PWRON
F-RDY AG23 A12 GPIO22
FREADY GPIO22
B13 GPIO23 SPI-EN K28 K25 AVLINK1
GPIO23 SPI_EN 1
D10 GPIO24 SF-SDI L28 AVLINK K26 AMBI-TEMP-FUS
GPIO24 SFSI 2
SF-SDO L26
SFSO
SF-WP K30 J27 PCVS
SFWPN PCVS
SF-HOLDn L27 J28 PCHS
SFHOLDN PCHS
SF-CS L29
SFCES
SF-CLK L30 J29 STB-RSTO
SFSCK STB_RSTO
K27 HP-DETECT
HP_DETECT
H26 AUDIO-MUTEn
MUTE

3 2011-12-22

LVDS fanout
8204 000 9237

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2012-Sep-14 back to
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 79

10-1-10 B03B, UMAC controller

7J00-8
UMAC controller
B03B
FUSION240

AH8
DDR3 P2
M0-MD0 DB71 0 0 M1-MD0
M0-MD1 AH5 V2 M1-MD1
1 1
M0-MD2 AH7 R1 M1-MD2
2 2
M0-MD3 AJ5 V1 M1-MD3
3 3
M0-MD4 AK8 R3 DB79 M1-MD4
4 4
M0-MD5 AH6 U1 M1-MD5
5 5
M0-MD6 AJ8 P1 M1-MD6
6 6
M0-MD7 AK5 U3 M1-MD7
7 7
M0-MD8 AK11 L5 DB78 M1-MD8
8 8
M0-MD9 DB72 AF9 R4 M1-MD9
9 9
M0-MD10 AJ11 L4 M1-MD10
10 10
M0-MD11 AG9 P5 M1-MD11
11 11
M0-MD12 AF10 M5 M1-MD12
12 12
M0-MD13 AG8 R5 M1-MD13
13 13
M0-MD14 AH10 M4 M1-MD14
14 14
M0-MD15 AH9 P4 DB77 M1-MD15
15 15
M0-MD16 AG1 MM0DQ MM1DQ W1 M1-MD16
16 16
M0-MD17 AF3 AB1 DB76 M1-MD17
17 17
M0-MD18 AE3 Y3 M1-MD18
18 18
M0-MD19 AH1 AB3 M1-MD19
19 19
M0-MD20 AH2 Y1 M1-MD20
20 20
M0-MD21 DB73 AD3 AC2 M1-MD21
21 21
M0-MD22 AD1 Y2 M1-MD22
22 22
M0-MD23 AD2 AC1 M1-MD23
23 23
M0-MD24 AK4 U5 M1-MD24
24 24
M0-MD25 AG3 AA4 M1-MD25
25 25
M0-MD26 AJ3 T5 M1-MD26
26 26
M0-MD27 AK2 Y5 M1-MD27
27 27
M0-MD28 AK3 U4 M1-MD28
28 28
M0-MD29 AJ2 W5 DB75 M1-MD29
29 29
M0-MD30 AG5 V5 M1-MD30
30 30
M0-MD31 DB74 AJ1 Y4 M1-MD31
31 31

M0-DQM0 AJ6 T1 M1-DQM0

0 0
M0-DQM1 AK9 P3 M1-DQM1
1 1
M0-DQM2 AE1 MM0DM MM1DM AA1 M1-DQM2
2 2
M0-DQM3 AH3 W3 M1-DQM3
3 3

M0-DQS0 AK7 T2 M1-DQS0

P P
M0-DQS#0 AK6 MM0DQS0 MM1DQS0 T3 M1-DQS#0
N N
M0-DQS1 DB14 AJ10 N3 DB46 M1-DQS1
P P
M0-DQS#1 DB16 AK10 MM0DQS1 MM1DQS1 N4 DB47 M1-DQS#1
N N
M0-DQS2 AF2 AA3 M1-DQS2
P P
M0-DQS#2 AF1 MM0DQS2 MM1DQS2 AA2 M1-DQS#2
N N
M0-DQS3 AH4 V4 M1-DQS3
P P
M0-DQS#3 AG4 MM0DQS3 MM1DQS3 V3 M1-DQS#3
N N

M0-MA0 AJ12 L2 M1-MA0

0 0
M0-MA1 AJ17 F2 M1-MA1
1 1
M0-MA2 AK15 H1 M1-MA2
2 2
M0-MA3 AH15 H3 M1-MA3
3 3
M0-MA4 AH17 F3 M1-MA4
4 4
M0-MA5 AF15 H5 M1-MA5
5 5
M0-MA6 AF17 F5 M1-MA6
6 6
M0-MA7 AJ15 H2 M1-MA7
7 7
M0-MA8 AH16 MM0A MM1A G3 M1-MA8
8 8
M0-MA9 AG17 F4 M1-MA9
9 9
M0-MA10 AF13 K5 M1-MA10
10 10
M0-MA11 AK16 G1 M1-MA11
11 11
M0-MA12 AK12 L1 M1-MA12
12 12
M0-MA13 AF16 G5 M1-MA13
13 13
M0-MA14 AK17 F1 M1-MA14
14 14
M0-MA15 AJ13 K2 M1-MA15
15 15
+1V5-M0 M0-BA0 AG12 M1 M1-BA0
0 0
M0-BA1 AF14 J5 M1-BA1 +1V5-M1
1 MM0BA MM1BA 1
M0-BA2 AK13 K1 M1-BA2
2 2
M0-CAS# AH12 L3 M1-CAS#
MM0CASN MM1CASN
M0-RAS# AF12 M3 M1-RAS#
MM0RASN MM1RASN
M0-WE# AF11 N2 M1-WE#
MM0WEN MM1WEN
M0-CKE AH13 K3 M1-CKE
MM0CKE MM1CKE
M0-ODT AG11 N1 M1-ODT
MM0ODT MM1ODT
M0-RESET# AG15 H4 M1-RESET#
MM0RESETN MM1RESETN
100n
2J06

3J05

AG14 J4
1K0

M0-CS# MM0CSN MM1CSN M1-CS#

100n
3J03

2J04
1K0
M0-MCLK0 AK14 J1 M1-MCLK0
P P
M0-MCLK0# AJ14 MM0CK MM1CK J2 M1-MCLK0#
N N
FJ05
M0-MVREF0 M0-MVREF0 AE11 U7
0 0 FJ04
AE12 MM0VREF MM1VREF U6 M1-MVREF1 M1-MVREF1
240R 1 1 240R
AE7 T7
MZQ0 MZQ1
3J00 AD18 E1 3J01
MM0ANA_TEST MM1ANA_TEST
100n

100n
2J07

3J06

2J05

AA7
1K0

DDR_RETN

100n

100n
2J02

3J04

2J03
1K0
FJ01 FJ00 FJ03
MM0ANA MM0ANA MM1ANA MM1ANA
FJ02
+1V5-M1

DB80 DB85

3J02
DB81 DB86

1K0
DB82 DB87
DDR-RTN
DB83 DB88

100p
2J00
DB84 DB89

3 2011-12-22

UMAC controller
8204 000 9237

19210_014_120424.eps
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2012-Sep-14 back to
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 80

10-1-11 B03C, UMAC 1 DDR3

UMAC 1 DDR3
B03C B03C
+1V5-M1

+1V5-M1
7J01 +1V5-M1

G7
D9

N1
N9
R1
R9

C1
C9
D2

H2
H9
B2

K2
K8

A1
A8

E9
F1
H5TQ2G63BFR-PBC
VDD VDDQ

M1-MA0 M1-MA0 N3
3J19 0
3J18 M1-MA1 P7
M1-MA1
1
100R 100R M1-MA2 P3 7J02

G7
2

D9

N1
N9
R1
R9

C1
C9
D2

H2
H9
B2

K2
K8

A1
A8

E9
F1
3J1A 3J1B M1-MA3 N2 H5TQ2G63BFR-PBC
3
M1-MA2 100R 100R M1-MA4 P8 D7 M1-MD1 VDD VDDQ
3J1D 4 0
3J1C +1V5-M1 M1-MA5 P2 C3 M1-MD4
5 1
M1-MA3 100R 100R M1-MA6 R8 A C8 DB40 M1-MD3 M1-MA0 N3
6 2 0
3J1E 3J1F M1-MA7 R2 C2 M1-MD6 M1-MA1 P7
7 3 1
M1-MA4 100R 100R M1-MA8 DB31 T8 DQU A7 M1-MD5 M1-MA2 P3
8 4 2
3J1G 3J1H M1-MA9 R3 A2 M1-MD0 M1-MA3 N2
9 5 3
M1-MA5 100R 100R M1-MA10 L7 B8 M1-MD7 M1-MA4 P8 D7 M1-MD21
10 6 4 0
3J1J 3J1K M1-MA11 DB32 R7 A3 DB41 M1-MD2 M1-MA5 P2 C3 DB56 M1-MD22
11 7 5 1
M1-MA6 100R 100R M1-MA12 N7 M1-MA6 R8 A C8 M1-MD23
12 6 2
3J1L 3J1M M1-MA13 DB33 T3 C7 DB42 M1-DQS0 M1-MA7 DB49 R2 C2 M1-MD16
100n 13 DQSU 7 3
2J16

3J11
100R 100R DB34 T7 B7 T8 DQU A7

1K0
M1-MA7 M1-MA14 14 DQSU DB43 M1-DQS#0 M1-MA8 DB50 8 4 M1-MD17
3J1N 3J1P M1-MA15 M7 M1-MA9 R3 A2 M1-MD18
15 9 5
M1-MA8 100R 100R F3 DB44 M1-DQS1 M1-MA10 L7 B8 DB57 M1-MD19
3J1R BC DQSL 10 6
3J1Y G3 DB45 M1-DQS#1 M1-MA11 R7 A3 M1-MD20
AP DQSL 11 7
M1-MA9 100R 100R M1-MA12 N7
FJ08 12
3J1S 3J1T DDR-MVREF11 DDR-MVREF11 H1 E3 M1-MD14 M1-MA13 DB51 T3 C7 M1-DQS2
VREFDQ 0 13 DQSU
M1-MA10 100R 100R M8 F7 M1-MD15 M1-MA14 DB52 T7 B7 M1-DQS#2
3J1V VREFCA 1 14 DQSU
3J1U F2 M1-MD12 M1-MA15 M7
2 15

100n

100n
2J14

2J15
M1-MA11 100R 100R L8 F8 M1-MD11 F3 DB58 M1-DQS3
ZQ 3 BC DQSL
100n

3J1Z
2J17

3J12

3J1W DQL H3 G3
1K0

M1-MD8 DB59 M1-DQS#3

4 AP DQSL

240R
3J10
M1-MA12 100R 100R M2 H8 DB48 M1-MD9
3J21 BA0 5
3J20 N8 G2 M1-MD10 DDR-MVREF12 H1 E3 M1-MD28
BA1 6 VREFDQ 0
M1-MA13 100R 100R DB62 M3 H7 M1-MD13 M8 F7 M1-MD31
3J23 BA2 7 VREFCA 1
3J22 DB63 F2 M1-MD30
2

100n

100n
2J18

2J19
M1-MA14 100R 100R M1-BA0 J3 L8 F8 DB60 M1-MD27
3J25 RAS ZQ 3
3J24 M1-MCLK0 M1-BA1 DB90 K1 DQL H3 M1-MD26
ODT 4

240R
3J13
M1-MA15 100R 100R M1-BA2 DB35 K3 M2 H8 M1-MD25
3J27 CAS BA0 5
3J26 M1-RAS# DB36 J7 N8 G2 M1-MD24
CK BA1 6
M1-BA0 100R 100R +1V5-M1 M1-ODT DB38 K7 J1 M3 H7 M1-MD29
3J29 CK BA2 7
3J28 M1-CAS# K9 J9 DB64 DB65
CKE
3J16

100R 100R L2 L1 J3
75R

M1-BA1 M1-MCLK0 DB91 CS NC M1-BA0 DB53 RAS

3J2A 3J2B M1-MCLK0# DB39 L3 L9 M1-BA1 K1
WE ODT
2J12

100R 100R T2 K3
10n

M1-BA2 RES RESET M1-BA2 DB54 CAS

3J2C 3J2D M1-RAS# J7
CK
M1-RAS# 100R 100R M1-CKE DB92 E7 M1-ODT K7 J1
3J2F DML CK
3J2E M1-CS# D3 M1-CAS# K9 J9
DMU VSS VSSQ CKE
M1-CAS# 100R 100R M1-WE# M1-MCLK0 L2 NC L1
CS
2J89

3J2H

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9
3J2G L3 L9
10n

M1-RESET# M1-MCLK0# DB55 WE

3J17

100R 100R T2
75R

M1-WE#
3J2K RESET
3J2J M1-DQM1 DBA8
M1-CS# 100R 100R M1-DQM0 M1-CKE E7
3J2M DML
3J2L M1-CS# D3 VSSQ
DMU VSS
M1-ODT 100R 100R M1-WE#
3J2P

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9
3J2N M1-RESET#
M1-CKE 100R 100R M1-MCLK0#
3J2Q 3J2R M1-DQM3
M1-RESET# 100R 100R M1-DQM2
3J2S 3J2T DB66
100R 100R +1V5-M1

2J1A
100n
3J14
1K0
FJ09
DDR-MVREF12

2J1B
100n
3J15
1K0
+1V5-M1 +1V5-M1

DB93 DB98 DBA3

DB94 DB99 DBA4

2J1M

2J1G
2J1R

2J1C
2J1P

2J1V

2J1E
100n

100n

100n
2J1T

100n

100n
2J1Z

100n

100n
2J22

2J81

2J82

2J83

2J84

2J21

2J1J
10u

10n

10n

10n

10n

10n

10n

10n

10n

DB95 DB01 DBA5

DB96 DBA1 DBA6

DB97 DBA2 DBA7

+1V5-M1 +1V5-M1
47u 16V

2J1W
2J1Q
2J1N

2J1U

2J1D

2J1H
2J1S

2J1K
100n

100n

100n

100n

100n

100n

100n

2J1F
2J27

2J24

2J25

2J1L

2J85

2J86

2J87

2J88

2J20
10u

10u

10n

10n

10n

10n

10n

10n

10n

10n

3 2011-12-22

UMAC 1 DDR3
8204 000 9237

19210_015_120424.eps
120424

2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 81

10-1-12 B03D, UMAC 0 DDR3

UMAC 0 DDR3
B03D B03D
+1V5-M0

+1V5-M0
7J03 +1V5-M0

G7
D9

N1
N9
R1
R9

C1
C9
D2

H2
H9
B2

K2
K8

A1
A8

E9
F1
H5TQ2G63BFR-PBC
VDD VDDQ

M0-MA0 M0-MA0 N3
3J35 0
3J34 M0-MA1 P7
M0-MA1
1
100R 100R M0-MA2 P3 7J04

G7
2

D9

N1
N9
R1
R9

C1
C9
D2

H2
H9
B2

K2
K8

A1
A8

E9
F1
3J36 3J37 M0-MA3 N2 H5TQ2G63BFR-PBC
3
M0-MA2 100R 100R M0-MA4 P8 D7 M0-MD0 VDD VDDQ
3J39 4 0
3J38 +1V5-M0 M0-MA5 P2 C3 M0-MD5
5 1
M0-MA3 100R 100R M0-MA6 R8 A C8 DB09 M0-MD4 M0-MA0 N3
3J3B 6 2 0
3J3A M0-MA7 R2 C2 M0-MD7 M0-MA1 P7
7 3 1
M0-MA4 100R 100R M0-MA8 DB61 T8 DQU A7 M0-MD2 M0-MA2 P3
3J3D 8 4 2
3J3C M0-MA9 R3 A2 M0-MD1 M0-MA3 N2
9 5 3
M0-MA5 100R 100R M0-MA10 L7 B8 M0-MD6 M0-MA4 P8 D7 M0-MD16
3J3F 10 6 4 0
3J3E M0-MA11 DB00 R7 A3 DB10 M0-MD3 M0-MA5 P2 C3 DB25 M0-MD18
11 7 5 1
M0-MA6 100R 100R M0-MA12 N7 M0-MA6 R8 A C8 M0-MD20
12 6 2
3J3G 3J3H M0-MA13 DB02 T3 C7 DB11 M0-DQS0 M0-MA7 DB18 R2 C2 M0-MD23
13 DQSU 7 3

2J2A

3J2V
100n
100R 100R DB03 T7 B7 T8 DQU A7

1K0
M0-MA7 M0-MA14 14 DQSU DB12 M0-DQS#0 M0-MA8 DB19 8 4 M0-MD17
3J3J 3J3K M0-MA15 M7 M0-MA9 R3 A2 M0-MD21
15 9 5
M0-MA8 100R 100R F3 DB13 M0-DQS1 M0-MA10 L7 B8 DB26 M0-MD19
BC DQSL 10 6
3J3L 3J3M G3 DB15 M0-DQS#1 M0-MA11 R7 A3 M0-MD22
AP DQSL 11 7
M0-MA9 100R 100R M0-MA12 N7
FJ0A 12
3J3N 3J3P DDR-MVREF01 DDR-MVREF01 H1 E3 M0-MD15 M0-MA13 DB20 T3 C7 M0-DQS2
VREFDQ 0 13 DQSU
M0-MA10 100R 100R M8 F7 M0-MD12 M0-MA14 DB21 T7 B7 M0-DQS#2
3J3R VREFCA 1 14 DQSU
3J3Y F2 M0-MD9 M0-MA15 M7
2 15

100n

100n
2J28

2J29
M0-MA11 100R 100R L8 F8 DB69 M0-MD10 F3 DB27 M0-DQS3
ZQ 3 BC DQSL
3J2W
2J2B

100n

3J3S 3J3T DQL H3 G3

1K0

4 M0-MD11 AP DQSL DB29 M0-DQS#3

240R
3J2U
M0-MA12 100R 100R DB68 M2 H8 DB17 M0-MD14
3J3V BA0 5
3J3U N8 G2 M0-MD13 DDR-MVREF02 H1 E3 M0-MD29
BA1 6 VREFDQ 0
M0-MA13 100R 100R M3 H7 M0-MD8 M8 F7 M0-MD28
3J3Z BA2 7 VREFCA 1
3J3W F2 M0-MD25
2

2J2C

2J2D
100n

100n
M0-MA14 100R 100R M0-BA0 J3 L8 F8 DB30 M0-MD26
RAS ZQ 3
3J40 3J41 M0-MCLK0 M0-BA1 DBA9 K1 DQL H3 M0-MD27
ODT 4

240R
3J2Z
M0-MA15 100R 100R M0-BA2 DB04 K3 M2 H8 M0-MD30
3J43 CAS BA0 5
3J42 M0-RAS# DB05 J7 DB67 N8 G2 M0-MD31
CK BA1 6
M0-BA0 100R 100R +1V5-M0 M0-ODT DB07 K7 J1 M3 H7 DB70 M0-MD24
3J45 CK BA2 7
3J44 M0-CAS# DBB0 K9 J9
CKE
3J32

100R 100R L2 L1 J3
75R

M0-BA1 M0-MCLK0 CS NC M0-BA0 DB22 RAS

3J46 3J47 M0-MCLK0# DB08 L3 L9 M0-BA1 K1
WE ODT
2J01

100R 100R DBB1 T2 K3

10n

M0-BA2 RES RESET M0-BA2 DB23 CAS

3J48 3J49 M0-RAS# J7
CK
M0-RAS# 100R 100R M0-CKE DBB2 E7 M0-ODT K7 J1
3J4B DML CK
3J4A M0-CS# D3 VSSQ M0-CAS# K9 J9
DMU VSS CKE
M0-CAS# 100R 100R M0-WE# M0-MCLK0 L2 NC L1
CS
2J2G

3J4D

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9
3J4C DB24 L3 L9
10n

M0-RESET# M0-MCLK0# WE
3J33

100R 100R T2
75R

M0-WE# RESET
3J4E 3J4F M0-DQM1
M0-CS# 100R 100R M0-DQM0 M0-CKE E7
3J4H DML
3J4G M0-CS# D3
DMU VSS VSSQ
M0-ODT 100R 100R M0-WE#
3J4K

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9
3J4J M0-RESET#
M0-CKE 100R 100R M0-MCLK0#
3J4L 3J4M M0-DQM3
M0-RESET# 100R 100R M0-DQM2
3J4N 3J4P
100R 100R +1V5-M0

2J2E
100n
3J30
1K0
FJ0B
DDR-MVREF02

100n

2J2F
3J31
1K0
+1V5-M0 +1V5-M0
47u 16V

2J2M
2J3G

2J2H

2J3C

2J2R
2J3K

2J2K

2J2P

2J3A

2J3E

2J2V
2J3F

100n

100n

100n

100n

100n

100n

100n

2J2T

2J2Z
2J32

2J34

2J36

2J38
10u

10u

10n

10n

10n

10n

10n

10n

10n

10n
DBB3 DBB8 DBC3

DBB4 DBB9 DBC4

DBB5 DBC0 DBC5

DBB6 DBC1 DBC6

+1V5-M0 +1V5-M0
DBB7 DBC2 DBC7
2J2W
2J3H

2J2N

2J3D

2J2U
2J2Y

2J3B

2J2S
100n

100n

100n

100n

100n

100n

100n
2J31

2J33

2J35

2J37

2J2L

2J39

2J30
2J3J

2J2J
10u

10u

10n

10n

10n

10n

10n

10n

10n

10n

3 2011-12-22

UMAC 0 DDR3
8204 000 9237

19210_016_120424.eps
120424

2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 82

10-1-13 B03E, DDR fanout

DDR fanout
B03E B03E

7J00-4
FUSION240
AV_IN_OUT
AR-1 A22 B21 HPHOL
AR_1 HPHOL
AL-1 B22 A21 HPHOR
AL_1 HPHOR
E22
AR_2
D22 C21
AL_2 SUBO
AR-3 A23 7J00-5
AR_3
AL-3 B23 A25 FUSION240
AL_3 SPK_AOR1
AR-4 E23 B25 PANEL_USB
AR_4 SPK_AOL1
AL-4 D23 USB1-DP AB30
AL_4 D1_P LAN_IO
A24 D25 USB1-DM AB29
AR_5 AOR2 D1_N
B24 C25 AB26
AL_5 AOL2 USBPPON1
AR-6 E24 USB1-RREF AB27
AR_6 TXRTUNE1
AL-6 D24 A2 V1-TX0P
AL_6 TX0_P
USB2-DP AC30 B2 V1-TX0N
D2_P TX0_N
D26 E26 SPDIFO USB2-DM AC29
SPDIFIN SPDIFO D2_N
AB25 C3 V1-TX1P
USBPPON2 TX1_P
C26 Y26 3J07 SCKI2SOUT USB2-RREF AC27 C2 V1-TX1N 7J00-9
SCKIN SCKI2SOUT TXRTUNE2 TX1_N
B26 Y27 3J08 10R WSI2SOUT FUSION240
WSI2SIN WSI2SOUT
A26 AA30 3J09 10R SDI2SOUT1 B3 V1-TX2P UART_JTAG
SDI2SIN 1 TX2_P
AA29 3J50 10R SDI2SOUT2 EN-RXD0 W29 A3 V1-TX2N U26 SCL-S
SDI2SOUT 2
AB28 3J51 10R SDI2SOUT3 EN-TXD0 V29
GBE_RXD0 TX2_N
RXD-SERVICE Y29
I2C SCLS U27 SDA-S
3 GBE_TXD0 RXD SDAS
IJ10 Y25 3J52 10R I2SCLK EN-RXD1 W28 A4 V1-TX3P TXD-SERVICE Y28
I2SCLK GBE_RXD1 TX3_P TXD
AC28 10R EN-TXD1 V28 B4 V1-TX3N
GPANA1 GBE_TXD1 TX3_N
FJ0F W27 AA28 SCL-M1
GBE_RXD2 SCLM1
FJ0G V27 C5 V1-TX4P EJT-TCK D14 AA27 SDA-M1
GBE_TXD2 TX4_P TCK SDAM1
CVBS C15 FJ0H W26 C4 V1-TX4N EJT-TMS D13
CVBS GBE_RXD3 TX4_N TMS
A15 FJ0J V26 EJT-TDO E12 D1 SCL-M2
CVBS2 GBE_TXD3 TDO SCLM2
CVBS3 B16 B5 V1-TX5P EJT-TDI E13 E2 SDA-M2
CVBS3 TX5_P TDI SDAM2
A16 EN-RXC V25 A5 V1-TX5N EJT-TRSTN C14
CVBS4 GBE_RXC TX5_N TRSTN
EN-TXC U25 AA26 SCL-M3
GBE_TXC SCLM3
C16 A6 V1-TX6P AA25 SDA-M3
C TX6_P SDAM3
EN-RXEN W30 B6 V1-TX6N
GBE_RXEN TX6_N
Y-G1 A20 EN-TXEN V30
Y_G1 GBE_TXEN
PB-B1 A19 C7 V1-TX7P
PB_B1 TX7_P
PR-R1 A18 EN-MDC W25 C6 V1-TX7N
PR_R1 GBE_MDC TX7_N
EN-MDIO Y30
GBE_MDIO
Y-G2 B20 CVBS-OUT2 IJ11 D4 V1-HTPDn
Y_G2 HTPDN
PB-B2 B19 A14 CVBS-OUT1 E5 V1-LOCKn
PB_B2 1 LOCKN
PR-R2 B18 CVBS_OUT B14 CVBS-OUT2 HDMIF-RX0+ A29 D5 9GA2
PR_R2 2 RX0_P IDP_HPD
HDMIF-RX0- B29
RX0_N
Y-G3 C20 HDMIF-RX1+ A28
Y_G3 RX1_P
PB-B3 C19 HDMIF-RX1- B28 A8 BL-SPI-CLK-FUS
PB_B3 RX1_N H_BK_LITE
PR-R3 C18 HDMIF-RX2+ A27 E4 3D-LR-FUS
PR_R3 RX2_P PWM0
HDMIF-RX2- B27 D2 BL-SPI-CS_BL-I-CTRL-FUS
RX2_N PWM1
D20 HDMIF-RXC+ B30 E3 BL-DIM-FUS
IJ12 Y_G4 RXC_P BOOST
D19 HDMIF-RXC- C30 D3 BKLGON-FUS
PB_B4 RXC_N BKLGON
IJ13 D18 C8 BL-SPI-SDO-FUS
PR_R4 TCON_ON
HEAC T27
HEAC
FS1 C17
FS1
FB1 B17 PWR5V T30
FB1 PWR5V
D17 RREF C29
FS2 RREF
A17
FB2

3 2011-12-22

DDR fanout
8204 000 9237

19210_017_120424.eps
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2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 83

10-1-14 B03F, Fusion power supply

Fusion power supply

B03F +1V2-MIPS
B03F

AE4
AF4
AE5
AF5
AE6
AF6
AG6
AF7
AG7
AD8
AE8
AF8
AD9
AE9
AD10
AE10
W11
Y11
AD11
AD12
AD13
AE13
AD14
AE14
AA10
AA11
AA12

W14
W15
W16
Y15
AA15

2J7F

10u
2J6T
10n
7J00-3

100n
2J78
FUSION240

VDDM0

VDDM0

VDDM0

VDDM0

VDD_1V2
Y10
+1V5 +1V5-M1 W10
V10
P10 +1V5-M0
5J0R IJ0S
V12
P12 +1V5

220u 2V0
120R IJ0R 5J0P

2J7W

2J7V
100n

2J7Z
100n

100n
2J08

2J92
V11

10u
2J95

2J94
P11

10n

10n
120R

2J5D

2J5C

2J5B

2J5A
100n

100n

100n

2J59

2J80

2J93
AC7

10u

10u

10n

10n
AB7
R7
7J00-1 P7
FUSION240 N7

2J7R

2J7U
2J7Y

2J7P

2J7S
100n

2J7T
2J09

2J23
M7
SUPPLY_1

10n

10n

10n

10n

10n

10n

10n
IJ07

VDDM1
5J05
+1V2-FA IJ01 G29 +3V3 H7
5J00
F19 AVDDH_DRX G30 G7
120R

2J5M
2J5G
2J5N

2J5H

2J5K
100n
AA19

2J5F
2J41

2J42

2J5L
G19 AVDDL_CH234 AC6

10u

10n

10n

10n

10n

10n

10n

10n
120R
2J3M
2J3N

100n

E30 AB6 AA18

10u

F20 G27 AA6 AA17

G20 AVSSL_CH234 AVSSH_DRX G28 T6 AA16
+3V3 IJ02 H27 R6 N10
5J01
F17 IJ08 P6 K20
5J07
G17 AVDDH_CH234 E29 +1V2-FA N6 K19
120R
2J3Y

2J3P

100n

AVDDL_DRX F28 M6 K18

10u

120R

100n

2J43

2J44
F18 H6 K14

10u
G18 AVSSH_CH234 G6 K13
D21 AC5 AK30
VREFAU
+1V2-FA IJ03 AB5 A30
5J02
D16 C22 IJ09 AC4 W24
5J08 RES
E16 AVDDL_CH516 C23 +3V3 AB4 V24
120R
2J3R
2J3S

100n

K4

VSS
C24 U24
10u

120R IJ00

100n

2J45

2J46
F15 E25 P24

4u7
SGNDAU SENSE+1V1-FD VDDC
F16 AVSSL_CH516 F22 T11 AD21
+3V3 IJ04 F23 AD20
5J03
B15 F24 T10 Y19
AVDDH_CH516
IJ0A AA20 U19
120R 5J09
2J3U

2J3T

100n

G15 G22 AA21 R19

10u

+3V3
G16 AVSSH_CH516 AVDD G23 Y21 N19
120R

100n

2J47

2J48
W21 L19

10u
+3V3-STANDBY IJ05 E21 V21 Y18
5J04
K24 AVSS F21 U21 U18
AVDD33_STB
IJ0B T21 R18
120R 5J0A
2J3W

2J3V

100n

J24 R21 N18

10u

AVSS_STB +3V3
D15 P21 L18
AVDDH 120R

2J4A
100n

2J49
H28 N21 AE17
10u
VDD33_XTAL DAC1
+3V3-STANDBY IJ06 K17 L21 AD17
5J06 AVSSH
L17 K21 Y17
AVSSH
E17 IJ0C M21 U17
120R INN16 5J0B
2J3Z

100n
2J40

M10 R17
10u

+3V3
E18 E15 L10 N17
2 AVDDH 120R

2J4C
2J4B
100n

E19 K10 AJ16

10u
3 INN DAC2
100n
2J90

E20 K16 P14 AG16

4 AVSSH
L16 L25 AE16
AVSSH
100n
2J91

IJ0D M24 AD16

5J0C
+2V5-F L24 Y16
E14 G21 U16
VDD25_LPLL 120R
2J4D

2J4E
100n

Y20 R16
10u
9J03

K15 W20 N16

VSSA_LPLL L15 V20 AE15

VDDC
9J04

U20 AD15

VSS
T20 U15
R20 R15
P20 N15
N20 AH14

PWR_GND
M20 U14
L20 R14
W19 N14
V19 L14
T19 AG13
IJ14 P19 U13
M19 R13
+1V1-FD
W18 N13

2J7G

2J7H
2J7K

2J7E
2J7L

2J7J
V18 L13

10u

10u

10u

10u

10u

10u
+2V5 5J0H IJ0E
7J00-2 T18 U12
FUSION240 P18 R12
120R
2J4S
2J4T

100n

M18 N12
SUPPLY_2
10u

IJ0L 5J0D
AD6 +2V5-F W17 AH11
VDD2V5_M0P AD7 V17 N11
120R
2J4G
2J4H
100n

2J4F

2J96

2J97

AC26 T17 AG10

1u0
10n

10n

10n

VDD25
+3V3 IJ0F Y12 P17 AJ9
5J0J 2J7D

2J7C

2J7B

2J7A
100n

100n

100n

100n

100n

2J79
AC25 Y13 M17 AJ7
VSSAC_1
Y14 V16 Y7
120R VSS_M0P

VDDC
2J4U
2J4V

100n

AC24 AA13 T16 W7

10u

VDD33
AA14 P16 V7
AB24 M16 L7
VSSAC_2
V15 K7
+2V5 IJ0G AC3 T15 J7
5J0K
B1 AD4 IJ0M +2V5-F P15 Y6
VDD2V5_M1P 5J0E
C1 VDDE2V5 AD5 M15 W6
120R
2J4W

2J6W
2J4Z

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

2J6Z
100n
2J77

2J76

2J75

2J74

2J73

2J72

2J71

2J70
V14 V6
10u

120R
100n

2J4L

2J98

2J99
2J4J

F14 R11 T14 L6

1u0

10n

10n

G14 GNDE2V5 U11 M14 K6

VSS_M1P R10 W13 J6

VSS
+1V1-FA IJ0H U10 V13 AA5
5J0L
C28 T13 N5
VDD11A
N24 P13 AJ4
120R VQPS
100n
2J50

2J51

2J52

D27 M13 W4
10n
10u

VSS11A_1
2J6M
2J6U

2J6N

2J6R
2J6V

2J6P

2J6Y

2J6S

W12 T4
10n

10n

10n

10n

10n

10n

10n

10n

IJ0N 5J0F +2V5-F

D29 G13 T12 G4
AVDD25_HDMI
VDDA2V5 F13 M12 J3
120R
2J4M

2J4N
100n

C27 M11 AG2

10u

+2V5 5J0M IJ0J VSS11A_2

K12 G11 AE2

VDDC
D30 GNDA2V5 L12 F11 AB2
120R VDD33A
100n
2J53

2J54

2J55

G10 W2
10n
10u

D28 IJ0P +1V1-FA F10 U2

VSS11A_3 5J0G
2J6G
2J6D

2J6H
2J6E
2J6F
2J6L

2J6J

G12 G9 R2
10n

10n

10n

10n

10n

10n

10n

VDDA1V1 F12 F9 M2
120R
2J4P

2J4Y
100n

E9 G2
10u

+3V3 5J0N IJ0K

K11 D9 AK1
GNDA1V1 L11 G8 A1
120R
2J56

2J58

F8
10u

1n0

E8
K29 D8
LDO11_CAP
2J6C

2J6A

2J6B
2J67

2J66

2J65

2J68

2J69

E7
10n

10n

10n

10n

10n

10n

10n

10n

D7
2J4R

E6
4n7

D6

VDDF_STB
VDDF1

VDDF2

VDDF2

VDDF2
AG18
AD19
AD22
AD23

AD24

AD25
AE18

AA24
AF18

G24

G25
H24

R24
R25
R26
Y24
T24

F25

T25

F26
+3V3
F6
F7

+3V3-STANDBY
2J5W

2J5U

2J5R
2J5V

2J5S

2J5P

2J5Y
100n

100n

100n

100n

2J5Z
100n

100n

100n

100n

2J5T
100n

100n
2J63

2J64

2J62

2J61

2J60
10u

10u

10u

10n
3 2011-12-22

Fusion power supply

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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 84

10-1-15 B04A, Control

Control
B04A B04A
RES 9CV0
+3V3-STANDBY
+3V3
SDA-BE
* 9GM1 SDA-DISP

9CV1 9GM2
SCL-BE
* SCL-DISP

SDA-BE RES 9GM3 SDA-BL

SCL-BE RES 9GM4 SCL-BL

3CVV-1 1

3CVV-2 2

3CVV-3 3

3CVV-4 4

3CVZ
1CV1

4K7

4K7

4K7

4K7

4K7
3CVF
SCL-M2 SCL-BE SCL-BE FCV2 1
47R FCV1
2

5
SDA-BE FCV3 3
1 3CVH-1 8 EJT-TRSTN SDA-M2
3CVG
SDA-BE 5 4
47R 47R
BM03B-SRSS-TBT
3 3CVH-3 6 3CV1

1
1CV2
FCV4 47R
EJT-TMS GPIO8 * 47R
CTRL-DISP3 DBG

2 FCV5
3CVH-4 3CV2
FCV6 4 5 EJT-TDO 3D-LR-FUS 3D-LR 1CWA
3
4 FCV7 47R 47R SCL-DISP 1
5 FCV8 2
2 3CVH-2 7 3CV3
6 FCV9 EJT-TCK BL-DIM-FUS BL-DIM SDA-DISP 3
7 8 47R 47R 5 4

BM06B-SRSS-TBT 3CVJ BM03B-SRSS-TBT

EJT-TDI
DBG 3GM7 RES DBG
47R +3V3
4K7
3
1CWB
1 7GM2 RES SCL-BL
PDTC114EU 1
2
2 SDA-BL 3
5 4

BM03B-SRSS-TBT
RES 3CV8 DBG
BL-SPI-CLK-FUS AMBI-SPI-CCLK
10R
RES 3CV9
BL-SPI-SDO-FUS AMBI-SPI-MOSI
10R
3CV4
AMBI-SPI-CCLK-FUS AMBI-SPI-CCLK
10R
3CV5
AMBI-SPI-MOSI-FUS AMBI-SPI-MOSI
10R
1CWC
3CV6
ENABLE-3V3-AMBI-FUS ENABLE-3V3-AMBI TXD-RF4CE 1
47R FCVA
2
GPIO19 ICV1 RXD-RF4CE 3
3CV7 3CVU 5 4
GPIO20 ICV2 POWER-OK POWER-OK +3V3
47R 2CV7 10K BM03B-SRSS-TBT
100n DBG
3CVA
GPIO22 RESET-HDMI-MUXn
47R

RES 3CVB
+3V3
4K7 +3V3-STANDBY
3CVK
GPIO24 IRQ-SRFn
3CVL
47R IRQ-SRFn
3CVM 10K
GPIO0 TXD-RF4CE
3CVN RES
47R TXD-RF4CE
3CVP 10K
GPIO1 RXD-RF4CE
3CVR RES
47R RXD-RF4CE
3CVS 10K
GPIO23 IRQ-EXPANDERn
3CVT
47R IRQ-EXPANDERn +3V3
+3V3
10K

+3V3

7GM1
3GM5

3GM6

PCA9540BGD
4K7

4K7

3
VDD
4 SDA-DISP SDA-DISP RES 3GM1 +3V3
SD0
SDA-BE 2 5 SCL-DISP SCL-DISP RES 3GM2 100K
SDA SC0
100K 3GM3
SCL-BE 1 7 SDA-BL SDA-BL
SCL SD1
8 SCL-BL SCL-BL 3GM4 100K
SC1
100K
VSS
6

4 2011-12-22

Control
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 85

10-1-16 B04B, V-by-One out

V-by-One out
B04B B04B
BL-DIM 1G55
CTRL-DISP3 20519-051E
+VDISP
3D-LR FGV5 60 61
58 59

2GV2
100n
3GV1-3 RES 56 57
RES 3GV1-2 3GVJ 100R RES 54 55

SHARP
10K 10K 52 53
3GVH 1K0 RES BGVJ

9GV3-2
9GV3-3
9GV3-4
51

2GV1
1u0
RES 3GV1-4

RES 3GV1-1
50
9GV5

10K

10K

RES
49
SAMSUNG 48
+3V3 9GW0 IGVA
47
3GVG 100R 3GW7 100R BGVL SAMSUNG IGVB
46
3GW8 100R BGVM 45

3GV6

3GV5
9GV4

10K

10K
IGVE 44
+3V3 +3V3 SHARP 43
3GV7 42
V1-HTPDn BGVN 41
V1-LOCKn 100R 3GV8 BGV1 40
2GW3 100R 9GW1 BGV2 39
100n 2GW4
SAMSUNG 38
V1-TX0N 100n 2GV3 BGV3
37
V1-TX0P 100n 2GV4
36
2GW5 100n
BGV4 35
100n 2GW6
BGV5 34
V1-TX1N 100n 2GV5
33
V1-TX1P 100n 2GV6
32
2GW7 100n BGV6 31
100n 2GW8
BGV7 30
V1-TX2N 100n 2GV7
29
V1-TX2P 100n 2GV8
28
2GW9 100n BGV8 27
100n 2GWA
BGV9 26
V1-TX3N 100n 2GV9
25
V1-TX3P 100n 2GVA
24
2GWB 100n BGVA 23
100n 2GWC
BGVB 22
V1-TX4N 100n 2GVB
21
V1-TX4P 100n 2GVC
20
2GWD 100n BGVC 19
100n 2GWE
BGVD 18
V1-TX5N 100n 2GVD
17
V1-TX5P 100n 2GVE
16
2GWF 100n BGVE 15
100n 2GWG
BGVF 14
V1-TX6N 100n 2GVF
13
V1-TX6P 100n 2GVG
12
2GWH 100n BGVG 11
100n 2GWJ IGVC
BGVH 10
V1-TX7N 100n 2GVH
9
V1-TX7P 100n 2GVJ
8
100n BGVK 7
2GWK 10p
SCL-DISP
SAMSUNG SHARP 3GWD 10R
6
5
2GWL 10p
4
SDA-DISP 3GWE 10R
3
2
1
CTRL-DISP3 3GWF 100R IGVD
9GV1 2GWM 1n0
SPLASH-ON FGV6 3GV9 IGV3
BL-ON FGV7 3GVA 100R IGV4
CTRL-DISP1 100R FGV1 3GVB IGV5
CTRL-DISP2 FGV0 100R 3GWG IGV6
SCL-DISP FGW0 3GVD 100R IGV7
SDA-DISP FGVZ 10R 3GVE IGV8
10R
FGV4 3GVF
3D-LED_3D-RF

2GVM
2GVN

2GVR
2GVK

2GVP
2GVL
100p

100p

100n

100n
10p

10p
100R
3GVC
CTRL-DISP3 FGV8 RES
100R
FGUA FGUB FGUC FGUD FGUE
3D-LR-DISP FGV9 3GWH 100R

4 2011-12-22

V-by-One out
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 86

10-1-17 B04C, V-disp output

V-disp output
B04C B04C
1 9GS1-1 8
RES
2 9GS1-2 7
RES
3 9GS1-3 6
RES
4 9GS1-4 5
RES
1 9GS2-1 8
RES
2 9GS2-2 7
RES
3 9GS2-3 6
RES FGS1
4 9GS2-4 5
RES

8
3 7
2 6
7GS1 1 5
SI4835DDY-GE3 FGS2
1GS1
RES 6 +VDISP
7GS2
5

4
SI3443CDV T 3.0A 32V
+12V 2
4 1
+3V3

3GS1

2GS1

2GS2

100n
RES
47R

22u
RES 4

RES
3
2GS3 RES RES
7GS3-2 2GS4 2GS5 IGS1
3GS2
3GS3

5
4K7

22n PUMD12
47R 1u0 IGS2 100n
3 IGS3
IGS4 3GS4 6GS1
IGS5 3GS5 DBG
47K DBG IGS6

3GS6
6

27K
4K7 LTST-C190KGKT

RES 3GS7
22K
LCD-PWR-ONn 2 7GS3-1
PUMD12
1

VDISP-SWITCH
RES
7GS4
PDTC114EU 3
IGS7
+2V5 1

7GS5
PDTC114EU 3
RES
1

+1V1-FD
220u 2V0

220u 2V0
RES 2JW1

2JW2

4 2011-12-22

V-disp output
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 87

10-1-18 B04D, Connector - Backlight

Connector backlight
B04D B04D
IGD1 3GD1
SDA-BL
10R

2GD1

10p
IGD2 3GD2
SCL-BL
10R

2GD2

10p
FGDC 3GD3-3
BL-SPI-CLK 3 6
100R

2GD3

10p
1G53
FGDD 1
BL-SPI-SDO 2 3GD3-2 7 FGD3 2
100R 3

2GD4
FGD4 FGD5 4

10p
5
FGD6 6
FGD7 7
8
FGD8 9
10

2GD5
FGD9 11

1u0
12
FGDA 13
14
FGDG 15
16 17

9GD1
FH52-15S-0.5SH

FGDE 3GD3-1
BL-SPI-CS_BL-I-CTRL 1 8
100R
2GD6

10p

1GD1
FGDB 3GD6
BL-DIM T 1.0A 63V
100R
2GD7

10p

3GD7
DBG

LTST-C190CKT
DBG
IGD3 330R
BKLGON-FUS

6GD1
3GD8 7GD1
BL-SPI-CLK-FUS RT9715EGB
10R
BL-SPI-CLK +3V3 5 3
VIN FLG
3GD9
BL-SPI-SDO-FUS
10R 4 1
EN VOUT
2GD8
10u

BL-SPI-SDO EN
3GD5

2GD9
GND

10u
BL-SPI-CS_BL-I-CTRL-FUS
10R
BL-SPI-CS_BL-I-CTRL
2

4 2011-12-22

Connector backlight
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 88

10-1-19 B04E, Tuner CVBS Debug

Tuner CVBS debug

B04E B04E

+5V

RES

3FW4 RES
3FW3

470R
10K
4
IFW1 7FW1-2 2FW3
6 RES
BC847BPN(COL)
5
2FW4 7FW1-1 RES 33p
CVBS-OUT1 RES 2 BC847BPN(COL)
IFW2 RES 3
47u
1
3FW5
RES
3FW8
RES IFW3 5FW3 RES DFW1

IFW4 150R IFW5 75R 1u8

3FW6

RES 3FW7

2FW5

2FW6
150R

100p

270p
10K

RES
RES

RES
DFW2

4 2011-12-22

Tuner CVBS debug

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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 89

10-1-20 B04F, Audio - Video

Audio - video
B04F CVBS1
3VWM
2VW1

100n
2VW2
CVBS B04F
SC1-CVBS 150R CVBS3
3VWN 100n
2VW3
G1-VGA 150R Y-G1
3VWP 100n
150R 2VW4
B1-VGA PB-B1
3VWR 100n
2VW5
R1-VGA 150R PR-R1
3VWS 100n
150R 2VW6
Y1-IN Y-G2
3VWT 100n
150R 2VW7
PB1-IN PB-B2
3VWU 100n
150R 2VW8
PR1-IN PR-R2
3VWV 100n
150R 2VW9
SC1-G Y-G3
100n
2VWA
SC1-B PB-B3
100n
2VWB
SC1-R PR-R3
100n

SC1-STATUS 9VW4 FS1

3VWW
SC1-BLK FB1
10K
3VW3 IVW1 2VWC
YPBPR-RIN AR-1
8K2 1u0

3VW4

33K
3VW5 IVW2 2VWD
YPBPR-LIN AL-1
8K2 1u0

3VW6

33K
3VW7 IVW3 2VWE
SC-RIN 9VW5 AR-4
8K2 1u0

3VW8

33K
3VW9 IVW4 2VWF
SC-LIN 9VW6 AL-4
8K2 1u0

3VWA

33K
V-SYNC-VGA 9VW1 PCVS

H-SYNC-VGA 9VW2 PCHS

RES 3VWB IVW5 2VWG RES

AR-6
8K2 1u0

RES 3VWC

33K
RES 3VWD IVW6 2VWH RES
AL-6
8K2 1u0

RES 3VWE

33K

+3V3
3VWF

4K7

AUDIO-MUTEn
RES 3VWG
4K7

3VWH IVW7 2VWJ

VGA-LIN AL-3
8K2 1u0
RES 3VWJ
33K

3VWK IVW8 2VWK

VGA-RIN AR-3
8K2 1u0
3VWL

33K

4 2011-12-22

Audio - video
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 90

10-1-21 B04G, EMMC

EMMC
B04G +3V3 +3V3 B04G

2EJ1

2EJ2

2EJ3

2EJ4

2EJ5

2EJ6
100n

100n

100n

100n

100n

100n
+3V3

+3V3

3EJ1

4K7
7EJ0-1

J10
M4
C6

N4
P3
P5

E6

K9
F5
H26M21001ECR
VCCQ VCC 3EJ2-2
SDIO1-CMD FEJ2 M5 CMD 0
A3 FEJ3 SDIO1-D0 SDIO1-D0 2 7
A4 FEJ4
SDIO1-CLK FEJ1 M6 CLK
MAIN 1
2
A5 FEJ5
SDIO1-D1
SDIO1-D2
4K7
3EJ2-3
B2 FEJ6 SDIO1-D3 SDIO1-D1 3 6
3EJ0 3
+3V3 FEJ0 K5 DATA B3
4K7
RST 4
RST 10K B4
5 3EJ2-4
VDDI C2 B5 SDIO1-D2 4 5
VDDI 6
B6
7 4K7
VSS VSSQ 3EJ2-1

2EJ7

100n
SDIO1-D3 1 8

G5
E7
K8
H10

C4
N2
N5
P4
P6
4K7

SDIO1-CLK
SDIO1-CMD

+3V3 +3V3 +3V3

M10
M11
M12
M13
M14

N10
N11
N12
N13
N14

P10
P11
P12
P13
P14
7EJ0-2 M3
M7
M8
M9

N1
N3
N6
N7
N8
N9

P1
P2
P7
P8
P9
H26M21001ECR
NC
A1 H1
SDIO1-D3 A2 H2
A6 H3
A7 H5
+3V3
A8 H12
A9 H13
A10 H14
A11
A12
NC J1
J2
A13 J3
A14 J5
B1 J12
B7 J13 +3V3
+3V3
B8 J14
B9 K1
B10 K2 RST
NC NC
B11 K3
B12 K6
B13 K7
B14 K10
VDDI C1 K12
C3 K13
C5 K14
C7 L1
C8 L2
C9 L3
C10 L12
C11 L13
C12 L14
C13 M1
C14 M2

NC
D1
D2
D3
D4
D12
D13
D14
E1
E2
E3
E5
E8
E9
E10
E12
E13
E14
F1
F2
F3
F10
F12
F13
F14
G1
G2

G12
G13
G14
G3
G10

4 2011-12-22

EMMC
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 91

10-1-22 B04H, Second source DC-DC converters

Second source DC-DC converters

B04H B04H
5UR3

30R
5UR1 IUR0 IUR2
+12Vb 3UR3-1
33R
30R

2UR5

2UR6

100n
3UR3-2

10u
2UR7
33R

10u
2UR0 2UR4 IUR8 5UR2 FUR1
3UR3-3 +5V

22
23
24
25
26
33R 7URA-2
1n0 1n0 3u6

2UR8

2UR9
3UR3-4 RT8288AZSP

22u

22u
33R VIA
2UR3
18 10
IUR9 100n
7URA-1 19 11
RT8288AZSP 20 VIA VIA 12

7
VCC IUR3 21 13
2UR1
1 4
VIN BOOT
100n
3UR4 VIA
2
SW 3 1M0

14
15
16
17
DETECT12V 5 IUR4
EN 3UR5
6 +5V
FB
68K 1%
GND

12K 1%
GND HS

3UR6
2UR2

3UR7
8

1M0
1n0

5UR5 IURA
+12Vb
30R
2URA

2URB

100n
22u

5UR6 FURA
IURB +3V3
10u

2URC

2URD
22u

22u

22
23
24
25
26
7UR6-1 7UR6-2
RT8293AHGSP RT8293AHGSP
IURC 2URE VIA
2 1
VIN BOOT
18 10
100n
7 3 19 11
EN SW VIA
IURD IURE 20 VIA 12
3URA
8 5 +3V3 21 13
SS FB
IURK 68K 1%
3URC RES

6
COMP VIA
22K 1%
2URF

10n

GND
3URB

GND HS
1M0
2URG

14
15
16
17
4

3n3

ENABLE+3V3 CUR5
RES 2URH

100p

IURF
2URJ

1n0

GND-3V3r GND-3V3r
3URF

13K

GND-3V3r GND-3V3r

GND-3V3r
GND-3V3r GND-3V3r
4 2011-12-22

Second source
8204 000 9229
DC-DC converters

19210_027_120424.eps
120424

2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 92

10-1-23 B04I, IR Debug

IR debug
B04I B04I

ICVW 7CVW
+3V3-STANDBY 3CVW 100R 2
VS
RC_IRQ-RF4CEn 3CVY 10R 3
OUT
1
GND1

2CVW

1u0
4
GND2
TSOP75236

4 2011-12-22

IR debug
8204 000 9229

19210_028_120424.eps
120424

2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 93

10-1-24 B05A, Class-D amplifier

Class-D amplifier
B05A B05A

3D60 A-STBY
+3V3D +12V-AUDIO +12V-AUDIO
10K
3

RESET-FUSION-OUTn 1 7D70
PDTC144EU

2D97

2D96

2D84

2D92
2D60

2D61

2D62

5D50

2D63

2D66

2D57

2D58

2D59

2D64

2D65

5D51
220n

220n

220n

220n
2

30R

30R
10u

10u

10u

10u

10u

10u

10u

10u

10u

10u
2D49 2D48
3D61
100u 16V ID54 ID55 16V 100u

2D93 RES
100u 16V

100u 16V
2D67 1u0

1u0
10R 5D85

2D5C
2D5A

3D78

3D82
10K

10K
3D62 AUDIO-MUTE +3V3D +3V3

2D86

2D68

2D69
100n

100n
10u
+3V3D 30R
10K
3 SPEAKER-L- SPEAKER-R-
AUDIO-MUTEn +3V3D 3D58

9D50
ID78

RES
1 7D71 RES

100u 16V

100u 16V
2D5D
2D5B

3D79

3D83
PDTC144EU 1R0

10K

10K
2
+3V3D 3D57 ID77 ID76 ID75 TAS5731P1
7D60
1R0 TAS5711PHP

13

27

32

44
45

40
41

34
35
5

2
3
2D72
9D52 AVDD DVDD OUT A B C D
RES 3D63 WSI2SOUT FD67 20 GVDD PVDD
LRCLK 10u
I2SCLK FD63 RES FD64 21 ID50 5D70 5D00
9D53 SCLK ID79 2D74 ID88
10R SCKI2SOUT FD65
9D54
FD66 15
MCLK AUDIO VR_DIG
18 SPEAKER-L+
SDI2SOUT1 22
SDIN AMPLIFIER 31 ID80 2D77 100n 10u 30R
+3V3D FD50 VREG

3D73

2D71

2D78
220n
+3V3-STANDBY

18R

10n
3D55 100n
SDA-SSB 23 1
SDA OUT_A
SCL-SSB 3D56 47R 24
SCL 2D79
47R 3D76 RES 4 ID81
+3V3D BST_A
3D50

10K
10K

33n 2D80

2D75

2D56
9D55

330p

220n
SDI2SOUT3 ID89 ID90 14 43 ID82
A_SEL BST_B FD69
3D54

ID91
47K

RES 33n SPEAKER-L+

3D77 46
ID56 OUT_B 5D71
D-RESET D-RESET 15K 25
RESET

2D99

2D98

2D70
19

10n

10n

10n
PDN 30R SPEAKER-L-
ID87 7D50-2 39 1D01 1D02
OUT_C
PUMH2
2D50 ID66 ID62 ID51 5D74 5D75 Left+ FD30 1 5D78
1
2D82 FD31

2D73

5D81
ID65 12 42 ID93 ID94 Left- 30R ID57

30R
10n
VR_ANA BST_C SPEAKER-L- 2 2
11 ID63 10u SPEAKER-R+ Right+ 3 3
4n7 PLL_FLTP 2D85 33n 3D74 2D94 30R 5D72
DETECT12V 7D50-1 10 33 FD32 Right- 4
PUMH2 3D51 PLL_FLTM BST_D
2D51 18R FD33 30R FD70 2041145-3
33n 330p

2D76
47n 36 2041145-4

10n
470R OUT_D ID52 5D76 5D01
3D52 2D52 ID96 SPEAKER-R+
ID58 3D70 RES

2D87

1D52

1D50

1D51
7 ID83

10n
A-STBY 470R 47n ID69 ID97 OC_ADJ 10u 30R
8 16 ID84 3D71 22K SPEAKER-R-
2D53 PBTL OSC_RES

3D75

2D83

2D55

2D81
220n

220n
9D51

18R

10n
18K2
ID61 ID70 50
4n7 2D54

2D89

1D53

1D54

1D55

1D56
220n
AUDIO-MUTE 6 51 ID53
SSTIMER
52
2n2 53
2D95
26 54
STEST

3D72
55

18R
330p
56
57 5D79 5D80
58 ID98 ID99 SPEAKER-R-
59
VIA 10u 30R

2D88

330p
60

2D91

5D83
61

30R
10n
62
63
64
65
66 5D77
67
68
PGND 30R
VSS 69 +3V3D
AGND GND A D DO AB CD GND_HS
30

29

28

17

47
48

37
38

49
ID59
CD00

3D80
1D35

4K7
FD52
1
FD51 2
3D81
SPEAKER-DETECTn 3
ID85 100R
4 5

2D90

100n
502386-0370

1X02
REF EMC HOLE

4 2011-12-16

Class-D amplifier
8204 000 9220

19210_029_120424.eps
120424

2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 94

10-1-25 B05B, Analogue externals

Analogue externals
B05B B05B

3VA7 FVA9
R1-VGA SC-RIN

CDS4C12GTA

CDS4C12GTA
RES

RES
1K0

1VAG
1VAA
2VA0

3VA2

2VA8

2VA9
150R

100p
12V

12V
47p

6n8
6VA0

6VA8
3VA8 FVAA
G1-VGA SC-LIN

CDS4C12GTA

CDS4C12GTA
RES

RES
1K0
SCART

1VAH
1VAB

2VAA

2VAB
2VA1

3VA3

150R

100p
12V

12V
47p

6n8
49045-0011

6VA1

6VA9
25 26
FVCG
24
23
FVAB 22
B1-VGA SC1-B 21

CDS4C12GTA

CDS4C12GTA
RES

RES
20
19

3VAG
1VAC

2VAC
2VA2

3VA4

150R

1VAJ
100p

75R
12V

12V
47p
18
17
VGA

6VAA
6VA2
FVA2
16
FVCF
FVA1 FVA3 15
1VA5
14
1 3VAH IVA0 3VA9 FVAC 13
2 H-SYNC-VGA SC1-STATUS 12

PDZ2.4B(COL)
CDS4C12GTA

CDS4C12GTA
RES

RES
3 100R 12K 11
4 FVA6 10

1VAD

2VAD
6VAB

3VAA

2VAE

1VAK
2VA3

3VA5

100p
12V

4K7

1K5

12V
47p

1u0
5 9
6 8

6VAC
6VA3
7 7
FVA0 6
8
9 5
10 3VAJ FVA4 4
11 FVA5 V-SYNC-VGA SC1-G 3

CDS4C12GTA

CDS4C12GTA
RES

RES
12 100R 2
13 FVA7 1

1VAE

3VAB
2VAF
2VA4

3VA6

1VAL
100p

75R
12V

12V
4K7
47p
14
1VA1
15

6VAD
6VA4
16
17 FVCE
FVA8
1216-02D-15L-2EC
3VA0 RES FVAD
VGA-SDA-EDID-HDMI SC1-R

CDS4C12GTA

CDS4C12GTA
RES

RES
10K

1VAM
2VAG

3VAC
2VA5

100p

75R
12V

12V
47p

6VAE
6VA5
CVBS1 CVBS1

PR1-IN PR1-IN
3VA1 RES FVAH IVA1 3VAD FVAE
VGA-SCL-EDID-HDMI SC1-BLK

PDZ2.4B(COL)
CDS4C12GTA

CDS4C12GTA
RES

RES
10K 100R

2VAH

1VAN
3VAE
6VAF
2VA6

100p
75R
12V

12V
47p

DRX0+ C2S1 GND

6VAG
6VA6

DRX0- C2S2 Y1-IN

DRX1+ C2S3 GND

FVAF
DRX1- C2S4 YPBPR-RIN +5V-VGA SC1-CVBS
CDS4C12GTA

CDS4C12GTA
RES

RES

1VAP
1VAF

3VAF
2VA7

2VAJ

150R
100p
C2S5
12V

12V
47p

DRX2+ GND
DRX2- C2S6 YPBPR-LIN

6VAH
6VA7

DRXC+ C2S7 GND

DRXC- C2S8 PB1-IN
3VAK FVAG
SC1-DETECTn
47R

2VAK

100p

4 2011-12-16

Analogue externals
8204 000 9220

19210_030_120424.eps
120424

2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 95

10-1-26 B06A, HDMI

HDMI
B06A B06A
1H05 6HA0

1 ERX2+ +5V +5V-VGA

2
3 ERX2- BAT54 COL 5HA2 pins (35,88)

3HBM
FHAB

4K7
4 ERX1+ +1V2-FE VDD12
FHAY 3HA0
5 AIN-5V 30R

2HB1

2HB2

2HB3
100n

100n
10u
6 ERX1- 10R

3HAN
2HA5

1 3HA1-1 8

10R
1u0
7 ERX0+ VGA-DETECT
EIN-5V

4K7
8
9 ERX0- 2HA6

3HBN
HDMI CONNECTOR 5

8K2
10 ERXC+ FHAC

1 3HAA-1 8
11 3HA2 1u0
FHB0

47K
12 ERXC- BIN-5V
13 PCEC-HDMI 10R I2C ADDRESS 5HA3 pin (79)

2 3HA1-2 7
HARC3 FHAA
14 TVDD12
0XB2

2HA4
FHAJ

4K7
+5V-EDID

1u0
15 ERX-DDC-SCL ERX-DDC-SCL 30R

2HAW

2HAY

2HB0
100n

100p
FHAK

10u
16 ERX-DDC-SDA ERX-DDC-SDA
17

7 3HAA-2 2
18 EIN-5V 3HA3
FHB1

47K
FHAD 19 ERX-HOTPLUG CIN-5V
21 20 10R

3 3HA1-3 6
23 22 FHB4 MICOM-VCC33

2HA2

4K7
1u0
5HA4 pin (25) pin (98)

3HAP
2HB4
EIN-5V FHA9

10K
10u
+1V2-FE AVDD12
VDD33 EPWR33 SBVCC5 VDD12
3HA4 30R

2HAR

2HAU
2HAS

2HAV
2HAT
100n

100n

100n

100n
1H04 FHB2

10u
DIN-5V
DDRX2+ 10R AVDD12 TVDD12
1

4 3HA1-4 5
2

2HA1

4K7
1u0
3 DDRX2-
DDRX1+ +5V +3V3
4
5 7HA0

16
34
89

43

52

64

25
98

35
88

79
SII9387ACTUC

7
DDRX1-

3HA5 RES
6 3HA8
FHB3 33 VCC33 VCC5 VDD12 TVDD12

PDZ2.4B(COL)
7 DDRX0+
DIN-5V
EIN-5V
10R 66
VDD33 EPWR MICOM SB AVDD12
+3V3
5HA5
FHA8 pins (7,16,34,89) VDD33
8 CEC_A

6HA1

5HA9

30R
3K3
9 DDRX0- 7HA5 30R

2HAM
RES 2HAH

2HAN
RES 2HAK

2HAP
HDMI CONNECTOR 4

2HA0

3HA9

2HAL
2HAJ
100n

100n

100n

100n

100n
47 RT9715EGB

4K7
1u0

10u

10u
10 DDRXC+ R0PWR5V

7 3HAC-2 2
51
11 R1PWR5V
56 5 3

47K
12 DDRXC- R2PWR5V VIN FLG
PCEC-HDMI 75
13 R3PWR5V
HARC2 60
14 R4PWR5V

3HA6

2HB5
FHAL 65 4 1

2K2

1u0
15 DRX-DDC-SCL DRX-DDC-SCL +5V-EDID R5PWR5V_VGA EN VOUT
DRX-DDC-SDA DRX-DDC-SDA FHAM
16 5HA0 RES 5HA1 RES EN
ARC-SiI FHA0 63
17 HDMI_RSVD RES

1 3HAC-1 8
2HA7 10p GND
18 DIN-5V FHB7 RES
30R 1u0
46
5HA6
FHA7 pin (43)
47K
FHAE 19 DRX-HOTPLUG ARX-HOTPLUG CBUS_HPD0 EPWR33
21 20 BRX-HOTPLUG FHB8 50

2
CBUS_HPD1 30R

2HAG
2HAF

100n
FHB9 55

10u
23 22 CRX-HOTPLUG CBUS_HPD2 RES
74 RES
DRX-HOTPLUG FHBA CBUS_HPD3
ERX-HOTPLUG 59
CBUS_HPD4
DIN-5V FHBB
40 37
2HA8 RES HECN ETH_RX1P
1H03 39 38
HECP ETH_RX1N
1 CRX2+ 1u0
44 41
2
CRX2-
ARX-DDC-SDA
ARX-DDC-SCL 45
DSDA0 ETH_TX1P
42 3HAR RES
+5V
3HAS FHA6 pin (64) SBVCC5
3 DSCL0 ETH_TX1N
4 CRX1+ 75R RES 10R
RES

2HAD

2HAE

100n
90

10u
5 ARXC- R0XCN 2HAC
91 36 3HAT
6 CRX1- ARXC+ R0XCP SPDIF_IN SPDIFO
CRX0+ ARX0- 92 390R
7 R0X0N 100n
CIN-5V ARX0+ 93
8 R0X0P RES
CRX0- 71 3HAV 47R SCL-SSB
9 CSCL 3HAU
HDMI CONNECTOR 3 10 CRXC+ ARX1- 94
R0X1N CSDA
70 3HAW 47R SDA-SSB
3 3HAA-3 6

ARX1+ 95 75R
11 R0X1P FHA1 3HBR
96 69
47K

12 CRXC- ARX2- R0X2N GPIO_MCON +3V3

PCEC-HDMI ARX2+ 97 68 FHA2 3HB0 MICOM-VCC33
13 R0X2P RESET 22K
HARC1 4K7 7HA4
14 3HBP
CRX-DDC-SCL CRX-DDC-SCL FHAN BRX-DDC-SDA 48 BC847BW
15 DSDA1 FHA4 3HB1 RES
CRX-DDC-SDA CRX-DDC-SDA FHAP BRX-DDC-SCL 49 76 RES
16 DSCL1 TPWR_CI2CA 10K
67 3HAY 4K7 FHA5 RESET-HDMI-MUXn
17 INT +3V3 4K7
5 3HAA-4 4

CIN-5V BRXC- 99
18 R1XCN FHA3 RES
100 9HA1
47K

FHAF 19 CRX-HOTPLUG BRXC+ R1XCP

21 20 BRX0- 1 87 HDMIF-RXC-
R1X0N TXCN +1V5 +5V
23 22 BRX0+ 2 86 HDMIF-RXC+ +3V3
R1X0P TXCP
85 HDMIF-RX0- 2HAB
TX0N
BRX1- 3 84 HDMIF-RX0+
R1X1N TX0P
CIN-5V BRX1+ 4
R1X1P 1u0
BRX2- 5 83 HDMIF-RX1- 7HA1-1
R1X2N TX1N
1H02 6 82 RT9025-12GSP

4
BRX2+ R1X2P TX1P HDMIF-RX1+
BRX2+ 81 HDMIF-RX2- VDD
1 TX2N
CRX-DDC-SDA 53 80 HDMIF-RX2+ 3 6 FHB5 +1V2-FE
2 DSDA2 TX2P VIN VOUT
BRX2- CRX-DDC-SCL 54
3 DSCL2
BRX1+ 2 7
4 EN ADJ

2HAA
8 77

10u
5 CRXC- R2XCN RSVDL1
BRX1- CRXC+ 9 78 1
6 R2XCP RSVDL2 PGOOD

2HA9
10

10u
7 BRX0+ CRX0- R2X0N
BIN-5V CRX0+ 11 5
8 R2X0P NC
BRX0- 102 GND
9
HDMI CONNECTOR 2

22
23
24
25
26
BRXC+ CRX1- 12 103 GND HS 7HA1-2
10 R2X1N
1 3HAB-1 8

RT9025-12GSP

9
CRX1+ 13 104
11 R2X1P
14 105
47K

12 BRXC- CRX2- R2X2N VIA

PCEC-HDMI CRX2+ 15 106
13 R2X2P
HARC0 107 18 10
14
BRX-DDC-SCL BRX-DDC-SCL FHAR DRX-DDC-SDA 72 108 19 11
15 DSDA3 VIA
BRX-DDC-SDA BRX-DDC-SDA FHAS DRX-DDC-SCL 73 109 20 VIA 12
16 DSCL3
VIA 110 21 13
17
7 3HAB-2 2

BIN-5V DDRXC- 3HB5 17 111

18 R3XCN
3HB6 4R7 18 112
47K

FHAG BRX-HOTPLUG DDRXC+ VIA

19 R3XCP
21 20 DDRX0- 3HB7 4R7 19 113
R3X0N
23 22 DDRX0+ 3HB8 4R7 20 114
R3X0P

14
15
16
17
4R7 115
DDRX1- 3HB9 21 116
R3X1N
BIN-5V DDRX1+ 3HBA 4R7 22 117
R3X1P
DDRX2- 3HBB 4R7 23
R3X2N
1H01 DDRX2+ 3HBC 4R7 24
R3X2P
ARX2+ 4R7
1
2 ERX-DDC-SDA 57
DSDA4
1V2 DVB-T2 and HDMI 5-1 mux (8000 and 9000 series)
ARX2- ERX-DDC-SCL 58
3 DSCL4
4 ARX1+
ERXC- 3HBD 26
5 R4XCN
ARX1- ERXC+ 3HBE 4R7 27
6 R4XCP
ARX0+ ERX0- 3HBF 4R7 28
7 R4X0N
AIN-5V ERX0+ 3HBG 4R7 29
8 R4X0P 3HB2
ARX0- 4R7 RES
9 +3V3-STANDBY
HDMI CONNECTOR 1 10 ARXC+ ERX1- 3HBH 30
R4X1N 22K
3 3HAB-3 6

ERX1+ 3HBJ 4R7 31 7HA2

11 R4X1P
3HBK 4R7 32
47K

12 ARXC- ERX2- R4X2N BC847BW

PCEC-HDMI ERX2+ 3HBL 4R7 33 RES
13 R4X2P
HARC4 4R7
14
ARX-DDC-SCL ARX-DDC-SCL FHAV VGA-SDA-EDID-HDMI 61
15 DSDA5_VGA
ARX-DDC-SDA ARX-DDC-SDA FHAW VGA-SCL-EDID-HDMI 62
16 DSCL5_VGA
17 3HB3
5 3HAB-4 4

7 3HAL-2 2

AIN-5V GND_HS PCEC-HDMI 9HA0 HDMI-CEC

3HAL-1

18
101
47K

47K

47K

FHAH 19 ARX-HOTPLUG 100R

FHB6
21 20
BC847BW
23 22
8

7HA3

3HBS

27K
+5V-EDID
AIN-5V

1X09 1X08 1X01 3HB4

REF EMC HOLE EMC HOLE REF EMC HOLE +3V3-STANDBY
22K

5 2011-12-06

HDMI
8204 000 9223

19210_031_120424.eps
120424

2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 96

10-1-27 B06B, HDMI-ARC

HDMI-ARC
B06B B06B
5HD6
+3V3 IHDM +3V3-ARC
30R
+3V3-ARC

2HDC
3HD0

680R

10u
2HD7
IHD0 7HD1-1
BC847BS(COL)
100n 3HD1
IHD9 IHDF ARC0
9HD4 56R

3HD4

100R
3HD2

3HD3

330R
2K2
FHD4 5HD0
HARC0 ARC0 +3V3-ARC +3V3-ARC
30R
FHD5 5HD1
HARC1 ARC1

3HD5

680R
30R
FHD6 5HD2
HARC2 ARC2
30R
FHD7 5HD3 2HD8
HARC3 ARC3 IHD1 7HD1-2
BC847BS(COL)
30R 100n 3HD6
IHD8 IHDG ARC1
FHD8 5HD4
HARC4 ARC4 9HD5 56R
30R

3HD9

100R
3HD7

3HD8

330R
2K2
+5V-ARC
2HD0

2HD1

2HD3

2HD4

2HD5
10p

10p

10p

10p

10p

5HD5
FHD3 +3V3-ARC +3V3-ARC
+5V
30R

2HDD
2HD6

100n
1u0

3HDA

680R
7HD0 2HD9

16
74HC4051PW IHD2 7HD2-1
VCC BC847BS(COL)
100n 3HDB
FHD0 11 13 IHD7 IHDH
ARC-SEL0 0 MDX 0
9HD6 56R
ARC2

ARC-SEL1 FHD1 10 0 14
8X 1

3HDE

100R
7

3HDC

3HDD

330R
FHD2 9 15

2K2
ARC-SEL2 2 2
9HD0 6 12
G8 3
1
4

HDMI-ARC 3 5 +3V3-ARC +3V3-ARC

5
2
6

3HDF
9HD1

680R
4
7
VEE
7 GND

8
2HDA
IHD3 7HD2-2
BC847BS(COL)
100n 3HDG
IHD6 IHDJ ARC3
9HD7 56R

3HDK

100R
3HDH

3HDJ

330R
2K2
+3V3-ARC +3V3-ARC

3HDL

680R
2HDB
IHD4 7HD3
BC847BW
100n 3HDM
IHD5 IHDK ARC4
9HD8 56R

3HDS

100R
RES 3HDN

3HDR
3HDP

330R
82R

2K2
RES
HDMI-ARC IHDL 9HD2 ARC4

3HDT

100R
RES
5 2011-12-06

HDMI-ARC
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 97

10-1-28 B06C, USB

USB
B06C +5V
B06C
+3V3 +3V3-USBS

RES
9EA3

9EA4

9EA5
2EA3

100n

2EA4

2EA5

2EA6

2EA7
100n

100n

100n

100n
3EA7
2EA0 +5V
+T 0R4
18p 3EA8-1
7EA0 +5V-PORTA

27

14

21
1EA0
CY7C65632-28LTXCT

12M

5
9
NC
100K

VCC

VCC_A_1
VCC_A_2
VCC_A_3

VCC_D
FEAD 3EA8-2
10 USB-PORTA-OC
2EA1 XIN
100K
11
18p XOUT 3EA8-3
1 USB-MAIN-DM
D-
USB-PORTB-DM 3 2 USB-MAIN-DP 100K
DD1- D+
USB-PORTB-DP 4
DD1+ +3V3 3EA8-4
USB-PORTB-OC 25
OVR1
RES 100K
USB-PORTA-DM 6 26 3EA6
DD2- SDA +3V3
USB-PORTA-DP 7 10K
DD2+

9EA1
RES
USB-PORTA-OC 24
OVR2

USB-SET-DM 12
DD3-
USB-SET-DP 13 18
DD3+ TEST|SCL
3EA0 20 IEA3 3EAC
+3V3 OVR3
10K
+5V

9EA2
RES
15 +T 0R4
DD4-
16
DD4+ 3EAD-1
3EA1 19
+3V3 OVR4 +5V-PORTB
10K 30 100K
VIA1
3EA2 RES 28 31
VREG VIA2 FEAE 3EAD-2
RESET-FUSION-OUTn RESET-FUSION-OUTn 17 32 USB-PORTB-OC
+3V3 RESET VIA3
3EA3 IEA1 22 33
10K +3V3 SELFPWR VIA4 100K
10K 23

GND_HS
3EA4 GANG 3EAD-3
RES 2EA8

8
10n

RREF
680R IEA2 100K

100K
3EAD-4

29
+3V3-USBS
100K
2EA2

100n

3EA5

3ECH
+5V
+T 0R4

+5V-HDD

1E01
FEA1
+5V-HDD 1E03
FEA2 1 FEA6
USB-HDD-DM 2 FEA7 +5V-PORTA 1
USB-HDD-DP 3 USB-PORTA-DM 2
FEA3 4 USB-PORTA-DP 3
5 6 FEA4
FEA8 4 FEA5
2EA9

100n

5 6
5401-3C2-100-70

2EAA

100n
5401

1E02
FEA9
FEAA +5V-PORTB 1
USB-PORTB-DM 2
USB2-DM cEC0 USB-HDD-DM USB-PORTB-DP 3
FEAB 4 FEAC
5 6

2EAB

100n
USB2-DP cEC1 USB-HDD-DP
5401

USB1-DM cEC2 USB-MAIN-DM

USB1-DP cEC4 USB-MAIN-DP

5 2011-12-06

USB
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 98

10-1-29 B06D, Service

Service
B06D B06D

TXD-HTV-TTL

RXD-HTV-TTL

RXD-HTV-TTL

TXD-HTV-TTL

TXD-HTV-RS232

RXD-HTV-RS232
+3V3

FCS3 FCS4

3CS1

3CS0
1CWE

10K

10K
FCS5 1
2
3
5 4
FCS2
BM03B-SRSS-TBT
5 1E06
FCS1 FCS0 4
3CS2 7 3CS4-2 2 4 3CS4-4 5 RXD-HTV-RS232 3
RXD-SERVICE
47R 3CS3 47R 47R
TXD-SERVICE 6 3CS4-3 3 1 3CS4-1 8 TXD-HTV-RS232 2
47R 47R 47R 1
MSJ-035-75C-B-RF-PBT-BRF

PDZ5.1B(COL)

PDZ5.1B(COL)
6CS1

6CS0

1CS1

1CS0
+3V3
HOTEL TV
9CS1

7CS1
16

ST3232C

VCC
2CS0
1 RS232
C1+ 2CS1
6
100n V-
3
C1- 100n 2CS2
2
2CS3 V+
4
C2+ 100n
100n
5
C2-

TXD-HTV-TTL 11 14 TXD-HTV-RS232
T1 T1
10 IN OUT 7
T2 T2

RXD-HTV-RS232 13 12 RXD-HTV-TTL
R1 R1
8 IN OUT 9
R2 R2
GND
15

5 2011-12-06

Service
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 99

10-1-30 B06E, Ethernet

Ethernet
B06E B06E
5EF5

2EFS

2EFT
10n

10n
30R
RES 5EF0 VDD33-PHY
+3V3-STANDBY VDD33-PHY FEF9
IEF1
30R
5EF4 AVDDL-1V1
+3V3-LAN

2EFH
2EF0

2EF1

2EF2

2EF3
100n

100n

100n
1u0

10u
30R

FEF0

5EF6

2EF5

2EF6

2EF7

2EF8
100n

100n

100n

100n
RES 30R
3EF0
VDD33-PHY
100K

2EFA
2EF4

5EF1

2EF9

2EFJ
RES 100n

100n

100n
4u7

10u
FEF1 7EF0 VDDH-2V5

11
17

14

38
2EFB AR8030-AL1A-R

3
22p

AVDD33

VDD33

DVDDL
AVDDL

3EFY
1EF0

1M0
5 2
XTLI LX

25M
2EFC 4 8 FEF8
22p XTLO VDDH_REG
FEF2
CLK-25M 3EF1 RES 23 27
CLK_25M VDDIO_REG 5EF7-1
22R
RESET-ETHERNETn FEF3 1 9 TXP 16 RD+ RX+ 1
RST TRXP0

2EFG

2EFV
2EFF

2EFZ

100n
10

1u0

1u0

22u
TRXN0 TXN

2EFU

100n
3EF2 1% FEF4 7 12 RXP 15 RDTC RXCT 2
RBBIAS TRXP1
13 RXN
2K37 TRXN1
RES0 26 14 RD- RX- 3
RES0
RES1 31 33 3EF5 CLK-RMII RES
RES1 CLK_RMII 5EF3-2
30 22R EN-RXEN 9 TD- TX- 8
CRS_DV
EN-MDC 40 1E00
MDC
3EF3 39 29 EN-RXD0 10 TCT TXCT 7
VDD33-PHY MDIO RXD0 1
EN-MDIO 1K5 20 28 EN-RXD1 TXP FEFA
INT RXD1 2
IRQ-WOLANn FEF5 TXN FEFB 11 TD+ TX+ 6
3
15 25 FEF7 RX-ER RXP FEFC
RX_ER 4
16 RES 5
VDDH-2V5 18 32 EN-TXEN 14 RD- 5EF3-1 RX- 3
TX_EN 6
19 NC RXN FEFE
7
36 34 15 RDTC RXCT 2

CDA5C16GTH

CDA5C16GTH

CDA5C16GTH

CDA5C16GTH
TXD0 EN-TXD0 8

1
37 35 EN-TXD1 9

RES 6EF2-4

RES 6EF2-3

RES 6EF2-2

RES 6EF2-1
TXD1

RES 2EFK
3EF4

RES 2EFL

RES 2EFN
16 RD+ RX+ 1

RES 2EFM
10K

16V

16V

16V

16V
15p

15p

15p

15p
LED-RES
50 21 LED-ACT 98435-111LF
LED_ACT
FEF6 51 22

8
3EG0 LED_RES

3EG1

3EG2

3EG3
2EFP

100n
52 24

75R

75R

75R
BC857BW 5EF7-2
7EF1 LED_10_100
53 11 TD+ TX+ 6
47R
54

RES

RES
VIA
55 10 TCT TXCT 7

470p

470p
56
GND_HS

57 9 TD- TX- 8

2EFD
3EF6

2EFE

2EFR
58 RES 6EF0

1n0
VIA RES VDD33-PHY
510R LTST-C190KGKT
3EF7
41
42
43
44
45
46
47
48
49

RES 6EF1 RES

VDD33-PHY
510R RES LTST-C190KGKT 5EF3-3
MGH7S
4 12 RES
5 13

DEF0
EN-TXC

CLK-RMII 9EF1
EN-RXC
CLK-25M RES 9EF2

VDDH-2V5

3EFE RES 3EFN

EN-RXD0 EN-RXD0
10K 10K
3EFF RES 3EFP
EN-RXD1 EN-RXD1
10K 10K
3EFG RES 3EFR
EN-RXEN EN-RXEN
10K 10K
3EFH 3EFS RES
RES0 RES0
10K 10K
3EFJ 3EFT RES
RES1 RES1
10K 10K
3EFK RES 3EFU
RX-ER RX-ER
10K 10K
3EFL 3EFV RES
LED-RES LED-RES
10K 10K
3EFM 3EFW RES
LED-ACT LED-ACT
10K 10K

5 2011-12-06

Ethernet
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 100

10-1-31 B06F, NAND-Flash & EEPROM

NAND-Flash & EEPROM

B06F B06F

+3V3

47u 16V
2JA0

2JA1

2JA2

2JA3
100n

100n

100n
9JA4

9JA3
+3V3

7JA0

12
34
37
39
MT29F8G08ABACAWP:C
VCC
1
1

3JA5
2

10K
2
3
3
FRA0 DJA0 29 4
0 4
FRA5 DJA1 30 5
1 5
FRA6 DJA2 31 6 9JA1 RES F-RDY
2 6
FRA7 DJA3 32 10 9JA2 RES F-CEn
3 7
FRA8 DJA4 41 IO 11
4 8
FRA10 DJA5 42 14
5 9
FRA11 DJA6 43 15
6 10
FRA12 DJA7 44 20
7 11
21
NC 12
22
13
F-RDY DJA8 7 23
R 14
B 24
15
26
16
27
17
F-OEn DJA9 8 28
RE 18
F-CEn DJAA 9 33
CE 19
NAND-ALE DJAB 17 35
ALE 20
NAND-CLE DJAC 16 40
CLE 21
F-WEn DJAD 18 45
WE 22
DJAE 19 46
WP 23
38
DNU1
3JA0

3JA1

47
4K7

4K7

DNU2
RES

VSS +3V3

13
25
36

48
+3V3 2JA4
+3V3 9JA5 IJA1

9JA6
7JA2 100n
M24C64-WDW6

3JA4

10K
(8K 8) 7
WC
EEPROM 3JA2
1
IJA0 6 SCL-SSB
0 SCL
2 47R
1 ADR 3JA3
3 5 SDA-SSB
2 SDA
47R

4
FJA0

5 2011-12-06

NAND-Flash & EEPROM

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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 101

10-1-32 B06G, Analogue externals

Analogue externals
B06G B06G
3VC6 FVC1
VGA-LIN AUDIO VGA/DVI

CDS4C12GTA
1K0

2VC8

6VC6

2VC9

1VC7
100p
5 1VA6

12V

1n0
4
3

RES
2
1
FVCB
MSJ-035-75C-BL-RF-PBT-BRF

3VC7 FVC2
VGA-RIN

CDS4C12GTA
1K0

2VCA

2VCB
6VC7

1VC8
100p
cVC0

12V

1n0
DRX0+

DRX1+ cVC1

RES
DRX2+ cVC2

DRXC+ cVC3
3VC8 FVC3
YPBPR-DETECTn
47R

2VCC

100p
FVC4
DRX0- cVC4 Y1 Y1

CDS4C12GTA
RES
2VC0

3VC0

1VC1
150R
12V
47p
YPBPR

6VC0
5 1VA8
4
FVC5
DRXC- cVC5 PB1 PB1 3

CDS4C12GTA
RES
2

2VC1

3VC1

1VC2
150R
1

12V
47p
FVCC
MSJ-035-75C-G-RF-PBT-BRF

6VC1
FVC6
PR1-IN

CDS4C12GTA
RES
2VC2

3VC2

1VC3
150R
12V
47p

6VC2 3VC9 FVC7

CVBS-DETECTn
47R

2VCD

100p
DRX1- cVC6 YPBPR-R YPBPR-R
3VC3 FVC8 CVBS +
CDS4C12GTA
RES

1K0
AUDIO CVBS / YPBPR
2VC3

2VC6

1VC4
100p

12V

1n0

5 1VA4
6VC3

4
3

3VC4 FVC9
DRX2- cVC7 YPBPR-L YPBPR-L 2
1
CDS4C12GTA
RES

1K0
FVCD MSJ-035-75C-Y-RF-PBT-BRF
2VC4

2VC7

1VC5
100p

12V

1n0
6VC4

FVCA
CVBS1
CDS4C12GTA
RES
2VC5

3VC5

1VC6
150R
100p

12V
6VC5

5 2011-12-06

Analogue externals
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 102

10-1-33 B06H, DC-DC

DC-DC
B06H B06H
5UW3 IUW8 IUW9 5UW4 FUW1
5UW0 IUW0 IUW1 5UW2 FUW0 +12Vb +3V3

2UWG RES
+12Vb +5V 30R 2u0

2UWF

100n
2UW5 RES

2UW6 RES
30R 3u6

2UWD

2UWH
2UWE
2UW2

2UWJ
2UW3 RES
100n

10u

10u

22u

22u

22u
47u 25V

47u 25V
5UW1

2UW0

2UW1

2UW4

2UW7
10u

10u

22u

22u

22u
30R 7UW1

14
7UW0 +12Vb TPS54426PWP

14
TPS54426PWP VCC
VCC 13 10
VIN SW1
13 10 11
VIN SW1 SW2

2UY6 RES
11 1 IUWC 2UWN
SW2 +3V3 VO

2UY5

100n
1 12

1u0
+5V VO IUW4 2UWB 3UW6 IUWA VBST
IUW2 12 2 IUWD
3UW0 VBST VFB 100n
2 6

BAV99 COL
VFB IUW5 100n 68K 1% IUWB PG
IUW3 6 4

3UWJ-1

3UWJ-2

3UWJ-3

3UWJ-4
120K 1% PG 2UWK RES SS IUWE 3UW9 RES

3UW8

220K
4 3

10R

10R

10R

10R
2UW8RES SS IUW6 VREG5

22K 1%
3UW4
3UW3

2UW9470K

3 7 100K
VREG5 2UY1 2UY2 22p EN
22K 1%

6UW2

3UW7

2UWL
7 100K 16

10n
22p EN

2UWM
RES

2UWP
3UW2

RES
16 17
10n

1n0

1u0
100n 100n

2UWC
2UWA
RES

17 18
1n0

1u0
18 19
19 20
GND-3V3
20 21
GND-5V VIA
21 22
VIA FUW4 GND-3V3 GND-3V3 GND-3V3
22 23
GND-5V GND-5V GND-5V +22V

2UY4 RES
23 24

2UY3
24 25

1u0

1u0
25 26
26
GND PGND GND_HS
GND PGND GND_HS

8
9

15
5

8
9

15
+5V
GND-3V3
GND-5V IUWG

2UWY

2UY0
RES

RES
47u

22u
IUW7 ENABLE+3V3
DETECT12V

+12Vb +5V +3V3

+2V5 +2V5-F

3UWB DBG
9UW0 RES

330R
3UWA-1

3UWA-2

3UWA-3

3UWA-4
4K7

4K7

4K7

4K7

LTST-C190CKT
DBG
FUW2
PDZ5.1B(COL)

6UW1
6UW0

RES 2UWS

1n0
2UWR

1u0

22
23
24
25
26
7UW2-1 7UW2-2
RT9025-12GSP RT9025-12GSP
4

VDD VIA
FUW3
+3V3 3 6 +2V5
VIN VOUT
18 10
ENABLE+2V5 2 7 19 11
EN ADJ

2UWV
20 VIA VIA 12

22u
2UWT

1 21 13
10u

PGOOD
2UWU

100n

5
NC VIA
GND
GND HS

14
15
16
17
8

IUWF 3UWC
3UWE RES

220K 1%

1% 470K
3UWD 2UWW
3UWF
82K

22K 1n0

+3V3
3UWG-1

3UWG-2

3UWG-3

3UWG-4

3UWH-1

3UWH-2

3UWH-3

3UWH-4
470R

470R

470R

470R

470R

470R

470R

470R
RES

RES

RES

RES

RES

RES

RES

RES

5 2011-12-06

DC-DC
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 103

10-1-34 B06I, DC-DC

DC-DC
B06I B06I

7UV0
LD1117DT12

FUV1
+3V3 3 2 +1V2-FA
IN OUT
COM

22u 16V
2UV6

2UV7
100n

1
7UV1
IUV1 2UV9 RT9187GB

10u FUV2
+3V3 1 5 +1V1-FA
IN OUT

3UV6 RES
3 4
EN ADJ

2UVB

100R
10u
GND

2
3UV1

120K 1%
IUV3 3UV2

68K 1%
33K 1%

1M0 RES
2UVC IUV2 3UV3

3UV4

3UV5
1n0 22K RES
RES

5 2011-12-06

DC-DC
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 104

10-1-35 B06J, -

-
B06J B06J

intentionally blank

5 2011-12-06

-
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 105

10-1-36 B06K, Audio

Audio
B06K B06K

+3V3

3DY0

1R0
1J50
3150-831-030-H1 IDY1
2
VCC
FDY0
1 SPDIFO
VIN
3
GND

CDS4C12GTA
MT

V_NOM
5 4
2DY0

RES 2DY1

1DY1

RES 6DY0
100n

100p

12V

5 2011-12-06

Audio
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 106

10-1-37 B06L, Conditional access

Conditional access
B06L B06L

3PW2-1
MDI0 1 8 CA-MDI0
33R
3PW3
MDI1 CA-MDI1
33R
3PW4
MDI2 CA-MDI2
33R
3PW1-1
MDI3 1 8 CA-MDI3
33R
3PW2-4
MDI4 4 5 CA-MDI4
33R
3PW1-2
MDI5 2 7 CA-MDI5
33R
3PW2-3
MDI6 3 6 CA-MDI6
33R
3PW2-2
MDI7 2 7 CA-MDI7
33R
3PW5
MICLK CA-MICLK
33R
3PW1-4
MIVAL 4 5 CA-MIVAL
33R
3PW1-3
MISTRT 3 6 CA-MISTRT
33R

5 2011-12-06

Conditional access
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 107

10-1-38 B06M, FE

FE
B06M B06M

+3V3

3KW1 3KW2
TS-CHDEC-DATA TS-CHDEC-DATA
560R 470R
3KW3 3KW4
TS-CHDEC-CLK TS-CHDEC-CLK
560R 470R
3KW5 3KW6
TS-CHDEC-VALID TS-CHDEC-VALID
560R 470R
3KW7 3KW8
TS-CHDEC-SOP TS-CHDEC-SOP
560R 470R

2FS3

10p

2FS1 5FS1
SOC-IF-P IF-IN-P
100n 4u7
2FS2 5FS2
SOC-IF-N IF-IN-N
100n 4u7

2FS4

10p

RESET-DVBS cFS0 RESET-FUSION-OUTn

SCL-FE cFS1 SCL-TUNER

SDA-FE cFS2 SDA-TUNER

+3V3

3RW1 3RW2
TS-DVBS-DATA TS-DVBS-DATA
560R 470R
3RW3 3RW4
TS-DVBS-CLK TS-DVBS-CLK
560R 470R
3RW5 3RW6
TS-DVBS-VALID TS-DVBS-VALID
560R 470R
3RW7 3RW8
TS-DVBS-SOP TS-DVBS-SOP
560R 470R

5 2011-12-06

FE
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 108

10-1-39 B06N, Serial flash

Serial flash
B06N B06N

3CT0
SF-SDI
47R
+3V3-STANDBY
3CTR ICT1 RES
+3V3-STANDBY 2CT2
RES
4K7 RES 7CT1-1

14
SN74LVC125APW
3CTS 100n RES
2
3CTT
47R 3 SFB-SI
SFB-EN 1 47R
EN

7
3CTU
SF-CLK
3CTJ 47R
+3V3-STANDBY +3V3-STANDBY
RES
4K7 RES 7CT1-2

14
SN74LVC125APW
3CTV RES
5
3CTW FCT2 3CTH
+3V3-STANDBY 47R 6 SFB-SCK SF-SDO
SFB-EN 4 47R 47R
3CTY EN
+3V3-STANDBY

7
10K
3

7CT4

8
NCP803 7CT3
3CTZ
VCC SF-CS M25P05-AVMN6
VCC

3CTK 47R FCT3
2 FCT9 RESET-STANDBYn +3V3-STANDBY +3V3-STANDBY SFB-SI 5 2
RESET RES D Q
4K7 RES 7CT1-3 FCT4 512K

14
SN74LVC125APW SFB-SCK 6
3CTP RES C FLASH
2CT4

GND 9
1n0

3CT1 FCT5
47R 8 SFB-CS SFB-CS 1
S
SFB-EN 10
1

EN 47R FCT6
RES SFB-WPn 3
W

7
7CT5 FCT7
BC857BW DETECT12V SFB-HOLDn 7
HOLD
3CT2
1CT7 SF-WP VSS
SKHUBHE010 47R
3CT3 ICT2
1 3 +3V3-STANDBY +3V3-STANDBY

4
2 4 4K7 RES RES 7CT1-4
FCT8

14
SN74LVC125APW
3CT4 RES
DBG +3V3-STANDBY 12
3CT5
47R 11 SFB-WPn
SFB-EN 13 47R 1CTZ
EN
SFB-SCK 1

7
SFB-CS 2
RES 3CT7

+3V3-STANDBY SFB-SI 3
3CT6

3CT8
10K

10K

10K

SF-SDO 4
3CT9
SF-HOLDn SFB-EN 5
47R
3CTA 6
RES TEST-CON +3V3-STANDBY 8 7
3CTB ICT3 RES

3CTM

4K7
10K +3V3-STANDBY 2CT3
RES 7CT2 502382-0670
3CTC 4K7 RES
TEST-MOD 74LVC1G125GW

5
3CTD 100n RES
10K 2
3CTE
47R 4 SFB-HOLDn
3CTF
RES ENABLE-STANDBY SFB-EN FCT1 1 47R
EN
10K

3
3CTG

10K

5 2011-12-06

Serial flash
8204 000 9223

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120424

2012-Sep-14 back to
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 109

10-1-40 B06O, Fusion peripherals

Fusion peripherals
B06O B06O

IEE0
USB1-RREF 1 3EE2-1 8
12K
3EE2-2
2 7
12K
IEE1 3EE2-3
USB2-RREF 3 6
12K
4 3EE2-4 5
12K

5 2011-12-06

Fusion peripherals
8204 000 9223

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120424

2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 110

10-1-41 B06P, HDMI

HDMI
B06P B06P

RES
3HW6

390R
3HW1
HDMI-ARC HEAC
56R
1%

3HW2

680R
RES
FHW0 3HW3 RES IHW1
+5V PWR5V
10K

3HW4

2HW1
27K

10n
3HW5 IHW2
+3V3 RREF
12K 1%

2HW2

100n

5 2011-12-06

HDMI
8204 000 9223

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120424

2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 111

10-1-42 B06Q, Control

Control
B06Q B06Q
+3V3

7CW0
PCA9540BGD

3
VDD
4 3CWU
SD0 SDA-SSB SDA-SSB
3CW0
SDA-M3 SDA-M3 2 5 SCL-SSB SCL-SSB 3CWV 2K2
SDA SC0
2K2 2K2
+3V3 3CW1 3CWW +3V3
SCL-M3 SCL-M3 1 7 SDA-SRF SDA-SRF
SCL SD1
2K2 8 SCL-SRF SCL-SRF 3CWY 2K2
SC1
3CUF 2K2
DCW5 FCWR VSS

6
4K7 TEST-MOD
+3V3 3CUG
DCW6 FCWS
+3V3-STANDBY 4K7 TEST-CON 1CW7
1CW8 SCL-SRF FCWB
SCL-DEBUG 3CUH FCWK 1
SCL-S FCW4
1 3CWJ 2
10R FCWL SCL-M1 SCL-FE SDA-SRF FCWC
2 3

3CWR
3CUJ SDA-S

4K7
3 47R 5 4
3CR6
4 5 SDA-DEBUG 10R SCL-FE +3V3
1CW5 3CWF BM03B-SRSS-TBT
SDA-M1 SDA-FE 2K2
BM06B-SRSS-TBT BM03B-SRSS-TBT 47R 3CR7
1 SDA-FE +3V3
3CU4
2 FCWD EJTAG-MCU-TMS STB-GP0 EJTAG-MCU-TDI 2K2
FCWF EJTAG-MCU-TDO 47R 1CW6
3
4 FCWG EJTAG-MCU-TCK SCL-SSB FCW3 1
3CU5
5 FCWE EJTAG-MCU-TDI STB-GP1 EJTAG-MCU-TMS FCW2 2
6 FCWH 47R SDA-SSB FCW1 3
7 8 3CWD 5 4
3CWS

3CWT
1K0

1K0
STB-GP2 EJTAG-MCU-TCK
3CR8 BM03B-SRSS-TBT
47R ENABLE-WOLAN +3V3-STANDBY
3CU2 10K
STB-GP3
47R
ENABLE-WOLAN
SDM
3CWK FCW0 DCW4 3CWE
HP-DETECT IRQ-WOLANn SDMn +3V3-STANDBY
3CWB
DVS1 STB-GP4 47R 10K
22K

3CWH
3CWL RES

2CW1

RES
100n

10K
ENABLE-STANDBY LIGHT-SENSOR
3CWC
DVS2 STB-GP5 47R +3V3-STANDBY
22K 3CWG
+3V3-STANDBY STB-GP6 SPLASH-ON
2CW2

2CW3
100n

100n 47R
3CUA 3EW0
STB-GP7 RESET-ETHERNETn IRQ-WOLANn

3CRA
3CR9

10K

10K
100R 10K +3V3-STANDBY

3CUD
3CU0

10K
+3V3-STANDBY
3CWM 10K
STB-GP8 RESET-RF4CEn
47R 1CW9
+3V3 FCWM
ICW1 SPI-EN DCW1 TXD-STANDBY 1
3CWN FCWN
STB-GP9 LCD-PWR-ONn FCWP 2
+3V3
47R RXD-STANDBY 3
RES 3CUE

10K
3CWP 5 4
STB-GP10 SDMn
+3V3
BM03B-SRSS-TBT
47R
RES 3CUM
RES 3CUK

3CUL

1CW4
10K

10K

10K

3AW0
2CW6

100n

AMBI-TEMP-FUS AMBI-TEMP SCL-M3 FCWT 1

10R FCWU
2
SDA-M3 FCWV 3

RES 3AW1
2AW0
10K

10K

10K

22K
1u0
5 4 +3V3-STANDBY
+3V3-STANDBY
RES 3CUN

3CUR
3CUP

3CUS

BM03B-SRSS-TBT
10K

1CWD
7CW1 14 SCL-MC FCWW 1
3CWA
RES 3CUU

PCA9554BS
3CUV
3CUT

3CW8 RES

3CW9 RES
10K

10K

10K

10K
FCWY 2
VDD SDA-MC FCWZ 3

100K

100K
15 2

10K
SC1-DETECTn

3CW2
A0 IO0 3CUB 5 4
16 3 YPBPR-DETECTn PWRON STANDBYn
A1 IO1
1 4 CVBS-DETECTn 47R BM03B-SRSS-TBT
A2 IO2
5 VGA-DETECT
3CUW IO3 3CU1 3CW3
SCL-SSB 12 7 FCW5 3CR2 100R ARC-SEL0 AVLINK1 DETECT12V KYBRD KEYBOARD_IRQ-SRFn KEYBOARD_IRQ-SRFn
SCL IO4 3CR0
SDA-SSB 3CUY 47R 13 8 ARC-SEL1
SDA IO5 47R 10R
9 FCW6 100R 3CR1 ARC-SEL2
47R IO6 3CU3 3CW4
10 LED EJTAG-MCU-TDO LGSEN LIGHT-SENSOR LIGHT-SENSOR
IO7 FCW7 100R
DCW2 47R 10R
11 IRQ-EXPANDERn
INT 3CU6 3CW5
STB-TXD TXD-STANDBY IR RC_IRQ-RF4CEn RC_IRQ-RF4CEn
18 22 47R 100R
3CR3

19 23
10K

3CU7

2CW4

RES 3CW7

2CW5

RES 3CW6
100n

100n
20 VIA VIA 24

22K

22K
STB-RXD RXD-STANDBY
21 25 47R
3CU8
VSS GND_HS STB-SCL SCL-MC
17

47R
6

3CU9 3CR4 RES

STB-SDA SDA-MC SCL-MC +3V3-STANDBY
47R 2K2
3CUC 3CR5 RES
RESET-FUSION-OUTn STB-RSTO SDA-MC +3V3-STANDBY
47R 2K2

5 2011-12-06

Control
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120424

2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 112

10-1-43 B06R, Temperature sensor

Temperature sensor
B06R B06R

+3V3

2TW0

9TW0

9TW1

9TW2
100n

RES

RES
8
7TW0
LM75BGD

+VS
3 7
OS A0
3TW0 1 6
SDA-SSB SDA A1
3TW1 47R
SCL-SSB 2 5
SCL A2

GND
47R

9TW3

9TW4

9TW5
RES
5 2011-12-06

Temperature sensor
8204 000 9223

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120424

2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 113

10-1-44 B06S, Strap options

Strap options
B06S B06S

3CP5
NAND-CLE
10K

3CP8 RES FCP6 3CP6

+3V3-STANDBY F-OEn F-OEn
10K 10K

5 2011-12-06

Strap options
8204 000 9223

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2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 114

10-1-45 B07A, LPC debug

LPC debug
B07A B07A
FNA3
9NA1
+3V3-STANDBY +3V3-LPC
RES

7NA0
LD1117DT33
5NA1
+5V-LPC 3 2 9NA2
IN OUT +3V3-LPC-ANA
30R
COM
2NA0

2NA1

2NA3

2NA4

2NA5

2NA6

2NA7

2NA8

2NA9
100n

100n

100n

100n

100n
22u

10n

10n

10n
1
+3V3-LPC

3NAS

1K0
+3V3-LPC +3V3-LPC-ANA +3V3-LPC

2NAA

LTST-C190KGKT
7NA2

3NBB

1K0
18p LPC1768FBD100

28
54
71
96

42
84

10
1
4

1NA1
2 VDD_REG3V3 VDDA

6NA0
VDD

24M
22
XTAL1

LTST-C190KGKT
3
2NAB
23
XTAL2
18p
LPC-TDO 3NA0-1 1

6NA1
TDO|SWO 3NAT
+3V3-LPC LPC-TDI 100R 3NA1 2 95 7NA3-1
TDI P1_0|ENET_TXD0 BC847BS(COL)
LPC-TMS 3NA0-2 100R 3 94
TMS|SWDIO P1_1|ENET_TXD1 1K0
LPC-TRSTn 100R 3NA0-3 4 93
3NA2 TRST P1_4|ENET_TX_EN
LPC-TCK 3NA0-4 100R 5 92
TCK|SWDCLK P1_8|ENET_CRS
10K 100R 91
P1_9|ENET_RXD0 3NBC
3

7NA1 FNA1 100 90 7NA3-2

RTCK P1_10|ENET_RXD1 BC847BS(COL)
NCP803 89 1K0
P1_14|ENET_RX_ER
VCC FNA2 14 88
RSTOUT P1_15|ENET_REF_CLK
87
FNA4 P1_16|ENET_MDC
2 17 86
RESET RESET P1_17|ENET_MDIO
32
3NA3 P1_18|USB_UP_LED|PWM1_1|CAP1_0
16 33
RTCX1 P1_19|MCOA0|USB_PPWR_|CAP1_1
9NA3
RES

GND 10K 34 3NAU SFB-SCK

P1_20|MCI0|PWM1_2|SCK0
18 35 3NAV 47R SFB-CS
RTCX2 P1_21|MCABORT_|PWM1_3|SSEL0
36 47R
1

P1_22|MCOB0|USB_PWRD|MAT1_0
LPC-SDA1 9NA4 3NA4 46 37 3NAW SF-SDO
P0_0|RD1|TXD3|SDA1 P1_23|MCI1|PWM1_4|MISO0
LPC-SCL1 9NA5 3NA5 100R 47 38 3NAY 47R SFB-SI
P0_1|TD1|RXD3|SCL1 P1_24|MCI2|PWM1_5|MOSI0
LPC-TXD0 3NA6 100R 98 39 47R
P0_2|TXD0|AD0_7 P1_25|MCOA1|MAT1_1 3NBK
LPC-RXD0 3NA7 100R 99 40 SFB-EN
P0_3|RXD0|AD0_6 P1_26|MCOB1|PWM1_6|CAP0_0
1NA7 100R 81 43 47R
P0_4|I2SRX_CLK|RD2|CAP2_0 P1_27|CLKOUT|USB_OVRCR_|CAP0_1
3NAZ LPC-EJT-RSTN 80 44
1 P0_5|I2SRX_WS|TD2|CAP2_1 P1_28|MCOA2|PCAP1_0|MAT0_0
3NA8 47R LPC-EJT-TMS 79 45
2 P0_6|I2SRX_SDA|SSEL1|MAT2_0 P1_29|MCOB2|PCAP1_1|MAT0_1
3NA9 47R LPC-EJT-TDO 78 21
3 P0_7|I2STX_CLK|SCK1|MAT2_1 P1_30|VBUS|AD0_4
3NAA 47R LPC-EJT-TCK 77 20 6 3NAP-3 3 7 3NAP-2 2 8 3NAP-1 1
4 P0_8|I2STX_WS|MISO1|MAT2_2 P1_31|SCK1|AD0_5 +VDISP
3NAB 47R LPC-EJT-TDI 76
5 P0_9|I2STX_SDA|MOSI1|MAT2_3 10K 10K 10K

5
47R 3NAC 48 75 3NB0 SFB-WPn

3NAP-4
6 P0_10|TXD2|SDA2|MAT3_0 P2_0|PWM1_1|TXD1

3NAR

2NAF

100n
3NAD 100R 49 74 3NB1 47R

10K

10K
7 8 LPC-SDA2 P0_11|RXD2|SCL2|MAT3_1 P2_1|PWM1_2|RXD1 SFB-HOLDn
LPC-SCL2 3NAE 100R 62 73 3NB2 47R POWER-OK
P0_15|TXD1|SCK0|SCK P2_2|PWM1_3|CTS1|TRACEDATA_3
BM06B-SRSS-TBT RXD-STANDBY 3NAF 100R 63 70 3NB3 47R STANDBYn

4
P0_16|RXD1|SSEL0|SSEL P2_3|PWM1_4|DCD1|TRACEDATA_2 RES
TXD-STANDBY 100R 61 69 3NB4 47R DETECT12V
P0_17|CTS1|MISO0|MISO P2_4|PWM1_5|DSR1|TRACEDATA_1
60 68 3NB5 47R +3V3-LPC
3NBG 3NBF 3NBH P0_18|DCD1|MOSI0|MOSI P2_5|PWM1_6|DTR1|TRACEDATA_0
59 67 10K
P0_19|DSR1|SDA1 P2_6|PCAP1_0|RI1|TRACECLK
47K 10K 47K 58 66
P0_20|DTR1|SCL1 P2_7|RD2|RTS1
LPC-USB-CONNECT 57 65 3NB6 LPC-TXD2
P0_21|RI1|RD1 P2_8|TD2|TXD2
56 64 3NB7 100R LPC-RXD2
P0_22|RTS1|TD1 P2_9|USB_CONNECT|RXD2
3NAG 9 53 FNAV 3NB8 100R +3V3-LPC
+3V3 P0_23|AD0_0|I2SRX_CLK|CAP3_0 P2_10|EINT0_|NMI
10K 8 52 10K
P0_24|AD0_1|I2SRX_WS|CAP3_1 P2_11|EINT1_|I2STX_CLK 3NBE
7 51 9NA7 RESET-STANDBYn LPC-USB-CONNECT BC857BS(COL)
P0_25|AD0_2|I2SRX_SDA|TXD3 P2_12|EINT2_|I2STX_WS 7NA5-1
6 50 9NA8 RESET-FUSION-OUTn 10K
P0_26|AD0_3|AOUT|RXD3 P2_13|EINT3_|I2STX_SDA
SDA-SSB 9NA9 3NAH 25
P0_27|SDA0|USB_SDA
SCL-SSB 9NAA 3NAJ 100R 24 27
P0_28|SCL0|USB_SCL P3_25|MAT0_0|PWM1_2 FNAP
LPC-USB-DP 3NAK 100R 29 26
P0_29|USB_D+ P3_26|STCLK|MAT0_1|PWM1_3 FNAR

3NBD
3NAL 33R 30

1K5
LPC-USB-DM P0_30|USB_D-
33R 82 3NBA RXD-SERVICE 1NA2
P4_28|RX_MCLK|MAT2_0|TXD3
12 85 3NB9 100R TXD-SERVICE FNA8
VREFP P4_29|TX_MCLK|MAT2_1|RXD3 +5V-LPC 1
1 3NAM-1 8 7 3NAM-2 2 3 3NAM-3 6
2NAD

2NAE

15 100R FNAD
RES 18p

RES 18p

+12Vb VREFN LPC-USB-DM 2

10K 10K 10K LPC-USB-DP FNAE
3
19 FNA9
VBAT 4
2NAC

3NAN
4 3NAM-4 5
100n

10K

5
13
10K

NC 7 6
RES VSS VSSA
+3V3-LPC-ANA

31
41
55
72
97
83

11
502382-0570
+3V3-LPC

3NBJ

100R
PROGRAM LPC
1NA4
INA0
LPC-TXD0 FNA5 1NA3
1 INA1 3NBL
FNA6 FNAF LPC-TRSTn LPC-TRSTn
2 1 +3V3-LPC
LPC-RXD0 FNA7 FNAS LPC-TMS 10K
3 2
5 4 FNAT LPC-TDO
3
FNAU LPC-TCK
4
BM03B-SRSS-TBT FNAK LPC-TDI
5

3NBM
FNAL

10K
6 RES
7 8

DEBUG MIPS 1NA5 1NA6 BM06B-SRSS-TBT

1NA8 LPC-SCL2 FNAA LPC-SCL1 FNAG
1 1
LPC-RXD2 FNAB FNAH
1 2 2
LPC-SDA2 FNAC LPC-SDA1 FNAJ
2 3 3
LPC-TXD2 3 5 4 5 4
5 4
BM03B-SRSS-TBT BM03B-SRSS-TBT
BM03B-SRSS-TBT

5 2011-12-16

LPC debug
8204 000 9222

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2012-Sep-14 back to
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 115

10-1-46 B07B, Headphone

Headphone
B07B B07B

+3V3-STANDBY

4
PUMD12
5 7DH0-2
RESET-HDPHN
3

6
FDH6
RESET-FUSION-OUTn 2 7DH0-1
PUMD12
1
3DH7

10R

2DHA

47p
1 3DH1-1 8

6
3DH1-2
22K

3DH1-3
22K

22K
3DH1-4
4 5

3
22K
2DHB

47p +3V3
7 1DH5
3

2DH2 2

100n
7DH1
TPA6111A2DGN
3 3DH3-3 6 1
8

IDH2 IDH3 IDH1

VDD
2DH6
33R
FDH4
5102-Z4R-J47-59

HPHOL
2DH3
8 3DH2-1 1 2 AMPLIFIER 1 9DH0
IDH8
4 3DH3-4 5
1 1 FDH1
IDH4 1u0 2DH4 10K IN- 4V 100u 33R
HPHOR 5 3DH2-4 4 6 2
2 VO 1DH4
2DH7 FDH5 3
1u0 10K IDH5 IDH9
5 7 9DH1 2 3DH3-2 7 1

CDS4C12GTA

CDS4C12GTA
SHUTDOWN 2 FDH2

8
MSJ-035-12D-B-AG-PBT-BRF
IDH6

3DH4-4
2DH5 33R

3DH4-1
4V 100u

1DH2

6DH1

1DH3

6DH2

2DH8

2DH9
3 10

1K0

1K0

12V

12V

22n

22n
BYPASS 3DH3-1
VIA 11 1 8 FDH3
1u0
GND GND_HS

RES

RES
4

1
33R
4

RESET-HDPHN 3 3DH2-3 6 IDH7

10K
RES 3DH6

9DH2
22K

HPHOL

HPHOR 9DH3

5 2011-12-16

Headphone
8204 000 9222

19210_051_120424.eps
120424

2012-Sep-14 back to
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 116

10-1-47 B07C, Internal USB

Internal USB
B07C B07C
9EHE-1 RES
9EHE-2 RES
9EHE-3 RES
9EHE-4 RES

3EHL DBG * WIRED NETWORK STANDBY ONLY

LTST-C190KGKT
DBG
330R

6EH1
7EH2
RT9715EGB *
+3V3-WIFI 5 3
VIN FLG

FEHA
ENABLE-WOLAN 4 1
EN VOUT +3V3-LAN
EN

100u 6.3V
2EHM

RES 2EHY
2EHL
GND

10u

10u
2
9EH6 9EH5 9EHC
* *
external regulator OFF ON ON
internal regulator ON OFF ON

+5V +3V3 +3V3-USBN 7EH4

TPS61200DRCG4

5 2
VIN VOUT

9EHC
RES 9EH6

9EH5
2EHV
8 1 IEH0
PS VAUX

2EHR

2EHS

2EHT
22u

22u

22u
100n IEH1
6 10
EN FB
7
UVLO

3EHR
3EHS
2EHU RES

330K
12

22K
GND_HS
5EH0 IEH2

VIA
2EHA

100n
3 13

PGND
L

GND
1n0
4u7

2EHC

2EHD
2EHB

2EHE
100n

100n

100n

100n

11
2EHF

18p 2EH9 3EHU

7EH1

27

14

21
1EH1
3225

CY7C65634-28LTXCT
12M

5
9
NC

47n 22K +3V3-WIFI

VCC

VCC_A_1
VCC_A_2
VCC_A_3

VCC_D
10 7EHJ
2EHG XIN BC847BW
11
18p XOUT
1 USB-SET-DM
D-

3EHT
3 2

22K
USB-CAM-DM DD1- D+ USB-SET-DP

3EHP

120K
USB-CAM-DP 4
DD1+ +3V3
3EHA 25
+3V3 OVR1
10K 2EHJ
6 26 3EHK RES 3EHV
USB-WIFI-DM DD2- SDA +3V3 IEHJ

2EHW
RES 9EH3
7 10K

10n
USB-WIFI-DP DD2+ 100n 22K

cEH0
3EHB 24
+3V3 OVR2

3EHJ

100K
10K
12
NC4
13 18
NC5 TEST|SCL 2EHN RES
3EHC 20
+3V3 NC6 +3V3-LAN
10K

9EH4
RES 9EH8-1 100n
15
NC1 RES 9EH8-2
16
NC2 RES 9EH8-3
3EHD 19 1C31

RES
+3V3 NC3 RES 9EH8-4
10K 30 FEH1
VIA1 +3V3 1
28 31 USB-WIFI-DM FEH2
RESET-FUSION-OUTn RESET-FUSION-OUTn VREG VIA2 2
3EHH 17 32 USB-WIFI-DP FEH3
+3V3 RESET VIA3 3
10K 3EHE 22 33 FEH4
RES +3V3 SELFPWR VIA4 4
10K 23 IRQ-WOLANn 9EHD FEH5
GND_HS

3EHF GANG 5
2EHH

8
1n0

RREF 6
680R
100K

RES 7 8
29

RES 7EH3 502386-0670

+3V3-USBN 3EHM
BC857BW
47R RES 3EHN
2EHK

3EHG
100n

USB-SET-DM 9EHA USB-WIFI-DM RES +3V3-LAN

10K
RES 2EHP
USB-SET-DP 9EHB USB-WIFI-DP
100n

1C30
FEH6
+5V 1
USB-CAM-DM FEH7
2
USB-CAM-DP FEH8
3
FEH9
4
5
6 7

502386-0570

5 2011-12-16

Internal USB
8204 000 9222

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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 117

10-1-48 B07D, Common interface

Common interface
B07D B07D
3PA1
+5V +5VCA
22u 16V +T 0R4 +3V3
2PA1

2PA2

100n

7PA1

20
74LVC245ABQ
1 VCC
3EN2
3EN1
19
G3
+3V3 +3V3
CA-MOVAL 3PA3
1
2 18 MOVAL MOVAL 3PA6 10K
100R 2
CA-MOSTRT 3PA8-1 8 3 17 MOSTRT MOSTRT 3PAA-1 10K
CA-MDO0 3PA8-2 100R 1 4 16 MDO0 MDO0 1 8 3PAA-2 10K
100R 2 7 6 5 15 2 7 10K 1P00
CA-MDO1 3PA8-3 MDO1 MDO1 3PAA-3
CA-MDO2 100R 3 3PA8-4 5 6 14 MDO2 MDO2 3 6 3PAA-4 10K 1
100R 4 7 13 4 5 CA-D03 2
8 12 CA-D04 3
9 11 CA-D05 4
GND GND_HS CA-D06 5
CA-D07

10

21
6
CA-CE1n 7
CA-A10 8
CA-OEn 9
CA-A11 10
+3V3 CA-A09 11
CA-A08 12
CA-A13 13
2PA3 CA-A14 14
CA-WEn 15
7PA2 100n

20
74LVC245ABQ CA-RDY 16
1 VCC +5VCA 17
3EN2
3EN1 18
19 CA-MIVAL 19
G3 CA-MICLK
+3V3 20
3PA2 CA-A12
CA-MOCLK 1 21
2 18 3PA5 10K CA-A07
100R 2 MOCLK MOCLK 22
CA-MDO7 3PA4 100R 3 17 MDO7 MDO7 3PA7 CA-A06 23
CA-MDO6 3PA9-4 5 4 4 16 MDO6 MDO6 10K 3PAB-1 10K CA-A05 24
CA-MDO5 3PA9-3 100R 5 15 MDO5 MDO5 3PAB-2 10K 1 8 CA-A04 25
CA-MDO4 3PA9-2 100R 6 3 6 14 MDO4 MDO4 3PAB-3 10K 2 7 CA-A03 26
CA-MDO3 3PA9-1 7 2 100R 7 13 MDO3 MDO3 3 6 3PAB-4 10K CA-A02 27
100R 8 1 8 12 4 5 CA-A01 28
9 11 CA-A00 29
GND GND_HS CA-D00 30
+3V3 CA-D01
10

21
31
CA-D02 32
CA-WP 33

DBG

DBG
34
35

10K

10K
CA-CD1n 36
MDO3 37

3PC0

3PC1
MDO4 38
MDO5 39
+3V3 CA-MDI6 MDO6 40
CA-MDI7 MDO7 41
CE2n 42
CA-VS1n 43
3PAC CA-IORDn
CA-CD1n 44
CA-IOWRn 45
10K 3PAD CA-MISTRT
CA-CD2n 46
CA-MDI0 47
3PAE 10K CA-MDI1
CA-VS1n 48
CA-MDI2 49
10K 3PAF CA-MDI3
CA-WAITn 50
10K +5VCA 51
DBG 52
CA-MDI4 53
+3V3 1C32 CA-MDI5 54
1 CA-MDI6 CA-MDI6 55
2 CA-MDI7 56
3PAM MOCLK
CA-RST 3 57
4 5 CA-RST 58
100K 3PAN CA-MDI7 CA-WAITn
CA-RDY 59
BM03B-SRSS-TBT CA-INPACKn
10K 60
3PAP REGn
CE2n 61
3PAL MOVAL
REGn 10K 62
3PAR RES MOSTRT
33R CA-CE1n 63
MDO0 64
RES 3PAS 10K MDO1
CA-IORDn 65
MDO2 66
10K 3PAT RES CA-CD2n
CA-IOWRn 67
RES 10K 68
9PAA RES 3PAU 71 69
CE2n CA-CE2n CA-OEn
72 70
10K 3PAV RES
RES CA-WEn
9PAB 92789-055LF
REGn CA-REGn 10K

3PAW RES
CA-WP
10K 3PAY RES
CA-INPACKn
10K

5 2011-12-16

Common interface
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 118

10-1-49 B07E, FPGA - power & control

FPGA - power & control

B07E B07E

5GG1 FGG1 6GG1 DBG 3GG1

+3V3 VAUX 3 DBG +3V3
30R 470R
LTST-C190KGKT
DONE 1 7GG1

RES 2GG1

2GG2

2GG3

2GG4

2GG5

2GG6

RES 2GG7

220n
PDTC144EU

2u2

2u2

2u2

2u2

2u2
2u2
2 DBG

7GG6
LD1117DT12
FGG2 MISO
3 2 VCCINT
+3V3 IN OUT
+3V3
2GG8

100n

COM
FGG7

2GGG
2GGC

2GGD
2GGA

2GGB

2GGE

2GGF
2GG9

220n

220n
10u

22u

22u

2u2

2u2

2u2
1

4K7 RES
3GG2

2GH7

100n
3GG3
7GG2

10R
* M25P40-VMN6

8
5GG2 FGG3 1GG1 VCC
VCCO3

+3V3 FGG8 IGG2
30R CCLK MOSI 5
1 D Q
CSO-B 2
2 FGG9
2GGM
2GGH

2GGK

2GGL
2GGJ

220n

220n

220n

6
2u2

2u2

3 MOSI CCLK C
4 MISO FGGA
PROG-B CSO-B 1
RES

5 S
7
6 HOLD
7 8 3
W
502382-0670 GND

4
5GG3 FGG4
+3V3
30R
VCCO2
PROGRAMMING FGGB 6SLX4-4MB-M25P40
6SLX9-4MB-M25P40
RES 2GGN

2GGR
2GGP

2GGS
220n

220n

ENGINEERING
2u2
2u2

+3V3

5GG4 FGG5
+3V3 7GG3
VCCO1 3225 RES
FPGA-LED0

4
30R
IGG1 3GG5 RES
2GGW
2GGU

RES 2GGV

2GGY

2GH1
220n

220n

220n

1 3
2u2

FPGA-SYS-CLK FPGA-LED1
2u2

47R

100n RES
VALUE
FPGA-LED2

2GH8

2
FPGA-LED3

DBG 3GG4-1

DBG 3GG4-2

DBG 3GG4-3

DBG 3GG4-4
8 330R 1

7 330R 2

6 330R 3

5 330R 4
5GG5 FGG6
+3V3 VCCO0
30R
2GH2

2GH3

2GH4

2GH5

2GH6
220n

220n

220n
2u2
2u2

+3V3 +3V3

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT
DBG

DBG

DBG

DBG
RES

7GG4 7GG5
74LVC1GU04GW 74LVC1GU04GW RES

5
2 4 2 4 3GG6
1 1 RES

6GG2

6GG3

6GG4

6GG5
NC NC
47R
1

3
3GG7 3GG8
FPGA-SYS-CLK
1M0 47R
3GG9

1K0

1GGA
3225 AMBI-SPI-CCLK 2 9GG1-2 7 AMBI-SPI-OUT-CCLK
2 NC 4
1 3 AMBI-SPI-MOSI 4 9GG1-4 5 AMBI-SPI-OUT-MOSI

12M AMBI-SPI-MISO 3 9GG1-3 6 AMBI-SPI-OUT-MISO

2GHA
2GH9

1 9GG1-1 8
10p

10p

AMBI-SPI-CSn AMBI-SPI-OUT-CSn

3D-LR 9GG2 RES 3D-LED_3D-RF

9GG3 RES 3D-LR-DISP

BL-SPI-CS_BL-I-CTRL 9GG4 BL-I-CTRL

5 2011-12-16

FPGA - power & control

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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 119

10-1-50 B07F, FPGA - I/O banks

FPGA - I/O banks

B07F 7GF1-1
XC6SLX4-2TQG144C0100 B07F
BANK0
9GF1 RES 144 127
IO_L1P_HSWAPEN_0 IO_L36P_GCLK15_0
143 126
IO_L1N_VREF_0 IO_L36N_GCLK14_0
142 124
IO_L2P_0 IO_L37P_GCLK13_0
141 123
IO_L2N_0 IO_L37N_GCLK12_0
140 121
IO_L3P_0 IO_L62P_0
139 120
IO_L3N_0 IO_L62N_VREF_0
138 119
IO_L4P_0 IO_L63P_SCP7_0
7GF1-6 137 118
IO_L4N_0 IO_L63N_SCP6_0
XC6SLX4-2TQG144C0100 134 117
IO_L34P_GCLK19_0 IO_L64P_SCP5_0
133 116
IO_L34N_GCLK18_0 IO_L64N_SCP4_0
132 115
20 IO_L35P_GCLK17_0 IO_L65P_SCP3_0
131 114
36 IO_L35N_GCLK16_0 IO_L65N_SCP2_0

VCCAUX
112
VAUX 53 IO_L66P_SCP1_0
111
90 IO_L66N_SCP0_0
129

19 3
28 13
VCCINT
7GF1-2
VCCINT 52 25 XC6SLX4-2TQG144C0100
89 49
BANK1
PWR_GND
128 54
68 105 88
GND
122 77 IO_L1P_1 IO_L42P_GCLK7_1
VCCO_0

104 87
125 91 IO_L1N_VREF_1 IO_L42N_GCLK6_TRDY1_1
VCCO0 102 85
135 96 IO_L32P_1 IO_L43P_GCLK5_1
101 84
108 IO_L32N_1 IO_L43N_GCLK4_1
100 83
76 113 IO_L33P_1 IO_L45P_1
VCCO_3 VCCO_2 VCCO_1

99 82
VCCO1 86 130 IO_L33N_1 IO_L45N_1
98 81
103 136 IO_L34P_1 IO_L46P_1
97 80
IO_L34N_1 IO_L46N_1
95 79
VCCO2 42 IO_L40P_GCLK11_1 IO_L47P_1
94 78
63 IO_L40N_GCLK10_1 IO_L47N_1
93 75
IO_L41P_GCLK9_IRDY1_1 IO_L74P_AWAKE_1
92 74
4 IO_L41N_GCLK8_1 IO_L74N_DOUT_BUSY_1
VCCO3 18
31

7GF1-3
XC6SLX4-2TQG144C0100

BANK2
72 56 FPGA-LED1
3GF7 FGF1 CMPCS_B_2 IO_L30P_GCLK1_D13_2
VCCO2 DONE DONE 71 55 FPGA-LED0
DONE_2 IO_L30N_GCLK0_USERCCLK_2
CCLK 3GF1 70 51
1K0 IO_L1P_CCLK_2 IO_L31P_GCLK31_D14_2
10R IGF2 69 50 FPGA-SYS-CLK
IO_L1N_M0_CMPMISO_2 IO_L31N_GCLK30_D15_2
AMBI-SPI-CCLK 67 48
IO_L2P_CMPCLK_2 IO_L48P_D7_2
AMBI-SPI-MOSI 66 47
IO_L2N_CMPMOSI_2 IO_L48N_RDWR_B_VREF_2
MISO 65 46 3D-LR-DISP
IO_L3P_D0_DIN_MISO_MISO1_2 IO_L49P_D3_2
MOSI 3GF2 10R 64 45 3D-LED_3D-RF
IO_L3N_MOSI_CSI_B_MISO0_2 IO_L49N_D4_2
AMBI-SPI-MISO 62 44
IO_L12P_D1_MISO2_2 IO_L62P_D5_2
AMBI-SPI-CSn 61 43 3D-LR
IO_L12N_D2_MISO3_2 IO_L62N_D6_2
9GF2 60 41 3GF8 10R SCL-SSB
IO_L13P_M1_2 IO_L64P_D8_2
59 40 3GF9 10R SDA-SSB
IO_L13N_D10_2 IO_L64N_D9_2 IGF1 2GF1
FPGA-LED3 58 39 100n
IO_L14P_D11_2 IO_L65P_INIT_B_2 RES
FPGA-LED2 57 38 3GF3 10R CSO-B
IO_L14N_D12_2 IO_L65N_CSO_B_2
37 PROG-B
PROGRAM_B_2
FGF9

7GF1-4
XC6SLX4-2TQG144C0100

BANK3
FGF2
35 17 BL-DIM1
IO_L1P_3 IO_L43P_GCLK23_3
34 16 BL-DIM2
IO_L1N_VREF_3 IO_L43N_GCLK22_IRDY2_3
CTRL-DISP2 3GFA RES 33 15 BL-DIM3
IO_L2P_3 IO_L44P_GCLK21_3
10R 32 14 BL-DIM4
IO_L2N_3 IO_L44N_GCLK20_3
AMBI-SPI-OUT-CSn 30 12 BL-DIM5
IO_L36P_3 IO_L49P_3
AMBI-SPI-OUT-MISO 29 11 BL-DIM6
IO_L36N_3 IO_L49N_3
AMBI-SPI-OUT-MOSI 27 10 BL-DIM7
IO_L37P_3 IO_L50P_3
AMBI-SPI-OUT-CCLK 26 9 BL-DIM8
IO_L37N_3 IO_L50N_3
24 8 BL-I-CTRL
IO_L41P_GCLK27_3 IO_L51P_3
23 7 BL-DIM
IO_L41N_GCLK26_3 IO_L51N_3
22 6 3GFB RES BL-SPI-CS_BL-I-CTRL
FGF3 IO_L42P_GCLK25_TRDY2_3 IO_L52P_3
21 5 10R
IO_L42N_GCLK24_3 IO_L52N_3
2
IO_L83P_3
1
IO_L83N_VREF_3

VAUX
10K

10K
3GF4

3GF5

7GF1-5
XC6SLX4-2TQG144C0100

MISC
DBG DBG 109
TCK
1GF1 1GF2 110
TDI
1 FGF8 1 107
TMS
2 FGF4 2 106
TDO
3 FGF5 3
4 FGF6 4 73
SUSPEND
5 FGF7 5
6 6
VAUX
7 8
100n DBG

SD51022
2GF2

5 2011-12-16

FPGA - I/O banks

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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 120

10-1-51 B07G, CPLD

CPLD
B07G B07G

5GC1 FGC1
+3V3 VINT
30R

2GC1

2GC2

2GC3
100n

100n
1u0

5GC2 FGC2
+3V3 VIO
30R
2GC4

2GC5

100n
1u0

VINT VIO

7GC1

15
35

26
XC9572XL-10VQG44C0100
VCCINT VCCIO
FPGA-SYS-CLK 9GC1 43
IXO1_43|GCK1
44
IXO1_44|GCK2
1
IXO1_1|GCK3
2 5
IXO1_2 IXO3_5
AMBI-SPI-CSn 3 6 9GC2 BL-DIM
IXO1_3 IXO3_6
AMBI-SPI-MOSI 39 7 3D-LR
IXO1_39 IXO3_7
AMBI-SPI-MISO 3GC1 33R 40 8
IXO1_40 IXO3_8
AMBI-SPI-CCLK 41 12 3GC2 3D-LED_3D-RF
IXO1_41 IXO3_12
42 13 33R CPLD-LED0 CPLD-LED0
IXO1_42 IXO3_13
14 CPLD-LED1 CPLD-LED1
IXO3_14
36 IXO3_16 16 CPLD-LED2 CPLD-LED2
IXO2_36|GTS1
34 18 CPLD-LED3 CPLD-LED3
IXO2_34|GTS2 IXO3_18
33
IXO2_33|GSR
19
IXO4_19

8 330R 1

7 330R 2

6 330R 3

5 330R 4
3GC3 29 20

3GC9-1

3GC9-2

3GC9-3

3GC9-4
IXO2_29 IXO4_20
30 21

DBG

DBG

DBG

DBG
AMBI-SPI-OUT-CSn IXO2_30 IXO4_21
33R 31 22 3GC4 33R AMBI-SPI-OUT-CCLK
IXO2_31 IXO4_22
AMBI-TEMP 32 23 AMBI-SPI-OUT-MISO
IXO2_32 IXO4_23
37 27 3GC6 33R AMBI-SPI-OUT-MOSI
IXO2_37 IXO4_27
38 28
IXO2_38 IXO4_28

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT
3GC7 RES

11
TCK

RES 2GCA
9
TDI

2GCB
2GC6

2GC7

2GC9
24
10K

1n0

10p

10p

10p

10p

6GC1

6GC2

6GC3

6GC4
DBG

DBG
TDO

DBG

DBG
10
TMS
GND
+3V3
4
17
25

DBG
1GC1
1 FGC3
2 FGC4
3 FGC5
4 FGC6
5 FGC7
6
+3V3
7 8
2GC8
DBG

100n

5 2011-12-16

CPLD
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 121

10-1-52 B07H, AmbiLight

AmbiLight
B07H B07H

+3V3AL

2AA3

1u0
1A04

2AA1

2AA2
470p

470p
FAA1
1
FAA2 9AA1
2 3AA1
FAA3 IAA1 AMBI-SPI-OUT-MOSI
3
4 3AA2 47R
FAA4 IAA2 AMBI-SPI-OUT-CCLK
5
FAA5 5AA2 30R 47R
6 3AA3
FAA6 IAA3 AMBI-TEMP
7
8 100R

2AA5

2AA6
100n

1u0
9 2AA7
10
11 100n

RES
12 GND-AL RES
IAA4 9AA2
13
14
15
16 AMBI-POWER
17
18

RES 2AA8

2AA9
19

100n
FAA7

10u
20

GND-AL
GND-AL

+3V3AL

2AAA

1u0
1A05

1
IAA5 9AA3 5AA3 30R
2
RES
3
4
5
IAA6
6
7
8
9
10
11 GND-AL
12
IAA7 9AA5
13
RES
14
15
16
17
18
2AAC
RES 2AAB
19

100n
10u

20

GND-AL

GND-AL

5 2011-12-16

AmbiLight
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 122

10-1-53 B07I, Interconnect

Interconnect
B07I B07I

3CL0 3CL1 RES

+3V3-STANDBY CA-IOWRn CA-IOWRn
10K 10K

3CL2 3CL3 RES

+3V3-STANDBY CA-WEn CA-WEn
10K 10K

3CL4
CA-OEn
10K

3CL5 3CL6 RES

+3V3-STANDBY CA-IORDn CA-IORDn
10K 10K

3CL7 RES 3CL8

+3V3-STANDBY CA-A14 CA-A14
10K 10K

5 2011-12-16

Interconnect
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 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 123

10-1-54 Layout top

1C21
5D85

3CYV
1G55

1D56
1D55
1D54
1D53

1D51
1D50
1D52
1C20 1G53

2D87 2D98 2D70

2D48 2D5C 5D00 1D35 3CYR

1T71
3CYS

2TA3 5TA1
3CYU

1D01 1D02

1TA1
BGVL BGVM
9GD1 3TA2

2UPK
2D76 2D99
BGV5 BGV9 BGVD BGVH 2GD72GD62GD42GD3 2GD22GD1 2TA2

BGV2
3D82 2D78 2UPH 2GV2 2GS2 2GD5

3CYF
6UP6

3GWG

3GS7
3GS6
ICY7

BGVE

3GD6
3GV9

2GVL
2D91

3GD2
3GD1
2D73

2GVM
2GVR

2GVN
2GVP

3GVA

3GVB

3GVE
2GVK
3GVF
5D74
3D83 9GS1 9GS2 2GD9 2GD8

5D78
5D70
BGV6 BGVA BGVK 3GD3

9GV3

7GD1
2UCY

2TA1
2D81 3UP3 6UP1 5TA2

3GVD
2D56
2UPF

6UP5

1GS1
3GV7

9GV1
2UPC
7GS5

3GVJ
2GWL

7UP22UPJ 3TA1

3GS5

3GS3
5D72

2D71

3GD7
5D81 9GW0
BGV7 BGVB 3GWE 6GD1

2D5D 7GS1

7UC2
5D76
3GW8 BGV3

3GS2
5D83
5D01
5UP5 6GS1

5D75
5D71

5D77

3GS4
2GS3

7GS2
3GW7 BGV8 BGVC BGVF 7GS3

3CVL
3CVK
5UC0

2VA1 2VA3 2VA2 2VA7 2VA4 2VA6

3VA1
5D80 BGVJ BGV4 2GS1

3UPD
3UPB

3UPE
2GS4 7GS4

2D55

2UCC
2UCA
2UCB
2UPE

1VA5
3GS1 2GS5
1VAE 3VAJ 2D89 2D83 BGVG 2UA5
2D80 2D82 2UPD

3GM3
3GM4
IUPE 3UA4
3D74 3D75 BGVN
1VAF 2D66
2D92 3UA3

2UCK
2UCJ
2UC1
1CWB

2UCF
2D94
2UPG

2D95
3VA4
2D62 2D64 3UC3 2UA6
1VAC

2D5B 2D60
2D75

5D79 2UPM BGV1 3UAA

3D72
2D88

3D73
7GM1

3VA5
1VAD 3UA2

2D61

2D65
5UB5

3GM2
3GM1
2UA7

5UC2
3VA3
2UBL

2UCW
1VAB
7UC3 1CV1
3UA1

2VA5
3VA0
2D97 2D79 2D85
2UBM 1CWA 2UA8

2UAT
3D62 3UB8 3UB6
2D59
2VA0
3VA2
2UBK

1M95
2D93

2D67
9D50
1VAA 3D79 3UB92UBW

7D60
2D54

2D77
3D78
2D96 7D71 2UC0

2UBV
3D70
2D58
9D51

7UB5 5UB7 6UC2 2UCL

2UBY
3D63
2D84 2D53 2D69
7D70
3D52 2D52 3D57
2D57 2UBS

2D5A

3D51

2D50
5D50
3D50 3D60 3D61 2UCT
2D51 2UA4

7D50
2D63 9UC1
1UP1
5D51 3UD2 2UBT 2UBN

2D86
2UA3

2D72
1UA0

2D68
3D58

3D76
3D77
9D55
9D54
3D71
2D74

9D52
9D53
3D55
3D56
3D54
2UBP 2UA2

2D49

7UA3
3UA8
9UA0
3UAC

2UAD
3UAB
2VAK 3VAK
1VAP

3UA9
6VAF

3UA0

3UA7
3UAK
1VAN 3VAD
7UA2 2UA1
1VA1

3UCJ 3UC5
3UC4
3UCS
3UCV
1VAM 2VAG
2UCS 2J95 3J24 2UA0

2J25
3J25
1VAL 2VAF 2UCG 5J0R

2J27
3J1R

2J08
6VAB

1VAK 3VAA

2JW1
2JW2
3J1Y

7UC7
2J92

3UAJ

3UAG
3UAD
3UD0
1VAJ 2VAC 3UAF 3UAH

7UA0

7UA1
1VAH 2VAA
3J1W

1VAG 3J1Z
2UA9

2UAJ
2VA8 DB34

DB31
DB52 DB93
DB50 DB32

3UAE
2J7S
DB49

2J1P 2J20 2J1V

2UP9
6UAA 9UA1

7J02

7J01
2UP7
7UC4

2UP4
7UP1

2UAV
2UF9

2J1N 2J82 2J1H 2J1B 2J1R 2J7T

2UAU

7UF6
3UP4

1FA1

1FA2
2FA5
3FA0
2UPA 3UP5
3J10
3UP2 2UPB DB90
2FA6 2UP2 3J13

5UP2
3UP1 3UP6

2J1E 2J1M 2J14

DBA2

2UP8
2UP1
1M99
2KCC

2URJ
3UP7

2URH

3URC
3URB
2URF

3URF
DB53
3J1G

3KC4
DB48

2KCB
1KC0
5UP1
2UP0 3J1H 7UF5
7CVW
DBA5

3UR5
3UR4
3UR7
3UR6
2UR2
2URG
3URA

2UR3
3J1B 3UGE
5FA5 5FA4 5KC9 5KC8

3J1A 3J20 3J2R 3UGC

7UR6
2FAG 2FAH

3J36 3J3S
3J37 3J3T
3KA0 5KC1 2KCG

1M11
9FA1

3J21 3J2Q DB40 3UGB

7KC0
2CVW 7UF7

7URA
3CVW
3CVY
9KC1 2KCF 3KCB DB57 DB56
2J21 2J1J
DB43 DB41
2J1G
3J3A 3J44 3J4E 3J2E DB66
DB42

3J3V
9KC0 2KCE 3KCA

3J3U

3J3Y 3J43
3J3R 3J42
3J3G 3J3B 3J45 3J4F 3J2F
9FA0

3KA1 5KC0 2KCD 3KC3 3J3H

3J48

3UF2
9GV4

2J24
3J3C
3J3D

3UFF
3UF1
3J47
3J46
3KC8
3KC9

2UR7
2UR5
3J49

1F00
2FAB 2FAC

1UA1
2UR6
3GVG

3KC2
3FA4 3FA3

3J40

3CVF
3CVG

7UF3

7UF8
2UF2
2KCJ 3KC7 3J41

3UFA
2J2W 2J33 2J2U 2J2D 2J2J 2J37

2GV4

2GVJ
2GV6

2GV8

2GVG
2GVC

2GVE
2GVA

2URE

2URB
2J35

5UR3
5UR1
2J3J
2URA

2EJ4

3UR3
2GV7

2GV9
2GV3

2GV5

2GVB

2GVD

2GVH
2GVF
3KA3
1CWC

2UR1
5UR5
1FA0

2UR0
2UR4

3UFV
3J3L
2FAA 2FA9

3FA2 5FA6 3J3M

7J04
3GD5

DB73
DB25
DB84
2UAB

5UR6

5UR2
3FA1 5FA7 3CV2
2FA0 DB76 DB79
2UAA

3CVM
DB26 3CVN
2EJ6

7EJ0
DB19

2J31
2RC9

DB21

2EJ1 3EJ1
2RB8

3EJ2
3RB0
2RCA

2EJ5
2RBT

3J2Z
2RBF 2RBE
2RBU 3RB3 2RBV
DB22 2EJ3
2RB7
1RA0
2RB6
9RB9

2J39 2J3D 2J30 2J29 2J2T 2J2V 2J2Z

9RB7
9RB6
1R01

1CV2
3CV8 3GD8
3CV9 3GD9
2RBD 2RB5
3KC1

DB10 2EJ7 2EJ2 3EJ0

3KC0
2URC 2URD 2UR8 2UR9
3RB12RBN
2RBP
2RBG

9RB8 2RBY

7J03
DB12
2RBA

2KCK
2RBB 2RB9

2RBM
2RCB
7RA0 DB11
DB71
5RA2

7RA1 7RC2
2RBC

3RA0

2J59

DB03 3FZ1
2RBH
2RBR
2RBS

2RBW 3CV7 2CV7

DB61
2RBJ 2RB2 3CV6
2RC8 DB09
2RB3

2RB4

2RC6

3CV4

3CVH 3CV5
3RA1

3CVS

3CVA
3CVB
9RB0

2RC7

3J2U
2J3K

DB17
DB00

7J00
2VW2 3VWN
2RB1 3VWM
2VW1 3VWW
2VWB
9VW4

1UA2
6RA0
2GYH 3GYD
2VW8 3VWV 3CVJ

3VWS
2VW5
2RBK

2VWA
2RBL 2GYG 3GYC

1M54
2VW7 3VWU
2VW9
2VW4 2UAP
3VWP 3VWR 2GYJ 3GYB
2VW6 3VWT
5RA1 2KCR 2VW3
2J3F 2J3H

7UAC
2VWD 3VW5 2GYF 3GYA
3VW6

1NA6

1NA5

1C32
2VWC 3VW3

2VWJ
3VW4
3VWJ
3CVU
3UAW 2GYE 3GY9
3RW6
3RW4
3RW8
3RW2
3KW2
3KW8
3KW4
3KW6

3VWH
1E01

2VWK 3VWK 2GYD 3GY8

2EA9

3VWL

9VW6
9VW5
3VW9 2GYC 3GY7
2VWF
2VWE
2VWH
3VW7

3VWD
3VWA

3VW8

3VWE
5UAA 2GYB 3GY3

1NA2

3CVT
2VWG 3VWB
5EF3

2FS2
2FS1
2EFN

3VWC

6UAB
1E00

5J05
2J42

2FZ6
2FZ3
3EG3

2EFP
1J00

3J50
3J09
6EF2
2EFM

2J41 2UAR

3FZ0
2FZ5
2J10 2J11

7UAE
2EFA
1NA8 2UAS
2EF9
3EG2

3EFW
1EF0

3UAM
2EFL

3EE2

5EF1
2EFZ
3EFM

3UV6
3EF2

2EFU 2EFB 2EFC

3CT1
6UAE

3CW8
3EFY
2EFR

2EFK

2CW3 3CTW
3EG1 3CTV

7CT1
3CW0

1GG1
2CW2 3CTU
2EFH 3CTP 3CTJ

1A05
2AAA
3EF0

3CR7
3CUA

5FS2
3CTB3CWE 2CW1 3CTZ 3CTR 2CT3

2FS4
3CR6

1GF1
3CW9 3CR5 3CWH
9AA3

3GFB 9GG4
3EF3
1H01

3CTS

5AA3
1CWE 7CS1
3CW2 3CR4 3CTK
2CS0 2CS3

1GF2
2EFJ
7EF0

5FS1
3HW4 3CU0

2FS3

3CP6 3CP8
3CS0
3CS1

3CTA

2AAB
3CT8 5GC2
3EF5 3CR8
3VC8

9AA5
3CS2 9CS1
2VCC

6CS1 6CS0 3CS4

2GCB

2GCA
7CT3

2GC8
3GC7
2GC6
2GC7
3GC3

3GC6

2GC5
2GC4
2VC2 3VC1

2AAC
3VC2 2VC1 3CTF 3CTH
6VC1
3CS3
6GG1 2GGA
6VC2 2CS2 3CUE
3EG0

3CT4
1E06

3EFT 2EFT

5EF4
2EFS 5EF0

1CS0 3CT5
3HW2
3HW1
3HW6

3CUW 2CS1 3CUD

1VC3 1VC2 3CT2
6EF1
6EF0

3EW0 3CT3
2EFG
3EFU

3EFN
3EFR
3EFV

3EFS

3EFP

3CWK
3CUY
2CW6 7CW1 3CT0
3CTT
5GC1
3HBM

6HA0 2GC1

1VA8
3CUM
6GG2

3GC4
2GC9
2CT4 2GC3
2HA6

3CUV 3UWD
3CR3 3HBN

9JA5
3HAN

3GC1

1CWD
1CS1

3CUU 3UWE 2UWW 6GG3

2UV7

6GC1
7UV0

2AA3

7GC1
3CUN
3CUR
3CUK
3CUS

3CUP

3CUL 3CUT 3UWF 3UWC 2UWV

1CT7

1P00

3GC9
1CTZ
6GG4 2AA2
6GC2
7UW2

1CW9 1CW8

1VC1 2TW0 2AA1

2GC2
3TW1
3TW0

1A04
6GG5 6GC3 3AA2
6VC0 9JA4

7JA0
9GC1
2HA9
7TW0

3VC0 9TW2 9JA3

3AA3
1CW5

2VC0 3GG5
9TW1 3GC2

2AA8 2AA5
3GG8 6GC4

7GG3

2AA9 2AA7
9GG3
9TW0

9GG2
9JA1

3GG6
2VC5
3VC5

7HA1

9AA2
3UWA
3VC9
1H02

2UV6

2GGB
6VC5
9TW5
9TW4
9TW3

2VCD 6UW0
2UWU
6UW1
2UWS

1VC6 2UWT 2UWR

9UW0 2GH8
2HAB

9GG1

9GC2
7GG4

7GG5
9JA6
3UWB 3CWD
2JA3 2EHR

INA0
3CU3
1CW4 1CW6 1CW7 3CWS
5EH0

2EHS
3GG7 3GG9

1VA4
3CU5
3CWT
7EH4
1VC4

2GHA
3CU4 9EHE
6VC3

1GGA
2VC6

3VC3 DCW4

7EHJ
INA1
3EHS
2VC3

2EHV
2GH9 3EHR
2EHU

1DH5 1C30 1C31

2VC4

3VC4

3EHT
3EHP
1GC1 3EHV 2EHJ 2EHW
7HA0

3EHM
2VC7 1VC5 6VC4 9EHD
3HAV

2EHE
3NAZ

2EHD
3NA9
3NA8
3NAB
3NAA
3HAW

9EHB
9EHA
3EHH
2UWA

1NA7 2EHH
7EH1
3HAL

5UW2

2UWJ 2UWH 9EH4 2EHC

3HB5
3UWH 3UWG

2UW9
5UW4

7UW0 2UWD 9EH3 3EHD

3HB6
1NA4
2UWB

2EHN
1VA6

3HB7 2UWC 3EHC

1NA3
2UWE
1H03

3UW3
1VC8 3HB8
3UW2

2PA1

9EH5
3EHG
2UWF

3EHE

3EHB
3EHA
3EHK

2EHA
2EHK
3HB9
2VCA 3VC7 2VCB

2UW2
3HBA 3UW7
6VC7

2UW0 3DH6

7EA0
3HBB 3UW8
2UWN

2HA2 2DH5
7UW1
3HBC
2UWP
7DH1

2DHA
2DH3
2DH4
2UW1

7DH0
2HA1

3DH7

2DHB
2UWL
3HA1

2HD6 2UW7 2UW4

2DH7

2DH2
9DH0
3HA0 2UWM 3DH1
5HD5

3HBF

3HBL
3HBJ
3HBG
3HBD

3HBH
3HBE

3HBK

3DH2
1VC7 6VC6 2HA5
2DH6
2UW5
2UW6

9DH3 9DH1 9DH2

2EHP
2VC9 3VC6 2VC8

3DH4
7NA3
3NBC

7HD0
2EAB

9HD2 2DH8

6DH2 1DH2 6DH1

3HDT 3NAT

3DH3
6NA1
3EA8
3EA7
3EAD
3EAC

1DH4
6DY0
1DY1 2EAA
1J50

6NA0
2DY1
2UWY

1DH3
2DY0
3DY0

1E02 1E03
3HDB
3HDE

2DH9
1H04 1H05

4 2011-12-16

SSB Layout top

3104 313 6555

19210_059_120425.eps
120425

2012-Sep-14 back to
div. table
 Circuit Diagrams and PWB Layouts QFU1.1E LA 10. EN 124

10-1-55 Layout bottom

3CY8 3CY6
3CY7

7CY62CYK
7CY2

3CY3
3GVC
9CY2

2GWM
3GWH

3GWF

3GWD
2GWK

3D80
3D81
2D90
3GVH

IGV6

ICY4
9GV5

FGV8

IGVE
IGV5
ID85

3CY9
FGD4 FGD6 FGD9 FGDA FGD5 FD52
9GW1
FD69 ID91
FGV9 IGV8
IGV7
IGV3 IGVC IGVD
3CY2 7CY1
FGD3 FGD7 FGD8 FGDG 9CY1 FD51 ID57

3CYT
2CYL
ICY2
ICY13CY4
ICY3
FCYE

FGS1

2CYF
2CY1

2CY9
2CY8
2CY7
2CY6
2CY5
2CY4
2CY3
FGS2

2CYC
2CYB

2CYA
2CYD
FD30

6VA2
6VA4
6VA7
6VA6
IGS6 ID96
FCY1

3GV5
3GV8 IGVB

3CYL

3CYJ

3CYM
3CYG
3CYH

3CYN
3CYE

3CYK

3CYP
FGV6 ID94

3CY5
IGV4 ID88

3CYC
3CYD
FGDE
IGD1 FGV7 3CYA

5UP6
FGDC

3GV1
FGDB 3CV3 IGVA FGUC FTA7

FGDD
IGS7 2CYE FD32

3CYB
FCY6 FCY7 FCY9 FCYB FCYD FVAH
9CY3 FVA3

2UPL
FGV1 FCY3 FCY5 FUPA
FGUB FD70
FTA6 FTA4 ITA1 FTA1 FTA3
IGD2
1GD1 FGV0
7GM2 FCY2 IUP4

FCYC
FCYA
FTA2 FD33
3GV6

9GM2
9GM1
FGV4 2CY2 FCY8

6UP4
ICY6

3CY1
IGS5 IUPF FD31

FGUE

2UCD
FGUD
FTA5 IGS3 2GV1
IGS4 IGS2 ID99
IGS1 IUP2 ID52 ID82
3GM7 ID50
3UC1 IUC3 ID51 FVA7

3VA6
IUPJ ID62
ID93
9GM4 FCV2
FVA0
FUAB
IUCB

3VAH
9GM3 FGVZ
FCV3

3VWF 3VWG

FCY4
FUAA
ID98 ID53

5UC1
FGW0

FUA9 IUC8

2UCE
IUC2
IUC0 FUB5
FGUA FVA8

ID63
FUA8 3GM5 IUA0 ID81

3UC0
IUBA
3GM6
IUBC ID75 ID76
IUC5

ID61
FUAL ID70

ID80
6UC13UC2

2UCH IUC7
IUBG
3UC8 IUC1
IUCP
IUBE ID97 ID83 FVA5

3UB7
3UC7
IUC6
7UC0 FUC0 7UC1 IUBB IUBD ID77
ID69

3UCF 2UCR
3UCB 3UCD
2UCM 2UCN
FVCF

3UCE 3UCA
FUA7
2UCP IUBF
ID66

3UCC
IUCA ID55 ID58 FVA2 FVA1

9UC0
IUC4

6UC0
FUA6 ID56
3UCR ID65 ID54

3UCP

6VA0
6VA3
6VA1
6VA5
IUC9
3UCG FD50
FUA4
3UC9 ID90
3UCN
IUCN ID87
FD66 FD64 ID79 ID84 ID78
FUA5 FVA6
IUCM
FD65
FD63
ID59 FVAG
FUA3 ID89
IUAM
FD67

FUA2
FVAF2VAJ 3VAF 6VAH
IVA1
FUA1 FVAE 3VAE 2VAH 6VAG FVCG

DFW2 3UCK
FUA0 3J2S 3J22 3J1N 3J1S 3J1C 3J18
IUCC IUCD FVAD 3VAC 6VAE
IUCE3UCL

7UC6
FVA4
IUAA 3J2T 3J23 3J1P 3J1T 3J1D 3J19
7UC5 3UCT 6VAD

FVAC
IJ0S 3VAB
IUCL 3UCH
FUAN
2UCV 3UCM 2UC3
3J1K IVA0

3UD1
DFW1 3VA9 2VAE 6VAC

IUCG
FJ03 3J1J 3UCW 2VAD
2FW6 FUC3 IUCH FUC2 2UC2
IUAD
6VAA

3UCY
3VAG

3UCZ
FVAB
3J1M

5FW3
2UC4
2UCU3UC6
FVAA
6UAF

3J1F

IUCJ
IUCK
3J1L

2FW3
IUAF
3J1E 3VA8 2VAB 6VA9

7UC8
IUCF
IUAC FVA9
DBA8 3J2A
IUAE
2FW5 DB33 DB51
3J28 3J2B
3VA7 2VA9 6VA8
DB94
IUAG 3J29

3FW8
IFW3 3J2D IUPG

2J83 2J7P

2J1D
DBA1
DBA3 3J2C
IUAB IFW5 FJ09 3J26 3J1U
FUAS IUFM IUFK DBA4 IUP7

2J7U
DB64 IUP6 FVCE
IFW1 DB62 2J19 3J27 3J1V
DB39 2J15DBA7 DB55
3UG1 IUFR
3FW4 DB91
3J2K IUP8
IUFL DB38

DB36
IUP3
3J2J

7FW1
IUFE
DB35 DB54 IUP1 AFA3
IUF3 IUFC
3J2L

2UP5

2UP6
2J86

2J1F 2J1U 2J81

2J1A
DBA6

2J17
3J12
IFA1

2J85
DB98 FUP1
3J2M

3J14
2J16
3J11

2J84
3UG2

2J1Q
2J1S

3J15
2J18
IUFN IURF IURD

5FA1
FGY2 IUP9 AFA2
IUFD FJ08 DB45 DB95 DB63
2J12
IKC1

2J89
DB01
2J1W 3J17 IKC0
FUAK 2UF53UGF IURK DB44 DB97 DB60 FFA9

IKC9
DB92
IUFJ

DB65
3J16

3FAB
IUF2
IURE ICVW 2J1K 2J1C 2J1L 3KCE 2KCS

2FAE 2FAK 2FAJ 2FAF 2FA7

3KCC 2FA8
2J1Z
IUR4 DB58
3J2G IKC3 IFA4

7FA1 3FAC
3UG0

DB59 DB99
IUR9 DKC1 AFA5
IUF6
IUF1 3J2H IFA3
2KC5 2KC0
3J2N

FCV1
3J4D 2J01 3J4L 3J34

2KC6
AFA4

3J3J 3J3P

3J4P 3J3Z
3J3W
IFW4

3J3K 3J3N
3J3F 3J38
2J2G

3J3E 3J39
IUFP IKC2
3J2P

3J32
3J33
3J4M IKC7
3J4C 3J35
2J93 5J0P 2J80

2KC4 2KC1
IUFA IUF0 3FW7 AFA0
3J4A 3J4J 3J4G IKC8

3FAA
IUF8 3FW3 3FW5 IFA5

3J4N
2UF4

IJ0R
3UFG

3J4H

2KC2
FJ00 3J4B 3J4K 3FA9

3FAD
3FW6
FUAH IUF7 IUF5 IKC6 3FA8
IURB
IUR0
IURC IFW2 AFA1
FKC1
7KA0 3KA2

2FAD
2GWG

2GWC
2GWE

2GWA
FJ0BDBC3 DBA9 FFA4

2GWJ

2GW8

2GW6

2GW4
2FW4
FUAJ 3UF7 IUR3
2J5A
DBB5
2KC7 2KC3 IKC5 3FA7

5KC6
IURA IFA6 3KA4
IUR2 DKC03KC6

2GWB
IGD3

2GWH

2GWD
2J2K

2GWF

2GW9

2GW7

2GW5

2GW3
IUFG

2FA4
IUFS 2KCH FFAB
IUR8
FFA8
DBC7
DB24 2KCP5KC5 FFA0 IKC4
FFAC FFA5

3CV1
FJ04
2J2F DB23 DBB9
FFA1 FFA7

2J96
3J02
2J00
IJ0G

2J4H

DB27
FCVA DB20
DBB4
3J31 FFA3

DB29
IUA1 2J04
5J0K 3J03 IJ0L 2J2H
DB05DB07
FFA6

2J2C
DB70

7FA0
2J4Z 3J04 3J30
FFA2

2FA2
FEJ1 2J4W 2J02 2J2E DBC0

2J36
2J38
FEJ5 FFAA

2J4L
2J98
FGV5 IJ14 DB77
IJ00 2J34 2J2L 2J32
DBC6
FEJ4
FEJ2 DB85 DB74 DB30
FEJ3
FEJ6 IJ0M

2RAF
2J5K 2J5D
DB86

IRA0
3CVR 3CVP
DB80 IRA9

2RAD
2RAE

2RAW
2RAV
9GA2 DB75 2J7Z
DB46 FJ0ADBC2

5FA0
IRA4
FEJ0 2J2M DBB7
IFA0
2FA1 IRA1

2RAP
DB78 DB47
2J7Y

2RC2
FURA 2RAK

2J4J
2RAR

3RA7
3RA8
FCV4
DB18
DB83 DB88 DB89
2RC1

2J1T
2J2N

2J2P
2J74 2J5U 2J09

DB68
DB04
IJ0P
3J01 2J7V DBB1
FRC0
2RAN 2RAC 2RAS FRA7
3CVZ 2J23

2J88
2J5G

2J87
2J6A

7RC0
2J03 9RC2

3J00

2RAU
IRC1
FUR1 FCV5
2J4Y 2J7W 2J5L 3J2W

2J4F
DB87 DBB6
FCV7 2J6S 2J22

2RC4
2RAT
2RAG

3CVV

2RC0
DBB3 DB02
2J65

2J4N 2J7L
2J5M 2J2B
2J7H

9CV1 9CV0

5J0E
FCV6

2J6M
DB13

2J7B
5J0G DB82

5J0D
DB96

2J4G
ICV1 IJ11 2J72 DB16
IJ0N
5J0F DB14 DB15

IRC0
2J6F
ICV2
DB72 DBB2 2RAB

2J6U
2J6Z 2J7J
2J2R

2J5B
DB67 2RA0

2J28
FCV8 2J6W 2J99 IRC23RC2
3J2V

2J7R
2RAM

2J5N
3RA2

2J6L

2RC3
2J94

2J05

3RC1
2J2Y

2RAH
2J68 IRA7

2J07
3J05
2J06

3J06
FJ14
3UA6

FCV9 2J4P 2J76 FJ05 DB69 2J2A DBC4 DBB8 2RAA FRA8
2J73 2RB0

2J3G 2J7F
FJ15 DBC5
DBC1 FRC1
2RAL FRA1
IJ04 2J3U 2J4M 2J6C 2J6R 2J5F 2J3A 2J3C2J3E 2J2S 2J3B 2RA1

2RCE
2RA9
5J03

2J4E
DB08
2J75 2J5C FRA2

2RAY
2J3T IJ0D 2J4D 2J78 FRA3

7UAF 2J4A
IJ0B 2J7K 2J7A 2J5H FRA6 3RA4 2RA2
5J0A

2RA3
2RA5
2RA6
2RA8

2RA7
DBB0
2J49 2J6G 2J67 2J6T FRA4
2J4C

2J70
7RC1
IJ03 2J4B 2J71 2RC5 FRA5
2J3P 5J0B
FGYA
2J3S

2J7C
2J3R IJ02 2J7D IRC3

2J7G

2RA4
2RCD
5J02 5J01
IJ0C 2J6V 2J6H

IJ13
3UAP 3UAN 9J03 2J90 2J77
FJ01
2J5R 5RA0 IRA8
FGY9 IJ12 2J79 2J5W FRA0 2RAJ

2J3Y
2J6P

2J6Y
2J69

2J5Z
DB81
FUAT
IJ01
9J04 2J91 5J00 2J6J 2J6N 3RA6 IRA2
2J3N

2RCC
5J0J
2J3M 2J6B IRA33RA3

2J66

2J60
FGY8
5RC0
5J09 2J48 2J46 IJ09 5J08 2J63 5J04 2J3W 2J7E
3UAT

2J45
2UAL

5KC7

FJ02
6UAC 3UAS

2J62
IVW2

2J4U
IJ0A
FGY7 FUAP IUAS
7UAB 2J4V

2J5Y
5J0M
5J0C 2J64
6UAD

FNAC FNAJ IJ05 IJ0F 2J61

IVW1 2J47 2J6D IJ0E 3PW4
2UAM

IUAJ

3PW2
2J97
FGY6 IUAP 5J0L IJ0H 2J5S FJ0H

2J4S
2UAN 3PC0 FEA4
2J5V 2J5T 2J3V 2J6E

2J4T
FNAH
IVW7 3PW3

3RW1
3RW7
3RW3
3RW5
3KW7
3KW3

3KW1
3KW5
2J40 3CUC

5J0H
IUAN3UAY FNAB
2J54 3PW5
FGY5 IVW8 2J52 2J51 2J50 2J43
3UAV

2J44

IJ0J
2UAK 7UAA

2J5P
3UA5

3PC1 IVW4 IJ0K

3PW1
IUAR

IUAT IUAL FEA1

IJ06
9VW1
3UAR FNAA FNAG
2J3Z
5J0N 2J55 2J53

2FZ4
FNAD IVW6 FJ0G FJ0F
FGY4 FJ16

IVW3
IUAK IUAV
3ECH

2FZ1
2FZ2

2J4R
9VW2
IJ08 IJ07 IJ10
FGY3 FNA8 FNAE FNA9 IVW5 FJ10 5J07 2J56 2J58 5J06 FJ0J FEA2

FEFE FEA3

5EF7
3J51
3J08
3J07 3J52
FEFC

3NBD
7NA5
3GG3

3GG2

9PAB 3PAL

3PA7

3PAV

3PAS

3PAE
9PAA
3PAT
3PAY

3PAP
3PAF

2HW2 3HW5
3PA5

3PAN
3PAM

3PAU
3PAW

3PAR
3PAC
3PAD

3PAB
3PA3

3CW3

2AW0 2CW4
3PA8 DEF0

2EF2

2EFF
FUAR IHW2 FEF2 FEF1
IEE1

FEFA
IGG2 IEE0
3CW7

FCT5

FEF0
FCWZ FEFB
3NBE

5EF6
7GG2

3CL4

3CWN

2EF3
FGGA 3CL2 3CL0 3CTM FEF4

7CT2

3AW1
FCT7
3AW0 3CTY 2EF8
2PA3

7PA2

3CTG

FCT2
3CL7 3CL5
7PA1
2PA2

3CU1 2EF6 FEF8

FGGB FCT4 IEF1
3CT9 ICT3 3CW6 DCW1 3CWF FCS5
IAA5 3CL3 3CL1

2EF4
FCT1 3CTE 2CT2 3CTD 3CWL 2CW5 3CWJ FEF3

5EF5
3CL8 3CL6
2GGW

3GF4 FCS4
3PA2
3PA4

FHAH
2GGU
2GGY

2GGV

FEF9
5GG4
2GGD

2GH1

3CW4 FCS3
2GG1
2GG5

IAA6 2EF5
3PA6

3PA9

3HDK
FGF7 3CW5
3GF5 3PAA 3CWA
2HW1 2EF1 2EF0

FVC3
IHDJ
FGG8

3CUB 3CWM IHW1

3HW3 2EF7
7GG1
FGG5

FEF6
FGF6 FGC2 FCW0 3CWB 9EF1

3EF6
IAA7 FGG9 2EFD 3HDG
3CU7
3GG1
2GH7

3CU2 9EF2 FCW7

2EFE
FGF5 ICT1 3CWG FCWR FCWS FHW0
FGF4 3CU6 FCWW 3CR1

5HD4
2HD5
3CWC FEF7 3EF7 FHD8

FCT6
ICW1 FCW6
FGF1 FCWL FCS2
3CU9
FGC1
7EF1

2EFV

3CR0
FCWK FCS0
FGF8 3GF7 3CU8 FEF5 FVC5 3HDS
FVC6
3GF1